cpu/mem.opc whitespace tidy

cpu/
	* mep.opc: Whitespace and formatting.
opcodes/
	* mep-asm.c: Regenerate.
	* mep-dis.c: Regenerate.

diff --git a/cpu/mep.opc b/cpu/mep.opc
index 6b264ccb73ecf35bcc2fe7cfcb2b234839bdc420..ebe119ae339ec087e79a620c03485ed28fec00d3 100644 (file)
--- a/cpu/mep.opc
+++ b/cpu/mep.opc
@@ -82,7 +82,7 @@ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask;
 )
 
 /* A mask for all ISAs executed by a VLIW coprocessor.  */
-#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask 
+#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask
 extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask;
 
 #define MEP_INSN_COP_P(insn) ( \
@@ -533,7 +533,7 @@ parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp,
          break;
        default:
          /* Safe assumption?  */
-         abort (); 
+         abort ();
        }
       errmsg = cgen_parse_address (cd, strp, opindex, reloc,
                                   NULL, &value);
@@ -579,7 +579,7 @@ parse_cdisp10 (CGEN_CPU_DESC cd,
   if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5)
     wide = 1;
 
-  if (strncmp (*strp, "0x0", 3) == 0 
+  if (strncmp (*strp, "0x0", 3) == 0
       || (**strp == '0' && *(*strp + 1) != 'x'))
     have_zero = 1;
 
@@ -646,7 +646,7 @@ mep_cgen_expand_macros_and_parse_operand
 
 static char *
 str_append (char *dest, const char *input, int len)
-{  
+{
   char *new_dest;
   int oldlen;
 
@@ -682,10 +682,10 @@ expand_macro (arg *args, int narg, const macro *mac)
   /*  printf("expanding macro %s with %d args\n", mac->name, narg + 1); */
   while (*e)
     {
-      if (*e == '`' && 
-         (*e+1) && 
-         ((*(e + 1) - '1') <= MAXARGS) &&
-         ((*(e + 1) - '1') <= narg))
+      if (*e == '`'
+         && (*e+1)
+         && ((*(e + 1) - '1') <= MAXARGS)
+         && ((*(e + 1) - '1') <= narg))
        {
          result = str_append (result, mark, e - mark);
          mac_arg = (*(e + 1) - '1');
@@ -706,7 +706,7 @@ expand_macro (arg *args, int narg, const macro *mac)
       free (result);
       return rescanned_result;
     }
-  else 
+  else
     return result;
 }
 
@@ -731,8 +731,8 @@ expand_string (const char *in, int first_only)
       switch (state)
        {
        case IN_TEXT:
-         if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) 
-           {         
+         if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0))
+           {
              pmacro = lookup_macro (in + 1);
              if (pmacro)
                {
@@ -743,7 +743,7 @@ expand_string (const char *in, int first_only)
                  while (*in == ' ') ++in;
                  if (*in != '(')
                    {
-                     state = IN_TEXT;                
+                     state = IN_TEXT;
                      pmacro = NULL;
                    }
                  else
@@ -752,7 +752,7 @@ expand_string (const char *in, int first_only)
                      narg = 0;
                      args[narg].start = in + 1;
                      args[narg].len = 0;
-                     mark = in + 1;                          
+                     mark = in + 1;
                    }
                }
            }
@@ -793,9 +793,9 @@ expand_string (const char *in, int first_only)
                  /* Fall through.  */
                default:
                  args[narg].len++;
-                 break;                  
+                 break;
                }
-           } 
+           }
          else
            {
              if (*in == ')')
@@ -803,14 +803,13 @@ expand_string (const char *in, int first_only)
              if (narg > -1)
                args[narg].len++;
            }
-         
        }
       ++in;
     }
-  
+
   if (mark != in)
     result = str_append (result, mark, in - mark);
-  
+
   return result;
 }
 
@@ -849,10 +848,10 @@ mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex,
     {
       if (strstr (*strp_in, str))
        /* A macro-expansion was pulled off the front.  */
-       *strp_in = strstr (*strp_in, str);  
+       *strp_in = strstr (*strp_in, str);
       else
        /* A non-macro-expansion was pulled off the front.  */
-       *strp_in += (str - hold); 
+       *strp_in += (str - hold);
     }
 
   free (hold);
@@ -860,7 +859,7 @@ mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex,
   return errmsg;
 }
 
-#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); 
+#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand);
 
 /* -- dis.c */
 
@@ -945,11 +944,11 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
   if (corelength > 0)
     {
       int my_status = 0;
-        
+
       for (i = 0; i < corelength; i++ )
        insnbuf[i] = buf[i];
       cd->isas = & MEP_CORE_ISA;
-        
+
       my_status = print_insn (cd, pc, info, insnbuf, corelength);
       if (my_status != corelength)
        {
@@ -958,10 +957,10 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
        }
       status += my_status;
 
-      /* Print the + to indicate that the following copro insn is   */
-      /* part of a vliw group.                                      */
+      /* Print the + to indicate that the following copro insn is
+        part of a vliw group.  */
       if (copro1length > 0)
-       (*info->fprintf_func) (info->stream, " + "); 
+       (*info->fprintf_func) (info->stream, " + ");
     }
 
   /* Now all that is left to be processed is the coprocessor insns
@@ -973,7 +972,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
   if (copro1length > 0)
     {
       int my_status = 0;
-        
+
       for (i = corelength; i < corelength + copro1length; i++ )
        insnbuf[i - corelength] = buf[i];
 
@@ -992,7 +991,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
          break;
        case 8:
          cd->isas = & MEP_COP64_ISA;
-         break; 
+         break;
        default:
          /* Shouldn't be anything but 16,32,48,64.  */
          break;
@@ -1025,7 +1024,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
 
       for (i = corelength + copro1length; i < 64; i++)
        insnbuf[i - (corelength + copro1length)] = buf[i];
-      
+
       switch (copro2length)
        {
        case 2:
@@ -1038,7 +1037,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
          cd->isas = 1 << ISA_EXT_COP1_48;
          break;
        case 8:
-         cd->isas = 1 << ISA_EXT_COP1_64; 
+         cd->isas = 1 << ISA_EXT_COP1_64;
          break;
        default:
          /* Shouldn't be anything but 16,32,48,64.  */
@@ -1066,29 +1065,29 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
     return status;
 }
 
-/* The two functions mep_examine_vliw[32,64]_insns are used find out 
-   which vliw combinaion (16 bit core with 48 bit copro, 32 bit core 
-   with 32 bit copro, etc.) is present.  Later on, when internally   
-   parallel coprocessors are handled, only these functions should    
-   need to be changed.                                               
+/* The two functions mep_examine_vliw[32,64]_insns are used find out
+   which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
+   with 32 bit copro, etc.) is present.  Later on, when internally
+   parallel coprocessors are handled, only these functions should
+   need to be changed.
+
+   At this time only the following combinations are supported:
 
-   At this time only the following combinations are supported: 
-   
    VLIW32 Mode:
    16 bit core insn (core) and 16 bit coprocessor insn (cop1)
    32 bit core insn (core)
    32 bit coprocessor insn (cop1)
    Note: As of this time, I do not believe we have enough information
          to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
-         no 16 bit coprocessor insns have been specified.  
+         no 16 bit coprocessor insns have been specified.
 
    VLIW64 Mode:
    16 bit core insn (core) and 48 bit coprocessor insn (cop1)
    32 bit core insn (core) and 32 bit coprocessor insn (cop1)
    64 bit coprocessor insn (cop1)
-  
+
    The framework for an internally parallel coprocessor is also
-   present (2nd coprocessor insn is cop2), but at this time it 
+   present (2nd coprocessor insn is cop2), but at this time it
    is not used.  This only appears to be valid in VLIW64 mode.  */
 
 static int
@@ -1099,9 +1098,9 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   int corebuflength;
   int cop1buflength;
   int cop2buflength;
-  bfd_byte buf[CGEN_MAX_INSN_SIZE];  
+  bfd_byte buf[CGEN_MAX_INSN_SIZE];
   char indicator16[1];
-  char indicatorcop32[2]; 
+  char indicatorcop32[2];
 
   /* At this time we're not supporting internally parallel coprocessors,
      so cop2buflength will always be 0.  */
@@ -1140,16 +1139,16 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
     {
       if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)
        {
-          /* We have a 32 bit copro insn.  */
-          corebuflength = 0;
+         /* We have a 32 bit copro insn.  */
+         corebuflength = 0;
          /* All 4 4ytes are one copro insn. */
-          cop1buflength = 4;
+         cop1buflength = 4;
        }
       else
        {
-          /* We have a 32 bit core.  */
-          corebuflength = 4;
-          cop1buflength = 0;
+         /* We have a 32 bit core.  */
+         corebuflength = 4;
+         cop1buflength = 0;
        }
     }
   else
@@ -1229,16 +1228,16 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
       if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07
          && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))
        {
-          /* We have a 64 bit copro insn.  */
-          corebuflength = 0;
+         /* We have a 64 bit copro insn.  */
+         corebuflength = 0;
          /* All 8 bytes are one copro insn.  */
-          cop1buflength = 8;
+         cop1buflength = 8;
        }
       else
        {
-          /* We have a 32 bit core insn and a 32 bit copro insn.  */
-          corebuflength = 4;
-          cop1buflength = 4;
+         /* We have a 32 bit core insn and a 32 bit copro insn.  */
+         corebuflength = 4;
+         cop1buflength = 4;
        }
     }
   else
@@ -1290,10 +1289,10 @@ print_slot_insn (CGEN_CPU_DESC cd,
       if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
           && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
          || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
-        {
-          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+       {
+         insn_list = CGEN_DIS_NEXT_INSN (insn_list);
          continue;
-        }
+       }
 
       if ((insn_value & CGEN_INSN_BASE_MASK (insn))
          == CGEN_INSN_BASE_VALUE (insn))
@@ -1460,13 +1459,13 @@ mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
          for (i = 0; i <= mep_config_index; i++)
            if (mep_config_map[i].name == NULL)
              break;
-         
+
          if (i < mep_config_index)
            {
              opcodes_error_handler (_("illegal MEP INDEX setting '%x' in ELF header e_flags field"), mep_config_index);
              mep_config_index = 0;
            }
-         
+
          cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
          if (cop_type == EF_MEP_COP_IVC2)
            ivc2 = 1;

diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index 219c4488f76e242c12f70f4341e66fa96386ff3f..f3c5f797433a5a1d5773982fe52c1bb1071a3bd4 100644 (file)
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -638,10 +638,10 @@ expand_macro (arg *args, int narg, const macro *mac)
   /*  printf("expanding macro %s with %d args\n", mac->name, narg + 1); */
   while (*e)
     {
-      if (*e == '`' &&
-         (*e+1) &&
-         ((*(e + 1) - '1') <= MAXARGS) &&
-         ((*(e + 1) - '1') <= narg))
+      if (*e == '`'
+         && (*e+1)
+         && ((*(e + 1) - '1') <= MAXARGS)
+         && ((*(e + 1) - '1') <= narg))
        {
          result = str_append (result, mark, e - mark);
          mac_arg = (*(e + 1) - '1');
@@ -759,7 +759,6 @@ expand_string (const char *in, int first_only)
              if (narg > -1)
                args[narg].len++;
            }
-
        }
       ++in;
     }

diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index 72c6c101bfd9f3d7744e0770a48519aedf568b66..91ea29b7c39e1dc7d69c332c652cbd1592531ea0 100644 (file)
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -154,8 +154,8 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
        }
       status += my_status;
 
-      /* Print the + to indicate that the following copro insn is   */
-      /* part of a vliw group.                                      */
+      /* Print the + to indicate that the following copro insn is
+        part of a vliw group.  */
       if (copro1length > 0)
        (*info->fprintf_func) (info->stream, " + ");
     }
@@ -336,16 +336,16 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
     {
       if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)
        {
-          /* We have a 32 bit copro insn.  */
-          corebuflength = 0;
+         /* We have a 32 bit copro insn.  */
+         corebuflength = 0;
          /* All 4 4ytes are one copro insn. */
-          cop1buflength = 4;
+         cop1buflength = 4;
        }
       else
        {
-          /* We have a 32 bit core.  */
-          corebuflength = 4;
-          cop1buflength = 0;
+         /* We have a 32 bit core.  */
+         corebuflength = 4;
+         cop1buflength = 0;
        }
     }
   else
@@ -425,16 +425,16 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
       if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07
          && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))
        {
-          /* We have a 64 bit copro insn.  */
-          corebuflength = 0;
+         /* We have a 64 bit copro insn.  */
+         corebuflength = 0;
          /* All 8 bytes are one copro insn.  */
-          cop1buflength = 8;
+         cop1buflength = 8;
        }
       else
        {
-          /* We have a 32 bit core insn and a 32 bit copro insn.  */
-          corebuflength = 4;
-          cop1buflength = 4;
+         /* We have a 32 bit core insn and a 32 bit copro insn.  */
+         corebuflength = 4;
+         cop1buflength = 4;
        }
     }
   else
@@ -486,10 +486,10 @@ print_slot_insn (CGEN_CPU_DESC cd,
       if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
           && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
          || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
-        {
-          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+       {
+         insn_list = CGEN_DIS_NEXT_INSN (insn_list);
          continue;
-        }
+       }
 
       if ((insn_value & CGEN_INSN_BASE_MASK (insn))
          == CGEN_INSN_BASE_VALUE (insn))
@@ -656,13 +656,13 @@ mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
          for (i = 0; i <= mep_config_index; i++)
            if (mep_config_map[i].name == NULL)
              break;
-         
+
          if (i < mep_config_index)
            {
              opcodes_error_handler (_("illegal MEP INDEX setting '%x' in ELF header e_flags field"), mep_config_index);
              mep_config_index = 0;
            }
-         
+
          cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
          if (cop_type == EF_MEP_COP_IVC2)
            ivc2 = 1;