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make note that it is for latch mode
author
Miodrag Milanovic
<mmicko@gmail.com>
Wed, 18 Sep 2019 15:48:16 +0000
(17:48 +0200)
committer
Miodrag Milanovic
<mmicko@gmail.com>
Wed, 18 Sep 2019 15:48:16 +0000
(17:48 +0200)
techlibs/anlogic/cells_sim.v
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diff --git
a/techlibs/anlogic/cells_sim.v
b/techlibs/anlogic/cells_sim.v
index cea9f8c11668640cff2af5511c00c467811ffb07..0fba435720456eb2d161249d789d72461fe7b906 100644
(file)
--- a/
techlibs/anlogic/cells_sim.v
+++ b/
techlibs/anlogic/cells_sim.v
@@
-55,6
+55,7
@@
module AL_MAP_SEQ (
end
else
begin
+ // DFFMODE == "LATCH"
if (SRMODE == "ASYNC")
begin
always @(clk_ce, srmux)