\begin{frame}{\subsecname}
\begin{itemize}
\item Reading and elaborating the design
-\item High-level synthesis and optimization
+\item Higher-level synthesis and optimization
\begin{itemize}
\item Converting {\tt always}-blocks to logic and registers
\item Perform coarse-grain optimizations (resource sharing, const folding, ...)
\end{itemize}
\item Convert remaining logic to bit-level logic functions
\item Perform optimizations on bit-level logic functions
-\item Map bit-level logic and register to gates from cell library
+\item Map bit-level logic gates and registers to cell library
\item Write results to output file
\end{itemize}
\end{frame}
#
hierarchy
-# recommended form. fail if parts of the design hierarchy are missing. remove
-# everything that is unreachable by the top module. mark the top module.
+# recommended form. fails if parts of the design hierarchy are missing, removes
+# everything that is unreachable from the top module, and marks the top module.
#
hierarchy -check -top top_module
\end{lstlisting}
# into one multi-port memory cell.
memory_collect
-# this takes the multi-port memory cells and transforms it to address decoder
+# this takes the multi-port memory cell and transforms it to address decoder
# logic and registers. This step is skipped if "memory" is called with -nomap.
memory_map
\end{lstlisting}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 2/2}
-\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
+\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -5cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
fsm_extract
fsm_opt
-opt_clean
+clean
fsm_opt
fsm_expand # if got option -expand
-opt_clean # if got option -expand
+clean # if got option -expand
fsm_opt # if got option -expand
fsm_recode # unless got option -norecode
to map all RTL cell types to a generic library of built-in logic gates and registers.
\bigskip
-\begin{block}{The build-in logic gate types are:}
+\begin{block}{The built-in logic gate types are:}
{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
\end{block}
\begin{itemize}
\item Yosys provides commands for each phase of the synthesis.
\item Each command solves a (more or less) simple problem.
-\item Complex command are often only front-ends to simple commands.
+\item Complex commands are often only front-ends to simple commands.
\item {\tt proc; opt; memory; opt; fsm; opt; techmap; opt; abc;;}
\end{itemize}
\sectionpage
\end{frame}
+\iffalse
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Representations of (digital) Circuits}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\fi
\subsection{Levels of Abstraction for Digital Circuits}
\only<6>{Physical Gate Level}%
\only<7>{Switch Level}}
\only<1>{
- Overall view of the circuit: E.g. block-diagrams or instruction-set architecture descriptions
+ Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions.
}%
\only<2>{
Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
\only<6>{
Netlist of cells that actually are available on the target architecture
(such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
- area and/or and/or speed (static timing or number of logic levels).
+ area, power, and/or speed (static timing or number of logic levels).
}%
\only<7>{
Netlist of individual transistors.
This scripts contain three types of commands:
\begin{itemize}
\item {\bf Frontends}, that read input files (usually Verilog).
- \item {\bf Passes}, that perform transformation on the design in memory.
- \item {\bf Backends}, that write the design in memory to a file (various formats are available, e.g. Verilog, BLIF, EDIF, SPICE, BTOR, etc.).
+ \item {\bf Passes}, that perform transformations on the design in memory.
+ \item {\bf Backends}, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, \dots).
\end{itemize}
\bigskip
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Example Problem}
+\subsection{Example Project}
-\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
-\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
-\end{columns}
+\begin{frame}[t]{\subsecname}
+The following slides cover an example project. This project contains three files:
+\begin{itemize}
+\item A simple ASIC synthesis script
+\item A digital design written in Verilog
+\item A simple CMOS cell library
+\end{itemize}
+\vfill
+Direct link to the files: \\ \footnotesize
+\url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Example Synthesis Script}
-
-\begin{frame}[t]{\subsecname}
+\begin{frame}[t]{\subsecname{} -- Synthesis Script}
\setbeamercolor{alerted text}{fg=white,bg=red}
\medskip
{\color{YosysGreen}\# mapping to internal cell library}\\
\boxalert<9>{techmap}; \boxalert<10>{opt}
-
-\bigskip
-\it continued\dots
\end{minipage}
\begin{minipage}[t]{5cm}
\tt\scriptsize
}%
\only<2>{
Elaborate the design hierarchy. Should always be the first
- command after reading the design.
+ command after reading the design. Can re-run AST front-end.
}%
\only<3>{
Convert ``processes'' (the internal representation of behavioral
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
+\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
+\end{frame}
+
+\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
+\end{columns}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
\subsection{Running the Synthesis Script}
\begin{frame}[t, fragile]{\subsecname{} -- Step 1/4}
clean
\end{verbatim}
-\vfill
-\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
+\vfill\hfil
+\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Command reference:
\begin{itemize}
\item Use ``{\tt help}'' for a command list and ``{\tt help \it command}'' for details.
-\item Or run ``{\tt yosys -H}'' and ``{\tt yosys -h \it command}''.
+\item Or run ``{\tt yosys -H}'' or ``{\tt yosys -h \it command}''.
\item Or go to \url{http://www.clifford.at/yosys/documentation.html}.
\end{itemize}
module cam(clk, wr_enable, wr_addr, wr_data, rd_data, rd_addr, rd_match);
parameter WIDTH = 8;
parameter DEPTH = 16;
- localparam ADDR_BITS = $clog2(DEPTH);
+ localparam ADDR_BITS = $clog2(DEPTH-1);
input clk, wr_enable;
input [ADDR_BITS-1:0] wr_addr;
do not break old ones is a high priority in Yosys.
\bigskip
-There are two external test suites build for Yosys: VlogHammer and yosys-bigsim
+Two external test suites have been built for Yosys: VlogHammer and yosys-bigsim
(see next slides)
\bigskip
\begin{frame}[fragile]{\subsecname{} -- VlogHammer}
VlogHammer is a Verilog regression test suite developed to test the different
-subsystems in Yosys by comparing them to each other and the implementations
-generated by some proprietary tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
+subsystems in Yosys by comparing them to each other and to the output created
+by some other tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
\bigskip
Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology mapping,
\end{lstlisting}
\bigskip
-Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 20 bugs in
-the proprietary tools used as external reference where found and reported.
+Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 50 bugs in
+the other tools used as external reference where found and reported so far.
\end{frame}
\begin{frame}{\subsecname{} -- yosys-bigsim}
Verilog code and synthesis results.
\bigskip
-The following designs are part of yosys-bigsim:
+The following designs are included in yosys-bigsim (excerpt):
\begin{itemize}
\item {\tt openmsp430} -- an MSP430 compatible 16 bit CPU
\item {\tt aes\_5cycle\_2stage} -- an AES encryption core
\subsection{Benefits of Open Source HDL Synthesis}
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Cost (also applies to ``free as in free beer'' solutions)
+\item Availablity and Reproducability
+\item Framework- and all-in-one-aspects
+\item Educational Tool
+\end{itemize}
+
+\bigskip
+
+Yosys is open source under the ISC license.
+\end{frame}
+
\begin{frame}{\subsecname{} -- 1/3}
\begin{itemize}
\item Cost (also applies to ``free as in free beer'' solutions): \smallskip\par
\begin{frame}{\subsecname{} -- 3/3}
\begin{itemize}
\item Educational Tool: \smallskip\par
-Propritaery synthesis tools are at times where secretive about their inner
-workings. They often are ``black boxes'' where a design goes in and synthesis
-results come out. Yosys is very open about its internals and it is easy to
-observe the different steps of synthesis.
+Propritaery synthesis tools are at times very secretive about their inner
+workings. They often are ``black boxes''. Yosys is very open about its
+internals and it is easy to observe the different steps of synthesis.
\end{itemize}
\bigskip
-\begin{block}{BTW: Yosys is licensed under the ISC license:}
+\begin{block}{Yosys is licensed under the ISC license:}
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{What the Yosys project needs from you}
+\subsection{Yosys needs you}
\begin{frame}{\subsecname}
-We need you as an active user:
+\dots as an active user:
\begin{itemize}
-\item Use Yosys for on your own designs
+\item Use Yosys for on your own projects
\item .. even if you are not using it as final synthesis tool
\item Join the discussion on the Subreddit
\item Report bugs and send in feature requests
\end{itemize}
\bigskip
-We need you as a developer:
+\dots as a developer:
\begin{itemize}
-\item Use Yosys as environment for your research work
+\item Use Yosys as environment for your (research) work
\item .. you might also want to look into ABC for logic-level stuff
\item Fork the project on github or create loadable plugins
-\item We desperately need a VHDL frontend or a VHDL-to-Verilog converter
+\item We need a VHDL frontend or a good VHDL-to-Verilog converter
\end{itemize}
\end{frame}
-\section{Programming Yosys Extensions}
+\section{Writing Yosys extensions in C++}
\begin{frame}
\sectionpage
\subsection{Simplified RTLIL Entity-Relationship Diagram}
\begin{frame}{\subsecname}
-Between passses and frontends/backends the design in stored in Yosys' internal RTLIL (RTL Intermediate Language) format. For
-writing Yosys extensions it is key to understand this format.
+Between passses and frontends/backends the design is stored in Yosys' internal
+RTLIL (RTL Intermediate Language) format. For writing Yosys extensions it is
+key to understand this format.
\bigskip
\begin{center}
\subsection{RTLIL without memories and processes}
\begin{frame}[fragile]{\subsecname}
-After the command {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are left with a much simpler version of RTLIL:
+After the commands {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are
+left with a much simpler version of RTLIL:
\begin{center}
\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
\end{center}
\bigskip
-Many command simply choose to only work on this simpler version:
+Many commands simply choose to only work on this simpler version:
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
if (module->processes.size() != 0 || module->memories.size() != 0)
log_error("This command does not operate on modules with processes "
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
struct RTLIL::SigChunk {
RTLIL::Wire *wire;
- RTLIL::Const data; // only used if wire == NULL, LSB at index 0
+ RTLIL::Const data; // only used if wire == NULL
int width, offset;
...
};
\subsubsection{The RTLIL::Cell Structure}
\begin{frame}[t, fragile]{\subsubsecname (1/2)}
-The {\tt RTLIL::Cell} strcut represents an instance of a module or library cell.
+The {\tt RTLIL::Cell} struct represents an instance of a module or library cell.
\smallskip
The ports of the cell
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname (2/2)}
-Simulation models (i.e. {\it documentation\/}) for the internal cell library:
+Simulation models (i.e. {\it documentation\/} :-) for the internal cell library:
\smallskip
\hskip2em {\tt yosys/techlibs/common/simlib.v} and \\
\bigskip
The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable
-width. This so-called {\it RTL cells\/} are the cells described in {\tt simlib.v}.
+width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}.
\bigskip
-The upper-case cell types (such as {\tt \$\_AND\_}) single-bit cells that are not
-parameterized. This so-called {\it internal Logic Gates} are the cells described
+The upper-case cell types (such as {\tt \$\_AND\_}) are single-bit cells that are not
+parameterized. This so-called {\it Internal Logic Gates} are the cells described
in {\tt simcells.v}.
\bigskip
projects / yosys.git / commitdiff