i965/gen6/gs: implement GS_OPCODE_FF_SYNC_SET_PRIMITIVES opcode

This opcode will be used when filling FF_SYNC header before
emitting vertices and their data.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 7039174e07868ac703da3849b2648ead47db3793..e4868d1c29219b140fe5e42d727187f2590a3d51 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1064,6 +1064,21 @@ enum opcode {
     * - src is the register that holds the destination indices value.
     */
    GS_OPCODE_SVB_SET_DST_INDEX,
+
+   /**
+    * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
+    * Used in gen6 for transform feedback.
+    *
+    * - dst will hold the register with the final Mx.0 value.
+    *
+    * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
+    *
+    * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
+    *
+    * - src2 is the value to hold in M0: number of SO vertices to write
+    *   and number of SO primitives needed.
+    */
+   GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
 };
 
 enum brw_derivative_quality {

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 25f73356421c2f37501181441d49103602e3f41c..0a33063e966dade37ea5ccd9cfee957d18a4b305 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -532,6 +532,8 @@ brw_instruction_name(enum opcode op)
       return "gs_svb_write";
    case GS_OPCODE_SVB_SET_DST_INDEX:
       return "gs_svb_set_dst_index";
+   case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
+      return "gs_ff_sync_set_primitives";
 
    default:
       /* Yes, this leaks.  It's in debug code, it should never occur, and if

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 2a2f7752c151d7b9d4d6700f9f2c436660de6307..d3d374d14c2dd6cb5d55a8900a4cae6decf701dc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -669,6 +669,10 @@ private:
    void generate_gs_prepare_channel_masks(struct brw_reg dst);
    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
    void generate_gs_get_instance_id(struct brw_reg dst);
+   void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
+                                           struct brw_reg src0,
+                                           struct brw_reg src1,
+                                           struct brw_reg src2);
    void generate_gs_ff_sync(vec4_instruction *inst,
                             struct brw_reg dst,
                             struct brw_reg src0);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 226968b20948ace8cf31f59dd8afd7f123d83228..d1aeeadd102fd1515d4926ebd07d52655b8d984e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -732,6 +732,27 @@ vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
    brw_pop_insn_state(p);
 }
 
+void
+vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst,
+                                                   struct brw_reg src0,
+                                                   struct brw_reg src1,
+                                                   struct brw_reg src2)
+{
+   brw_push_insn_state(p);
+   brw_set_default_access_mode(p, BRW_ALIGN_1);
+   /* Save src0 data in 16:31 bits of dst.0 */
+   brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
+           brw_imm_ud(0xffffu));
+   brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
+   /* Save src1 data in 0:15 bits of dst.0 */
+   brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
+           brw_imm_ud(0xffffu));
+   brw_OR(p, suboffset(vec1(dst), 0),
+          suboffset(vec1(dst), 0),
+          suboffset(vec1(src2), 0));
+   brw_pop_insn_state(p);
+}
+
 void
 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
                                     struct brw_reg dst,
@@ -1423,6 +1444,10 @@ vec4_generator::generate_code(const cfg_t *cfg)
          generate_gs_ff_sync(inst, dst, src[0]);
          break;
 
+      case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
+         generate_gs_ff_sync_set_primitives(dst, src[0], src[1], src[2]);
+         break;
+
       case GS_OPCODE_SET_PRIMITIVE_ID:
          generate_gs_set_primitive_id(dst);
          break;