S/390: Use load-on-condition in cstorecc4

gcc/ChangeLog:

2017-04-25  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* config/s390/s390.md ("cstorecc4"): Use load-on-condition and deal
	with CCZmode for TARGET_Z196.

From-SVN: r247130

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 91e67b78d801ce5eac2d3330c58f94039c305fb6..2f2365b0b18825b93d38bcffe3d9528bc789a55d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-04-25  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+       * config/s390/s390.md ("cstorecc4"): Use load-on-condition and deal
+       with CCZmode for TARGET_Z196.
+
 2017-04-25  Jakub Jelinek  <jakub@redhat.com>
 
        PR rtl-optimization/80501

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 59f189c5e974c2d36a47de67c18f5dc41db885ba..6a1cab6947aee2fe5e65f9e3be3766d5a6a84947 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -6518,13 +6518,30 @@
   [(parallel
     [(set (match_operand:SI 0 "register_operand" "")
          (match_operator:SI 1 "s390_eqne_operator"
-           [(match_operand:CCZ1 2 "register_operand")
+           [(match_operand 2 "cc_reg_operand")
            (match_operand 3 "const0_operand")]))
      (clobber (reg:CC CC_REGNUM))])]
   ""
-  "emit_insn (gen_sne (operands[0], operands[2]));
-   if (GET_CODE (operands[1]) == EQ)
-     emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
+  "machine_mode mode = GET_MODE (operands[2]);
+   if (TARGET_Z196)
+     {
+       rtx cond, ite;
+
+       if (GET_CODE (operands[1]) == NE)
+        cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx);
+       else
+        cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx);
+       ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx);
+       emit_insn (gen_rtx_SET (operands[0], ite));
+     }
+   else
+     {
+       if (mode != CCZ1mode)
+        FAIL;
+       emit_insn (gen_sne (operands[0], operands[2]));
+       if (GET_CODE (operands[1]) == EQ)
+        emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
+     }
    DONE;")
 
 (define_insn_and_split "sne"