[sim] handle integer division overflow

Behavior is now same as GCC's optimizer.  Previously, we just crashed :)

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 9b752aa48bdcf589ca1ee9df7a1dd66131d2ae33..f6a9b6bbeec6a551b79c103fc5ba24d5e0e50632 100644 (file)
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,5 @@
 require64;
-RD = sreg_t(RS1) / sreg_t(RS2);
+if(RS2 == 0 || sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+  RD = sreg_t(RS1) < 0 ? INT64_MIN : INT64_MAX;
+else
+  RD = sreg_t(RS1) / sreg_t(RS2);

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index f1b65fd9169da15c3a49eeeac3e6f55f20257061..86792a2010c462cf96599712a424a595d63dbc08 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,5 @@
 require64;
-RD = RS1 / RS2;
+if(RS2 == 0)
+  RD = UINT64_MAX;
+else
+  RD = RS1 / RS2;

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 46f78145cbf5a190a7c59164380f58b911725735..296bb9e16f52d11fa5d13a4332792d2724ae851b 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,2 +1,4 @@
-RD = sext32(uint32_t(RS1)/uint32_t(RS2));
-
+if(uint32_t(RS2) == 0)
+  RD = sext32(UINT32_MAX);
+else
+  RD = sext32(uint32_t(RS1)/uint32_t(RS2));

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 0654b490b8c3f3a081feb731a47fd1c91b3c013f..05374695b7c3016c783f836cbe60673bd70d7c89 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,2 +1,4 @@
-RD = sext32(int32_t(RS1)/int32_t(RS2));
-
+if(int32_t(RS2) == 0 || int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
+  RD = sext32(int32_t(RS1) < 0 ? INT32_MIN : INT32_MAX);
+else
+  RD = sext32(int32_t(RS1)/int32_t(RS2));

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 1c82b9589cb066a4410ff7b99bfb1b12f41e10b8..146dbc6a3f85ba170b79c3a285b2f1b416221a58 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,2 +1,5 @@
 require64;
-RD = sreg_t(RS1) % sreg_t(RS2);
+if(RS2 == 0 || sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+  RD = 0;
+else
+  RD = sreg_t(RS1) % sreg_t(RS2);

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index e6af5123ddb376cf0db848d356b876c41c826cae..3b6c44f79aa822b816df1b81b3fee85dc797217e 100644 (file)
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,2 +1,5 @@
 require64;
-RD = RS1 % RS2;
+if(RS2 == 0)
+  RD = 0;
+else
+  RD = RS1 % RS2;

diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 0a7a1ba4f003962b08c59755e315ad423949d72a..820a396e011e016028f6c96525fe413efa2fb84d 100644 (file)
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,2 +1,4 @@
-RD = sext32(uint32_t(RS1) % uint32_t(RS2));
-
+if(uint32_t(RS2) == 0)
+  RD = 0;
+else
+  RD = sext32(uint32_t(RS1) % uint32_t(RS2));

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 0d67c882995d16abb273090353b42275a76b7421..0e68dc6e3b524e1830b4ec800ea8b13505135871 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,2 +1,4 @@
-RD = sext32(int32_t(RS1) % int32_t(RS2));
-
+if(int32_t(RS2) == 0 || int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
+  RD = 0;
+else
+  RD = sext32(int32_t(RS1) % int32_t(RS2));