Explain why we don't use RDPC for sparc PIC register setup.

	* config/sparc/sparc.md (load_pcrel_sym<P:mode>): Explain why we
	don't use the "rd %pc" instruction on v9 for PIC register loads.

From-SVN: r184422

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e12e596ed1db9fb8e465f6bf869ed52463fb5503..df2419a5b45d9b1a92cc6a72829b54e9cb6951ff 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2012-02-20  David S. Miller  <davem@davemloft.net>
+
+       * config/sparc/sparc.md (load_pcrel_sym<P:mode>): Explain why we
+       don't use the "rd %pc" instruction on v9 for PIC register loads.
+
 2012-02-20  Aldy Hernandez  <aldyh@redhat.com>
 
        PR middle-end/52141

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index f70acd373372b8aa74abc705b48cb19010018978..c0c1ef8ac38aecdc34d79264ec879eb207684166 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1352,6 +1352,10 @@
 ;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
 ;; value subject to a PC-relative relocation.  Operand 2 is a helper function
 ;; that adds the PC value at the call point to register #(operand 3).
+;;
+;; Even on V9 we use this call sequence with a stub, instead of "rd %pc, ..."
+;; because the RDPC instruction is extremely expensive and incurs a complete
+;; instruction pipeline flush.
 
 (define_insn "load_pcrel_sym<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")