boards/targets: declare ethmac interrupt with new add_interrupt method

The previous way to define interrupt is still valid, but using add_interrupt
method will ease maintenance

diff --git a/litex/boards/targets/ac701.py b/litex/boards/targets/ac701.py
index 0933866ebed0b70a2fc5cd048f3537257d109ba0..a10885d1b0335696e664eb8d0e4517d2867d1573 100755 (executable)
--- a/litex/boards/targets/ac701.py
+++ b/litex/boards/targets/ac701.py
@@ -76,11 +76,6 @@ class EthernetSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    interrupt_map = {
-        "ethmac": 3,
-    }
-    interrupt_map.update(BaseSoC.interrupt_map)
-
     mem_map = {
         "ethmac": 0x30000000,  # (shadow @0xb0000000)
     }
@@ -133,6 +128,7 @@ class EthernetSoC(BaseSoC):
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_interrupt("ethmac")
 
 # Build --------------------------------------------------------------------------------------------
 def main():

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 98cc0adc6380b80c28813bcdcc727fef64ca34bf..683b3024c6fef05dfb118cc91f0f1ec5fc1c46bf 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -80,11 +80,6 @@ class EthernetSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    interrupt_map = {
-        "ethmac": 3,
-    }
-    interrupt_map.update(BaseSoC.interrupt_map)
-
     mem_map = {
         "ethmac": 0x30000000,  # (shadow @0xb0000000)
     }
@@ -99,6 +94,7 @@ class EthernetSoC(BaseSoC):
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_interrupt("ethmac")
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 1b9e1d6cf42ec20501eeaf8098f1bdf1b874e02f..d529e0e311905ffa1d75f1493a3b391043a0ed21 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -71,11 +71,6 @@ class EthernetSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    interrupt_map = {
-        "ethmac": 3,
-    }
-    interrupt_map.update(BaseSoC.interrupt_map)
-
     mem_map = {
         "ethmac": 0x30000000,  # (shadow @0xb0000000)
     }
@@ -90,6 +85,7 @@ class EthernetSoC(BaseSoC):
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_interrupt("ethmac")
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 954fe954bfba1d5acc2465cd6b8c802de597b3dc..93b435a94c1826e9320842b477ad9a487c8d5c38 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -71,11 +71,6 @@ class EthernetSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    interrupt_map = {
-        "ethmac": 3,
-    }
-    interrupt_map.update(BaseSoC.interrupt_map)
-
     mem_map = {
         "ethmac": 0x30000000,  # (shadow @0xb0000000)
     }
@@ -90,6 +85,7 @@ class EthernetSoC(BaseSoC):
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_interrupt("ethmac")
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 9067ceedf3579cc2bf4561abe7838b91b0e6b0e5..5105a39947e5e96e6ff432c52da36a80e527dbe7 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -109,11 +109,6 @@ class EthernetSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    interrupt_map = {
-        "ethmac": 3,
-    }
-    interrupt_map.update(BaseSoC.interrupt_map)
-
     mem_map = {
         "ethmac": 0x30000000,  # (shadow @0xb0000000)
     }
@@ -129,6 +124,7 @@ class EthernetSoC(BaseSoC):
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_interrupt("ethmac")
 
         self.ethphy.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.cd_eth_tx.clk.attr.add("keep")

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 7125d1a61e25a7f893a58a8e1699023bbfa70b6e..e82f19904a830f1ca87486992a48c0835939a12f 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -75,11 +75,6 @@ class EthernetSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    interrupt_map = {
-        "ethmac": 3,
-    }
-    interrupt_map.update(BaseSoC.interrupt_map)
-
     mem_map = {
         "ethmac": 0x30000000,  # (shadow @0xb0000000)
     }
@@ -94,6 +89,7 @@ class EthernetSoC(BaseSoC):
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_interrupt("ethmac")
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index 3c5f02c9132261c874c5492bea5bb9e608ac321a..f7832973cefae7692198719c66dea52c5ed8f8a2 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -32,11 +32,6 @@ class EthernetSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    interrupt_map = {
-        "ethmac": 3,
-    }
-    interrupt_map.update(BaseSoC.interrupt_map)
-
     mem_map = {
         "ethmac": 0x30000000,  # (shadow @0xb0000000)
     }
@@ -51,6 +46,7 @@ class EthernetSoC(BaseSoC):
             interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_interrupt("ethmac")
 
 # Build --------------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index ec7a572f44f700f35fab8056608a26568ab4c514..757b9e28b21af6f8cb79ee769c296f955bf1f360 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -107,11 +107,6 @@ class EthernetSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    interrupt_map = {
-        "ethmac": 3,
-    }
-    interrupt_map.update(BaseSoC.interrupt_map)
-
     mem_map = {
         "ethmac": 0x30000000,  # (shadow @0xb0000000)
     }
@@ -127,6 +122,7 @@ class EthernetSoC(BaseSoC):
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_interrupt("ethmac")
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")