(no commit message)

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index abba7bf4a9b98c9ec7fd19a394624807c4e2e73b..c9b8206221f7a7741e7d4d09f64485f2fe87d0b2 100644 (file)
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -16,3 +16,11 @@ To achieve full soft-emulated interoperability, all implementations
 **must**, at the bare minimum, raise Illegal Instruction traps for
 all SPRs including all reserved SPRs, all SVP64-related Context
 instructions (REMAP), as well as for the entire SVP64 Prefix space.
+
+Summary of Compliancy Levels, each Level includes all lower levels:
+
+* **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
+  into SVSRR1. Register Files as Standard Power ISA.
+* **Embedded**: `svstep` instruction, all SV Branch instructions,
+  and support for Hardware for-looping
+  in both Horizontal-First and Vertical-First Mode as well as Predication