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diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 06c8f0634d725b740a31dbaa488cd2d92e440ba9..3766c12a8b095316fa363b1472b9e154285c0552 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -23,7 +23,6 @@ from existing SVP64 instructions and have been moved to [[discussion]]
 
 Notes:
 
-* Some of these actually could be added to a scalar ISA as bitmanipulation instructions.  These are separated out into their own section.
 * Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU)
 * Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations.  See [[sv/cr_int_predication]].