revert fhdl/verilog: avoid reg initialization in printheader when reset is not an...

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 4cc657b38da8c1aacc7a6825e3a984cab09b239e..5d5f5896e393e88d311180caea36f91bbb9605db 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -178,11 +178,7 @@ def _printheader(f, ios, name, ns):
         if sig in wires:
             r += "wire " + _printsig(ns, sig) + ";\n"
         else:
-            if isinstance(sig.reset, int):
-                resetexpr = " = " + _printexpr(ns, sig.reset)[0]
-            else:
-                resetexpr = ""
-            r += "reg " + _printsig(ns, sig) + resetexpr + ";\n"
+            r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
     r += "\n"
     return r