add test for yosys's $divfloor and $modfloor cells
authorJacob Lifshay <programmerjake@gmail.com>
Wed, 25 May 2022 00:51:48 +0000 (17:51 -0700)
committerJacob Lifshay <programmerjake@gmail.com>
Wed, 25 May 2022 00:51:48 +0000 (17:51 -0700)
Depends on: https://github.com/YosysHQ/yosys/pull/3335

tests/unsorted/floor_divmod.sby [new file with mode: 0644]

diff --git a/tests/unsorted/floor_divmod.sby b/tests/unsorted/floor_divmod.sby
new file mode 100644 (file)
index 0000000..53218cc
--- /dev/null
@@ -0,0 +1,44 @@
+[options]
+mode bmc
+
+[engines]
+smtbmc
+
+[script]
+read_verilog -icells -formal test.v
+prep -top top
+
+[file test.v]
+module top;
+       wire [7:0] a = $anyconst, b = $anyconst, fdiv, fmod, a2;
+       assign a2 = b * fdiv + fmod;
+
+       \$divfloor #(
+               .A_WIDTH(8),
+               .B_WIDTH(8),
+               .A_SIGNED(1),
+               .B_SIGNED(1),
+               .Y_WIDTH(8),
+       ) fdiv_m (
+               .A(a),
+               .B(b),
+               .Y(fdiv)
+       );
+
+       \$modfloor #(
+               .A_WIDTH(8),
+               .B_WIDTH(8),
+               .A_SIGNED(1),
+               .B_SIGNED(1),
+               .Y_WIDTH(8),
+       ) fmod_m (
+               .A(a),
+               .B(b),
+               .Y(fmod)
+       );
+
+       always @* begin
+               assume(b != 0);
+               assert(a == a2);
+       end
+endmodule