from litex.gen import *
-from litex.soc.interconnect.csr import *
-
-class Identifier(Module, AutoCSR):
- def __init__(self, sysid, frequency, revision=None):
- self._sysid = CSRStatus(16)
- self._frequency = CSRStatus(32)
-
- ###
-
- self.comb += [
- self._sysid.status.eq(sysid),
- self._frequency.status.eq(frequency)
- ]
+class Identifier(Module):
+ def __init__(self, ident):
+ contents = list(ident.encode())
+ l = len(contents)
+ if l > 255:
+ raise ValueError("Identifier string must be 255 characters or less")
+ contents.insert(0, l)
+ self.mem = Memory(8, len(contents), init=contents)
+
+ def get_memories(self):
+ return [(True, self.mem)]
class SoCCore(Module):
csr_map = {
- "crg": 0, # user
- "uart_phy": 1, # provided by default (optional)
- "uart": 2, # provided by default (optional)
- "identifier": 3, # provided by default (optional)
- "timer0": 4, # provided by default (optional)
- "buttons": 5, # user
- "leds": 6, # user
+ "crg": 0, # user
+ "uart_phy": 1, # provided by default (optional)
+ "uart": 2, # provided by default (optional)
+ "identifier_mem": 3, # provided by default (optional)
+ "timer0": 4, # provided by default (optional)
+ "buttons": 5, # user
+ "leds": 6, # user
}
interrupt_map = {
"uart": 0,
shadow_base=0x80000000,
csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200,
- with_identifier=True,
+ ident="",
with_timer=True):
self.platform = platform
self.clk_freq = clk_freq
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
- self.with_identifier = with_identifier
-
self.shadow_base = shadow_base
self.csr_data_width = csr_data_width
self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
- if with_identifier:
- platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
- self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq))
+ if ident:
+ self.submodules.identifier = identifier.Identifier(ident)
+ self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.l2_size = l2_size
-
+
self._sdram_phy = []
self._wb_sdram_ifs = []
self._wb_sdram = wishbone.Interface()
if hasattr(obj, "get_memories"):
memories = obj.get_memories()
for memory in memories:
+ if isinstance(memory, tuple):
+ read_only, memory = memory
+ else:
+ read_only = False
mapaddr = self.address_map(name, memory)
if mapaddr is None:
continue
sram_bus = Interface(*ifargs, **ifkwargs)
- mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
+ mmap = SRAM(memory, mapaddr, read_only=read_only,
+ bus=sram_bus)
self.submodules += mmap
csrs += mmap.get_csrs()
self.srams.append((name, memory, mapaddr, mmap))
read = Signal()
write = Signal()
- counter = Counter(max=ratio)
- self.submodules += counter
+ counter = Signal(max=ratio)
+ counter_reset = Signal()
+ counter_ce = Signal()
+ self.sync += \
+ If(counter_reset,
+ counter.eq(0)
+ ).Elif(counter_ce,
+ counter.eq(counter + 1)
+ )
counter_done = Signal()
- self.comb += counter_done.eq(counter.value == ratio-1)
+ self.comb += counter_done.eq(counter == ratio-1)
# Main FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
- counter.reset.eq(1),
+ counter_reset.eq(1),
If(master.stb & master.cyc,
If(master.we,
NextState("WRITE")
If(master.stb & master.cyc,
slave.stb.eq(1),
If(slave.ack,
- counter.ce.eq(1),
+ counter_ce.eq(1),
If(counter_done,
master.ack.eq(1),
NextState("IDLE")
If(master.stb & master.cyc,
slave.stb.eq(1),
If(slave.ack,
- counter.ce.eq(1),
+ counter_ce.eq(1),
If(counter_done,
master.ack.eq(1),
NextState("IDLE")
).Else(
slave.cti.eq(2)
),
- slave.adr.eq(Cat(counter.value, master.adr))
+ slave.adr.eq(Cat(counter, master.adr))
]
# Datapath
slave.sel.eq(master.sel[i*dw_to//8:(i+1)*dw_to]),
slave.dat_w.eq(master.dat_w[i*dw_to:(i+1)*dw_to])
]
- self.comb += Case(counter.value, cases)
+ self.comb += Case(counter, cases)
cached_data = Signal(dw_from)
self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r))
self.sync += \
- If(read & counter.ce,
+ If(read & counter_ce,
cached_data.eq(master.dat_r)
)
self.submodules += address
self.comb += address.d.eq(master.adr)
- counter = Counter(max=ratio)
- self.submodules += counter
+ counter = Signal(max=ratio)
+ counter_ce = Signal()
+ counter_reset = Signal()
+ self.sync += \
+ If(counter_reset,
+ counter.eq(0)
+ ).Elif(counter_ce,
+ counter.eq(counter + 1)
+ )
counter_offset = Signal(max=ratio)
counter_done = Signal()
self.comb += [
counter_offset.eq(address.q),
- counter_done.eq((counter.value + counter_offset) == ratio-1)
+ counter_done.eq((counter + counter_offset) == ratio-1)
]
cached_data = Signal(dw_to)
# Main FSM
self.submodules.fsm = fsm = FSM()
fsm.act("IDLE",
- counter.reset.eq(1),
+ counter_reset.eq(1),
If(master.stb & master.cyc,
address.ce.eq(1),
If(master.we,
fsm.act("WRITE",
If(master.stb & master.cyc,
write.eq(1),
- counter.ce.eq(1),
+ counter_ce.eq(1),
master.ack.eq(1),
If(counter_done,
NextState("EVICT")
write_sel = Signal()
cases[i] = write_sel.eq(1)
self.comb += [
- cached_sels[i].reset.eq(counter.reset),
+ cached_sels[i].reset.eq(counter_reset),
If(write,
cached_datas[i].d.eq(master.dat_w),
).Else(
cached_sels[i].ce.eq(1)
)
]
- self.comb += Case(counter.value + counter_offset, cases)
+ self.comb += Case(counter + counter_offset, cases)
cases = {}
for i in range(ratio):
timer0_en_write(0);
timer0_reload_write(0);
- timer0_load_write(identifier_frequency_read()/4);
+ timer0_load_write(SYSTEM_CLOCK_FREQUENCY/4);
timer0_en_write(1);
timer0_update_value_write(1);
recognized = 0;
#include <net/microudp.h>
#include "sdram.h"
-#include "dataflow.h"
#include "boot.h"
/* General address space functions */
printf("CRC32: %08x\n", crc32((unsigned char *)addr, length));
}
+static void ident(void)
+{
+ char buffer[IDENT_SIZE];
+
+ get_ident(buffer);
+ printf("Ident: %s\n", buffer);
+}
+
#ifdef __lm32__
enum {
CSR_IE = 1, CSR_IM, CSR_IP, CSR_ICC, CSR_DCC, CSR_CC, CSR_CFG, CSR_EBA,
#endif /* __lm32__ */
-static void dfs(char *baseaddr)
-{
- char *c;
- unsigned int addr;
-
- if(*baseaddr == 0) {
- printf("dfs <address>\n");
- return;
- }
- addr = strtoul(baseaddr, &c, 0);
- if(*c != 0) {
- printf("incorrect address\n");
- return;
- }
- print_isd_info(addr);
-}
-
/* Init + command line */
static void help(void)
else if(strcmp(token, "mw") == 0) mw(get_token(&c), get_token(&c), get_token(&c));
else if(strcmp(token, "mc") == 0) mc(get_token(&c), get_token(&c), get_token(&c));
else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c));
+ else if(strcmp(token, "ident") == 0) ident();
#ifdef L2_SIZE
else if(strcmp(token, "flushl2") == 0) flush_l2_cache();
else if(strcmp(token, "sdrinit") == 0) sdrinit();
#endif
- else if(strcmp(token, "dfs") == 0) dfs(get_token(&c));
-
else if(strcmp(token, "") != 0)
printf("Command not found\n");
}
#endif
timer0_en_write(0);
timer0_reload_write(0);
- timer0_load_write(identifier_frequency_read()*2);
+ timer0_load_write(SYSTEM_CLOCK_FREQUENCY*2);
timer0_en_write(1);
timer0_update_value_write(1);
while(timer0_value_read()) {
"(c) Copyright 2007-2015 M-Labs Limited\n"
"Built "__DATE__" "__TIME__"\n");
crcbios();
- id_print();
#ifdef CSR_ETHMAC_BASE
eth_init();
#endif
extern "C" {
#endif
-void get_sysid_formatted(char *sysid);
-void id_print(void);
+#define IDENT_SIZE 256
+void get_ident(char *ident);
#ifdef __cplusplus
}
#include <string.h>
#include <id.h>
-void get_sysid_formatted(char *sysid)
-{
- sysid[0] = identifier_sysid_read() >> 8;
- sysid[1] = identifier_sysid_read();
- sysid[2] = 0;
-}
-void id_print(void)
+void get_ident(char *ident)
{
- char sysid[3];
-
- get_sysid_formatted(sysid);
- printf("Running on LiteX SoC (sysid:%s) at %dMHz\n", sysid, identifier_frequency_read()/1000000);
+#ifdef CSR_IDENTIFIER_MEM_BASE
+ int len, i;
+
+ len = MMPTR(CSR_IDENTIFIER_MEM_BASE);
+ for(i=0;i<len;i++)
+ ident[i] = MMPTR(CSR_IDENTIFIER_MEM_BASE + 4 + i*4);
+ ident[i] = 0;
+#else
+ ident[0] = 0;
+#endif
}
int t;
timer0_en_write(0);
- t = 2*identifier_frequency_read();
+ t = 2*SYSTEM_CLOCK_FREQUENCY;
timer0_reload_write(t);
timer0_load_write(t);
timer0_en_write(1);
{
timer0_en_write(0);
timer0_reload_write(0);
- timer0_load_write(identifier_frequency_read()/10*ds);
+ timer0_load_write(SYSTEM_CLOCK_FREQUENCY/10*ds);
timer0_en_write(1);
timer0_update_value_write(1);
while(timer0_value_read()) timer0_update_value_write(1);
flterm.join(True)
except KeyboardInterrupt:
pass
- flterm.join()
if __name__ == "__main__":
projects / litex.git / commitdiff