ice40: match memory inference attribute values case insensitive.

LSE/Synplify use case insensitive matching.

diff --git a/techlibs/ice40/brams.txt b/techlibs/ice40/brams.txt
index d51c7119a5d12f9aac878de31b05afd1f005d53e..36dfddab25bbe87f2f4058c6c8c6bb984bebec7e 100644 (file)
--- a/techlibs/ice40/brams.txt
+++ b/techlibs/ice40/brams.txt
@@ -30,6 +30,7 @@ endbram
 
 # The syn_* attributes are described in:
 # https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
+attr_icase 1
 
 match $__ICE40_RAM4K_M0
   # implicitly requested RAM or ROM

diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
index 83386f0ecef4e19d5c750b339b3d9f186695d162..43bcf2452cc1469efc1446240abcce6793eb0028 100644 (file)
--- a/tests/arch/ice40/memories.ys
+++ b/tests/arch/ice40/memories.ys
@@ -34,6 +34,12 @@ setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
+design -reset; read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+setattr -set syn_ramstyle "Block_RAM" m:memory
+synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
+select -assert-count 1 t:SB_RAM40_4K # any case works
+
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 setattr -set ram_block 1 m:memory