Added stubnets example to manual prog chapter

diff --git a/manual/CHAPTER_Prog.tex b/manual/CHAPTER_Prog.tex
index a1ca383d04a4ccabfee6635d52ddead55bd359b2..b6157aa1c9d676e9dccee2518c343e0e4e438e78 100644 (file)
--- a/manual/CHAPTER_Prog.tex
+++ b/manual/CHAPTER_Prog.tex
@@ -11,3 +11,11 @@ with an example module.
 \section{Internal Utility Libraries}
 \section{Loadable Modules}
 
+\section{Example Module}
+
+\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc}
+
+\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile}
+
+\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v}
+

diff --git a/manual/FILES_Prog/Makefile b/manual/FILES_Prog/Makefile
index d73581882b3e1e17ffb6f87f4fb7f6da26b550ac..1afde80fd34f48228b405904ddc83b821c98e789 100644 (file)
--- a/manual/FILES_Prog/Makefile
+++ b/manual/FILES_Prog/Makefile
@@ -1,14 +1,13 @@
-
 test: stubnets.so
-       yosys -q -l test1.log -m ./stubnets.so test.v -p "proc; stubnets"
-       yosys -q -l test2.log -m ./stubnets.so test.v -p "proc; opt; stubnets"
-       yosys -q -l test3.log -m ./stubnets.so test.v -p "proc; techmap; opt; stubnets -report_bits"
+       yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
+       yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
+       yosys -ql test3.log -m ./stubnets.so test.v -p "techmap; opt; stubnets -report_bits"
        tail test1.log test2.log test3.log
 
 stubnets.so: stubnets.cc
-       $(shell yosys-config --cxx --cxxflags --ldflags -o stubnets.so -shared stubnets.cc --ldlibs )
+       $(shell yosys-config --cxx --cxxflags --ldflags -o stubnets.so \
+                                  -shared stubnets.cc --ldlibs )
 
 clean:
        rm -f test1.log test2.log test3.log
        rm -f stubnets.so stubnets.d
-

diff --git a/manual/FILES_Prog/stubnets.cc b/manual/FILES_Prog/stubnets.cc
index 00eab1b1710dcb13449e0beadd28759e7c7dade9..1c71f78b894163ce01af99b828293a71eb206e3a 100644 (file)
--- a/manual/FILES_Prog/stubnets.cc
+++ b/manual/FILES_Prog/stubnets.cc
@@ -67,7 +67,8 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
                // for each bit (unless it is a constant):
                // check if it is used at least two times and add to stub_bits otherwise
                for (size_t i = 0; i < sig.chunks.size(); i++)
-                       if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] + usage_offset) < 2)
+                       if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] +
+                                       usage_offset) < 2)
                                stub_bits.insert(i);
 
                // continue if no stub bits found