Signed extension

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index a09f96a7fb5af1a79259ad442c345aef09f68939..a4602dd63a8d844136c71bb0336d25ab9b5cdafb 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -50,7 +50,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
 
                if (st.ffA) {
                        SigSpec D = st.ffA->getPort("\\D");
-                       cell->setPort("\\A", D.extend_u0(30));
+                       cell->setPort("\\A", D.extend_u0(30, true));
                        cell->setParam("\\AREG", State::S1);
                        if (st.ffA->type == "$dff")
                                cell->setPort("\\CEA2", State::S1);
@@ -60,7 +60,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
                }
                if (st.ffB) {
                        SigSpec D = st.ffB->getPort("\\D");
-                       cell->setPort("\\B", D.extend_u0(18));
+                       cell->setPort("\\B", D.extend_u0(18, true));
                        cell->setParam("\\BREG", State::S1);
                        if (st.ffB->type == "$dff")
                                cell->setPort("\\CEB2", State::S1);

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index ceed64b3079d31947865a591f6e3788036c325e3..4b7bea30862c94f016c04de1632bce436f91e549 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -9,10 +9,10 @@ endmatch
 
 match ffA
        select ffA->type.in($dff, $dffe)
+       select param(ffA, \CLK_POLARITY).as_bool()
        // select nusers(port(ffA, \Q)) == 2
-       index <SigSpec> port(ffA, \Q).extend_u0(30) === port(dsp, \A)
+       index <SigSpec> port(ffA, \Q).extend_u0(25, true) === port(dsp, \A).extract(0, 25)
        // DSP48E1 does not support clock inversion
-       index <Const> param(ffA, \CLK_POLARITY).as_bool() === true
        optional
 endmatch
 
@@ -23,9 +23,9 @@ endcode
 
 match ffB
        select ffB->type.in($dff, $dffe)
+       select param(ffB, \CLK_POLARITY).as_bool()
        // select nusers(port(ffB, \Q)) == 2
-       index <SigSpec> port(ffB, \Q).extend_u0(18) === port(dsp, \B)
-       index <Const> param(ffB, \CLK_POLARITY).as_bool() === true
+       index <SigSpec> port(ffB, \Q).extend_u0(18, true) === port(dsp, \B)
        optional
 endmatch