class AlphaTLB : public SimObject
{
protected:
- typedef TheISA::Addr Addr;
typedef std::multimap<Addr, int> PageTable;
PageTable lookupTable; // Quick lookup into page table
class AlphaITB : public AlphaTLB
{
protected:
- typedef TheISA::Addr Addr;
mutable Stats::Scalar<> hits;
mutable Stats::Scalar<> misses;
mutable Stats::Scalar<> acv;
class AlphaFault : public Fault
{
- protected:
- typedef TheISA::Addr Addr;
public:
AlphaFault(char * newName, int newId, Addr newVect)
: Fault(newName, newId), vect(newVect)
{;}
- TheISA::Addr vect;
+ Addr vect;
};
extern class ResetFaultType : public AlphaFault
*/
class PCDependentDisassembly : public AlphaStaticInst
{
- protected:
- typedef TheISA::Addr Addr;
protected:
/// Cached program counter from last disassembly
mutable Addr cachedPC;
class Branch : public PCDependentDisassembly
{
protected:
- typedef TheISA::Addr Addr;
/// Displacement to target address (signed).
int32_t disp;
class Jump : public PCDependentDisassembly
{
protected:
- typedef TheISA::Addr Addr;
/// Displacement to target address (signed).
int32_t disp;
{
typedef uint32_t MachInst;
- typedef uint64_t Addr;
+// typedef uint64_t Addr;
typedef uint8_t RegIndex;
enum {
class ProcessInfo
{
- protected:
- typedef TheISA::Addr Addr;
private:
ExecContext *xc;
class StackTrace
{
protected:
- typedef TheISA::Addr Addr;
typedef TheISA::MachInst MachInst;
private:
ExecContext *xc;
class PhysicalMemory;
AlphaISA::PageTableEntry
-kernel_pte_lookup(PhysicalMemory *pmem, AlphaISA::Addr ptbr, AlphaISA::VAddr vaddr);
+kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr);
-AlphaISA::Addr vtophys(PhysicalMemory *xc, AlphaISA::Addr vaddr);
-AlphaISA::Addr vtophys(ExecContext *xc, AlphaISA::Addr vaddr);
-uint8_t *vtomem(ExecContext *xc, AlphaISA::Addr vaddr, size_t len);
-uint8_t *ptomem(ExecContext *xc, AlphaISA::Addr paddr, size_t len);
+Addr vtophys(PhysicalMemory *xc, Addr vaddr);
+Addr vtophys(ExecContext *xc, Addr vaddr);
+uint8_t *vtomem(ExecContext *xc, Addr vaddr, size_t len);
+uint8_t *ptomem(ExecContext *xc, Addr paddr, size_t len);
-void CopyOut(ExecContext *xc, void *dst, AlphaISA::Addr src, size_t len);
-void CopyIn(ExecContext *xc, AlphaISA::Addr dst, void *src, size_t len);
-void CopyString(ExecContext *xc, char *dst, AlphaISA::Addr vaddr, size_t maxlen);
+void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
+void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
+void CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
#endif // __ARCH_ALPHA_VTOPHYS_H__
class ObjectFile
{
public:
- typedef TheISA::Addr Addr;
enum Arch {
UnknownArch,
class Checkpoint;
class SymbolTable
{
- typedef TheISA::Addr Addr;
public:
- typedef std::map<TheISA::Addr, std::string> ATable;
+ typedef std::map<Addr, std::string> ATable;
typedef std::map<std::string, Addr> STable;
private:
class RemoteGDB
{
protected:
- typedef TheISA::Addr Addr;
typedef TheISA::MachInst MachInst;
private:
friend void debugger();
class BaseCPU : public SimObject
{
protected:
- typedef TheISA::Addr Addr;
// CPU's clock period in terms of the number of ticks of curTime.
Tick clock;
/// Binary machine instruction type.
typedef TheISA::MachInst MachInst;
- /// Memory address type.
- typedef TheISA::Addr Addr;
/// Logical register index type.
typedef TheISA::RegIndex RegIndex;
/// Integer register index type.
{
protected:
typedef TheISA::RegFile RegFile;
- typedef TheISA::Addr Addr;
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscRegFile MiscRegFile;
public:
class InstRecord : public Record
{
protected:
- typedef TheISA::Addr Addr;
typedef TheISA::IntRegFile IntRegFile;
// The following fields are initialized by the constructor and
InstRecord *
getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
const StaticInstPtr staticInst,
- TheISA::Addr pc, int thread = 0)
+ Addr pc, int thread = 0)
{
if (DTRACE(InstExec) &&
(InstRecord::traceMisspec() || !xc->misspeculating())) {
class ExecContext;
class MemTest : public SimObject
{
- protected:
- typedef TheISA::Addr Addr;
public:
MemTest(const std::string &name,
class DefaultBP
{
- protected:
- typedef TheISA::Addr Addr;
public:
/**
* Default branch predictor constructor.
class AlphaFullCPU : public FullO3CPU<Impl>
{
protected:
- typedef AlphaISA::Addr Addr;
typedef TheISA::IntReg IntReg;
public:
typedef typename Impl::Params Params;
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
- /** Memory address type. */
- typedef TheISA::Addr Addr;
/** Logical register index type. */
typedef TheISA::RegIndex RegIndex;
/** Integer register index type. */
template<class Impl>
class TwobitBPredUnit
{
- protected:
- typedef TheISA::Addr Addr;
public:
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
class DefaultBTB
{
- protected:
- typedef TheISA::Addr Addr;
private:
struct BTBEntry
{
typedef typename CPUPol::DecodeStruct DecodeStruct;
typedef typename CPUPol::TimeStruct TimeStruct;
- // Typedefs from the ISA.
- typedef TheISA::Addr Addr;
-
public:
// The only time decode will become blocked is if dispatch becomes
// blocked, which means IQ or ROB is probably full.
/** Typedefs from ISA. */
typedef TheISA::MachInst MachInst;
- typedef TheISA::Addr Addr;
public:
enum Status {
class ReturnAddrStack
{
- protected:
- typedef TheISA::Addr Addr;
public:
ReturnAddrStack(unsigned numEntries);
class PhysRegFile
{
protected:
- typedef TheISA::Addr Addr;
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::MiscRegFile MiscRegFile;
typedef typename CPUPol::RenameMap RenameMap;
// Typedefs from the ISA.
- typedef TheISA::Addr Addr;
typedef TheISA::RegIndex RegIndex;
public:
class StoreSet
{
- protected:
- typedef TheISA::Addr Addr;
public:
typedef unsigned SSID;
class TournamentBP
{
- protected:
- typedef TheISA::Addr Addr;
public:
/**
* Default branch predictor constructor.
#if FULL_SYSTEM
extern "C"
void
-sched_break_pc_sys(System *sys, TheISA::Addr addr)
+sched_break_pc_sys(System *sys, Addr addr)
{
new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
}
extern "C"
void
-sched_break_pc(TheISA::Addr addr)
+sched_break_pc(Addr addr)
{
for (vector<System *>::iterator sysi = System::systemList.begin();
sysi != System::systemList.end(); ++sysi) {
class PCEvent
{
protected:
- typedef TheISA::Addr Addr;
static const Addr badpc = MemReq::inval_addr;
protected:
class PCEventQueue
{
protected:
- typedef TheISA::Addr Addr;
typedef PCEvent * record_t;
class MapCompare {
public:
class BreakPCEvent : public PCEvent
{
protected:
- typedef TheISA::Addr Addr;
bool remove;
public:
class ProfileNode
{
- protected:
- typedef TheISA::Addr Addr;
private:
friend class FunctionProfile;
class Callback;
class FunctionProfile
{
- public:
- typedef TheISA::Addr Addr;
private:
Callback *reset;
const SymbolTable *symtab;
/// Binary machine instruction type.
typedef TheISA::MachInst MachInst;
- /// Memory address type.
- typedef TheISA::Addr Addr;
/// Logical register index type.
typedef TheISA::RegIndex RegIndex;
*/
class OptCPU : public SimObject
{
- protected:
- typedef TheISA::Addr Addr;
private:
typedef int RefIndex;
*/
class ITXReader : public MemTraceReader
{
- protected:
- typedef TheISA::Addr Addr;
private:
/** Trace file. */
FILE *trace;
*/
class IdeDisk : public SimObject
{
- protected:
- typedef TheISA::Addr Addr;
protected:
/** The IDE controller for this disk. */
IdeController *ctrl;
*/
class PciConfigData : public SimObject
{
- protected:
- typedef TheISA::Addr Addr;
public:
/**
* Constructor to initialize the devices config space to 0.
class Platform : public SimObject
{
- protected:
- typedef TheISA::Addr Addr;
public:
/** Pointer to the interrupt controller */
IntrControl *intrctrl;
*/
class SimpleDisk : public SimObject
{
- protected:
- typedef TheISA::Addr Addr;
public:
typedef uint64_t baddr_t;
/* namespace Regs */ }
inline const Regs::Info&
-regInfo(TheISA::Addr daddr)
+regInfo(Addr daddr)
{
static Regs::Info invalid = { 0, false, false, "invalid" };
static Regs::Info info [] = {
}
inline bool
-regValid(TheISA::Addr daddr)
+regValid(Addr daddr)
{
if (daddr > Regs::Size)
return false;
class Tsunami : public Platform
{
- protected:
- typedef TheISA::Addr Addr;
public:
/** Max number of CPUs in a Tsunami */
static const int Max_CPUs = 64;
class Binning
{
- protected:
- typedef TheISA::Addr Addr;
private:
std::string myname;
System *system;
class Statistics : public Serializable
{
- protected:
- typedef TheISA::Addr Addr;
private:
friend class Binning;
#if __GNUC__ == 3 && __GNUC_MINOR__ != 3
typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ;
typedef int64_t int64_ta __attribute__ ((aligned (8))) ;
-typedef TheISA::Addr Addr_a __attribute__ ((aligned (8))) ;
+typedef Addr Addr_a __attribute__ ((aligned (8))) ;
#else
#define uint64_ta uint64_t __attribute__ ((aligned (8)))
#define int64_ta int64_t __attribute__ ((aligned (8)))
///
class Linux {
- protected:
- typedef TheISA::Addr Addr;
-
public:
//@{
class ThreadInfo
{
- protected:
- typedef TheISA::Addr Addr;
private:
ExecContext *xc;
namespace tru64 {
struct m_hdr {
- TheISA::Addr mh_next; // 0x00
- TheISA::Addr mh_nextpkt; // 0x08
- TheISA::Addr mh_data; // 0x10
+ Addr mh_next; // 0x00
+ Addr mh_nextpkt; // 0x08
+ Addr mh_data; // 0x10
int32_t mh_len; // 0x18
int32_t mh_type; // 0x1C
int32_t mh_flags; // 0x20
int32_t mh_pad0; // 0x24
- TheISA::Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
+ Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
};
struct pkthdr {
int32_t len;
int32_t protocolSum;
- TheISA::Addr rcvif;
+ Addr rcvif;
};
struct m_ext {
- TheISA::Addr ext_buf; // 0x00
- TheISA::Addr ext_free; // 0x08
+ Addr ext_buf; // 0x00
+ Addr ext_free; // 0x08
uint32_t ext_size; // 0x10
uint32_t ext_pad0; // 0x14
- TheISA::Addr ext_arg; // 0x18
+ Addr ext_arg; // 0x18
struct ext_refq {
- TheISA::Addr forw, back; // 0x20, 0x28
+ Addr forw, back; // 0x20, 0x28
} ext_ref;
- TheISA::Addr uiomove_f; // 0x30
+ Addr uiomove_f; // 0x30
int32_t protocolSum; // 0x38
int32_t bytesSummed; // 0x3C
- TheISA::Addr checksum; // 0x40
+ Addr checksum; // 0x40
};
struct mbuf {
/// For stack_create.
struct vm_stack {
// was void *
- TheISA::Addr address; //!< address hint
+ Addr address; //!< address hint
size_t rsize; //!< red zone size
size_t ysize; //!< yellow zone size
size_t gsize; //!< green zone size
uint64_t align; //!< address alignment
uint64_t flags; //!< MAP_FIXED etc.
// was struct memalloc_attr *
- TheISA::Addr attr; //!< allocation policy
+ Addr attr; //!< allocation policy
uint64_t reserved; //!< reserved
};
sigset_t sigmask; //!< thread signal mask
sigset_t sig; //!< thread pending mask
// struct nxm_pth_state *
- TheISA::Addr pth_id; //!< out-of-line state
+ Addr pth_id; //!< out-of-line state
int flags; //!< shared flags
#define US_SIGSTACK 0x1 // thread called sigaltstack
#define US_ONSTACK 0x2 // thread is running on altstack
int nxm_set_quantum; //!< quantum reset value
int nxm_sysevent; //!< syscall state
// struct nxm_upcall *
- TheISA::Addr nxm_uc_ret; //!< stack ptr of null thread
+ Addr nxm_uc_ret; //!< stack ptr of null thread
// void *
- TheISA::Addr nxm_tid; //!< scheduler's thread id
+ Addr nxm_tid; //!< scheduler's thread id
int64_t nxm_va; //!< page fault address
// struct nxm_pth_state *
- TheISA::Addr nxm_pthid; //!< id of null thread
+ Addr nxm_pthid; //!< id of null thread
uint64_t nxm_bound_pcs_count; //!< bound PCS thread count
int64_t pad[2]; //!< pad
};
int nxm_nslots_per_rad; //!< max number of VP slots per RAD
int nxm_nrads; //!< max number of RADs
// nxm_slot_state_t *
- TheISA::Addr nxm_slot_state; //!< per-VP slot state
+ Addr nxm_slot_state; //!< per-VP slot state
// struct nxm_shared *
- TheISA::Addr nxm_rad[1]; //!< per-RAD shared areas
+ Addr nxm_rad[1]; //!< per-RAD shared areas
};
/// For nxm_thread_create.
int policy; //!< policy
int signal_type; //!< signal_type
// void *
- TheISA::Addr pthid; //!< pthid
+ Addr pthid; //!< pthid
sigset_t sigmask; //!< sigmask
/// Initial register values.
struct {
/// memory space. Used by stat(), fstat(), and lstat().
template <class T>
static void
- copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr, global_stat *host)
+ copyOutStatBuf(FunctionalMemory *mem, Addr addr, global_stat *host)
{
TypedBufferArg<T> tgt(addr);
/// memory space. Used by statfs() and fstatfs().
template <class T>
static void
- copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr, global_statfs *host)
+ copyOutStatfsBuf(FunctionalMemory *mem, Addr addr, global_statfs *host)
{
TypedBufferArg<T> tgt(addr);
class F64 {
public:
- static void copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr,
+ static void copyOutStatBuf(FunctionalMemory *mem, Addr addr,
global_stat *host)
{
Tru64::copyOutStatBuf<Tru64::F64_stat>(mem, addr, host);
}
- static void copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr,
+ static void copyOutStatfsBuf(FunctionalMemory *mem, Addr addr,
global_statfs *host)
{
Tru64::copyOutStatfsBuf<Tru64::F64_statfs>(mem, addr, host);
class PreF64 {
public:
- static void copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr,
+ static void copyOutStatBuf(FunctionalMemory *mem, Addr addr,
global_stat *host)
{
Tru64::copyOutStatBuf<Tru64::pre_F64_stat>(mem, addr, host);
}
- static void copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr,
+ static void copyOutStatfsBuf(FunctionalMemory *mem, Addr addr,
global_statfs *host)
{
Tru64::copyOutStatfsBuf<Tru64::pre_F64_statfs>(mem, addr, host);
/// the simulated memory space. Used by pre_F64_stat(),
/// pre_F64_fstat(), and pre_F64_lstat().
static void
- copyOutPreF64StatBuf(FunctionalMemory *mem, TheISA::Addr addr, struct stat *host)
+ copyOutPreF64StatBuf(FunctionalMemory *mem, Addr addr, struct stat *host)
{
TypedBufferArg<Tru64::pre_F64_stat> tgt(addr);
getdirentriesFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
#ifdef __CYGWIN__
panic("getdirent not implemented on cygwin!");
#else
nxm_task_initFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
TypedBufferArg<Tru64::nxm_task_attr> attrp(xc->getSyscallArg(0));
TypedBufferArg<Addr> configptr_ptr(xc->getSyscallArg(1));
nxm_thread_createFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
TypedBufferArg<Tru64::nxm_thread_attr> attrp(xc->getSyscallArg(0));
TypedBufferArg<uint64_t> kidp(xc->getSyscallArg(1));
int thread_index = xc->getSyscallArg(2);
nxm_blockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
uint64_t val = xc->getSyscallArg(1);
uint64_t secs = xc->getSyscallArg(2);
nxm_unblockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
cout << xc->cpu->name() << ": nxm_unblock "
/// Activate exec context waiting on a channel. Just activate one
/// by default.
static int
- activate_waiting_context(TheISA::Addr uaddr, Process *process,
+ activate_waiting_context(Addr uaddr, Process *process,
bool activate_all = false)
{
int num_activated = 0;
/// M5 hacked-up lock acquire.
static void
- m5_lock_mutex(TheISA::Addr uaddr, Process *process, ExecContext *xc)
+ m5_lock_mutex(Addr uaddr, Process *process, ExecContext *xc)
{
TypedBufferArg<uint64_t> lockp(uaddr);
/// M5 unlock call.
static void
- m5_unlock_mutex(TheISA::Addr uaddr, Process *process, ExecContext *xc)
+ m5_unlock_mutex(Addr uaddr, Process *process, ExecContext *xc)
{
TypedBufferArg<uint64_t> lockp(uaddr);
m5_mutex_lockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
m5_lock_mutex(uaddr, process, xc);
m5_mutex_trylockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
TypedBufferArg<uint64_t> lockp(uaddr);
m5_mutex_unlockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
m5_unlock_mutex(uaddr, process, xc);
m5_cond_signalFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
Addr cond_addr = xc->getSyscallArg(0);
// Wake up one process waiting on the condition variable.
m5_cond_broadcastFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
Addr cond_addr = xc->getSyscallArg(0);
activate_waiting_context(cond_addr, process, true);
m5_cond_waitFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- using TheISA::Addr;
Addr cond_addr = xc->getSyscallArg(0);
Addr lock_addr = xc->getSyscallArg(1);
TypedBufferArg<uint64_t> condp(cond_addr);
*/
typedef int64_t Tick;
+/**
+ * Address type
+ * This will probably be moved somewhere else in the near future.
+ * This should be at least as big as the biggest address width in use
+ * in the system, which will probably be 64 bits.
+ */
+typedef uint64_t Addr;
+
#endif // __HOST_H__
class Process : public SimObject
{
protected:
- typedef TheISA::Addr Addr;
typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
public:
void dumpstats(ExecContext *xc, Tick delay, Tick period);
void dumpresetstats(ExecContext *xc, Tick delay, Tick period);
void m5checkpoint(ExecContext *xc, Tick delay, Tick period);
- uint64_t readfile(ExecContext *xc, TheISA::Addr vaddr, uint64_t len, uint64_t offset);
+ uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset);
void debugbreak(ExecContext *xc);
void switchcpu(ExecContext *xc);
- void addsymbol(ExecContext *xc, TheISA::Addr addr, TheISA::Addr symbolAddr);
+ void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr);
}
class BaseBufferArg {
- protected:
- typedef TheISA::Addr Addr;
-
public:
BaseBufferArg(Addr _addr, int _size) : addr(_addr), size(_size)
SyscallReturn
mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
- TheISA::Addr start = xc->getSyscallArg(0);
+ Addr start = xc->getSyscallArg(0);
uint64_t length = xc->getSyscallArg(1);
// int prot = xc->getSyscallArg(2);
int flags = xc->getSyscallArg(3);
class System : public SimObject
{
- protected:
- typedef TheISA::Addr Addr;
public:
MemoryController *memctrl;
PhysicalMemory *physmem;
template <class T>
class VPtr
{
- protected:
- typedef TheISA::Addr Addr;
public:
typedef T Type;
projects / gem5.git / commitdiff