arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU

The PMU model currently doesn't calculate the PMU event counter index
correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this
obvious mistake.

Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3121
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 39530702c4e00d27bb800974cf9318e3663f93f8..ac2f4759fa496e4f0ef56f0d7367766e6571b3e9 100644 (file)
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -163,7 +163,7 @@ PMU::setMiscReg(int misc_reg, MiscReg val)
         return;
 
       case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
-        setCounterTypeRegister(misc_reg - MISCREG_PMEVCNTR0_EL0, val);
+        setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0, val);
         return;
 
       case MISCREG_PMCCFILTR: