cpu: Use new InstRecord faulting flag in cpu models

This patch sets the faulting flag in atomic, timing, minor and o3 CPU
models.

It also fixes the minor/timing CPU models which were not respecting the
ExecFaulting flag. This is now checked before calling dump() on the
tracing object, to bring it in line with the other CPU models.

Change-Id: I9c7b64cc5605596eb7fcf25fdecaeac5c4b5e3d7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30135
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index d311d145730debd59a7bf075d9057eb7e78a8a9c..3c94531ecc6da202eddf41db00e021d4e78d2035 100644 (file)
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014,2018-2019 ARM Limited
+ * Copyright (c) 2013-2014,2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -48,6 +48,7 @@
 #include "debug/Activity.hh"
 #include "debug/Branch.hh"
 #include "debug/Drain.hh"
+#include "debug/ExecFaulting.hh"
 #include "debug/MinorExecute.hh"
 #include "debug/MinorInterrupt.hh"
 #include "debug/MinorMem.hh"
@@ -978,6 +979,15 @@ Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue,
         committed = true;
 
         if (fault != NoFault) {
+            if (inst->traceData) {
+                if (DTRACE(ExecFaulting)) {
+                    inst->traceData->setFaulting(true);
+                } else {
+                    delete inst->traceData;
+                    inst->traceData = NULL;
+                }
+            }
+
             DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n",
                 *inst, fault->name());
             fault->invoke(thread, inst->staticInst);

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 667f42b2eedbc02e0c8ea4ed74ba69b2b7a7b1aa..4f467e96a6bd3069f8f2090b997711d236c0f814 100644 (file)
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2014, 2017 ARM Limited
+ * Copyright (c) 2010-2014, 2017, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1260,6 +1260,7 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
             tid, head_inst->seqNum);
         if (head_inst->traceData) {
             if (DTRACE(ExecFaulting)) {
+                head_inst->traceData->setFaulting(true);
                 head_inst->traceData->setFetchSeq(head_inst->seqNum);
                 head_inst->traceData->setCPSeq(thread[tid]->numOp);
                 head_inst->traceData->dump();

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4671402c91a9a6bd8e6e0090ba779f5046e0848a..c57fe14d22e71dd3eb1fd8fa9fd59687fc250b17 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2012-2013,2015,2017-2019 ARM Limited
+ * Copyright (c) 2012-2013,2015,2017-2020 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -713,10 +713,8 @@ AtomicSimpleCPU::tick()
                 if (fault == NoFault) {
                     countInst();
                     ppCommit->notify(std::make_pair(thread, curStaticInst));
-                }
-                else if (traceData && !DTRACE(ExecFaulting)) {
-                    delete traceData;
-                    traceData = NULL;
+                } else if (traceData) {
+                    traceFault();
                 }
 
                 if (fault != NoFault &&

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index c6d57616bb32a9ffe6f28a01d7c82f14fab0072c..1dac921f60277d35cff7cc4c6a4e2a618b7a3997 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2015, 2017, 2018 ARM Limited
+ * Copyright (c) 2010-2012, 2015, 2017, 2018, 2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -64,6 +64,7 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Decode.hh"
+#include "debug/ExecFaulting.hh"
 #include "debug/Fetch.hh"
 #include "debug/Quiesce.hh"
 #include "mem/packet.hh"
@@ -432,6 +433,17 @@ BaseSimpleCPU::wakeup(ThreadID tid)
     }
 }
 
+void
+BaseSimpleCPU::traceFault()
+{
+    if (DTRACE(ExecFaulting)) {
+        traceData->setFaulting(true);
+    } else {
+        delete traceData;
+        traceData = NULL;
+    }
+}
+
 void
 BaseSimpleCPU::checkForInterrupts()
 {

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 323850ac51cebe61783970ecd42de96bbcd9ddee..9f5bf662b28d05c3a6e3bb10bccd4f071df7fd05 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012,2015,2018 ARM Limited
+ * Copyright (c) 2011-2012,2015,2018,2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -120,6 +120,14 @@ class BaseSimpleCPU : public BaseCPU
 
     Status _status;
 
+    /**
+     * Handler used when encountering a fault; its purpose is to
+     * tear down the InstRecord. If a fault is meant to be traced,
+     * the handler won't delete the record and it will annotate
+     * the record as coming from a faulting instruction.
+     */
+    void traceFault();
+
   public:
     void checkForInterrupts();
     void setupFetchRequest(const RequestPtr &req);

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c1c70cb3819284687518a1487717ecc6e7cb9f75..84d7d0eb75f7eeb9d45441165f5ff64f5749aa39 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited
+ * Copyright (c) 2010-2013,2015,2017-2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -363,10 +363,8 @@ TimingSimpleCPU::translationFault(const Fault &fault)
     updateCycleCounts();
     updateCycleCounters(BaseCPU::CPU_STATE_ON);
 
-    if (traceData) {
-        // Since there was a fault, we shouldn't trace this instruction.
-        delete traceData;
-        traceData = NULL;
+    if ((fault != NoFault) && traceData) {
+        traceFault();
     }
 
     postExecute();
@@ -794,9 +792,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
         // ifetch
         if (_status == BaseSimpleCPU::Running) {
             if (fault != NoFault && traceData) {
-                // If there was a fault, we shouldn't trace this instruction.
-                delete traceData;
-                traceData = NULL;
+                traceFault();
             }
 
             postExecute();
@@ -813,9 +809,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
         // keep an instruction count
         if (fault == NoFault)
             countInst();
-        else if (traceData && !DTRACE(ExecFaulting)) {
-            delete traceData;
-            traceData = NULL;
+        else if (traceData) {
+            traceFault();
         }
 
         postExecute();
@@ -913,9 +908,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     if (fault == NoFault)
         countInst();
     else if (traceData) {
-        // If there was a fault, we shouldn't trace this instruction.
-        delete traceData;
-        traceData = NULL;
+        traceFault();
     }
 
     delete pkt;