Signed-off-by: Rob Clark <robclark@freedesktop.org>
val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}
+ if (fp->has_kill) {
+ val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
+ }
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, val);
}
ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = cond;
ctx->kill[ctx->kill_count++] = instr;
+
+ ctx->so->has_kill = true;
}
/*
ctx->kill[ctx->kill_count++] = instr;
+ ctx->so->has_kill = true;
+
}
/*
* I2F / U2F / F2I / F2U
/* do we have one or more texture sample instructions: */
bool has_samp;
+ /* do we have kill instructions: */
+ bool has_kill;
+
/* const reg # of first immediate, ie. 1 == c1
* (not regid, because TGSI thinks in terms of vec4 registers,
* not scalar registers)