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authorlkcl <lkcl@web>
Tue, 14 Jul 2020 19:36:05 +0000 (20:36 +0100)
committerIkiWiki <ikiwiki.info>
Tue, 14 Jul 2020 19:36:05 +0000 (20:36 +0100)
3d_gpu/architecture/regfile.mdwn patch | blob | history

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 4ea2234d99178e93c3b9857352a76fe1dc5e20c1..0988b42e2f750bf8eda4ae62843daf2f4f78d075 100644 (file)
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -8,8 +8,9 @@ A minimum of 4 register files are required for POWER:
 
 * Floating-point
 * Integer
-* Control and Condition Code Registers (CR0-7, CTR, LR)
+* Control and Condition Code Registers (CR0-7)
 * SPRs (Special Purpose Registers)
+* Fast Registers (PC, MSR, CTR, LR, SRR0, SRR1 etc.)
 
 Source code:
 
http://libre-riscv.org ikiwiki