split out instructions from openpower/isa/fixedshift.mdwn

diff --git a/openpower/isa/fixedshift.mdwn b/openpower/isa/fixedshift.mdwn
index db59a6fa85bb2fea7f1892ab5af44678db6ca031..bd0911f613e826e8b041c25a16373f97449b93e5 100644 (file)
--- a/openpower/isa/fixedshift.mdwn
+++ b/openpower/isa/fixedshift.mdwn
@@ -10,369 +10,38 @@
 
 <!-- Section 3.3.14.1 Fixed-Point Rotate Instructions pages 101 - 106 -->
 
-# Rotate Left Word Immediate then AND with Mask
+[[!inline pagenames="openpower/isa/fixedshift/rlwinm" raw="yes"]]
 
-M-Form
+[[!inline pagenames="openpower/isa/fixedshift/rlwnm" raw="yes"]]
 
-* rlwinm RA,RS,SH,MB,ME (Rc=0)
-* rlwinm.  RA,RS,SH,MB,ME (Rc=1)
+[[!inline pagenames="openpower/isa/fixedshift/rlwimi" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedshift/rldicl" raw="yes"]]
 
-    n <- SH
-    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
-    m <- MASK32(MB, ME)
-    RA <- r & m
+[[!inline pagenames="openpower/isa/fixedshift/rldicr" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedshift/rldic" raw="yes"]]
 
-    CR0                    (if Rc=1)
+[[!inline pagenames="openpower/isa/fixedshift/rldcl" raw="yes"]]
 
-# Rotate Left Word then AND with Mask
+[[!inline pagenames="openpower/isa/fixedshift/rldcr" raw="yes"]]
 
-M-Form
+[[!inline pagenames="openpower/isa/fixedshift/rldimi" raw="yes"]]
 
-* rlwnm RA,RS,RB,MB,ME (Rc=0)
-* rlwnm.  RA,RS,RB,MB,ME (Rc=1)
+[[!inline pagenames="openpower/isa/fixedshift/slw" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedshift/srw" raw="yes"]]
 
-    n <- (RB)[XLEN-5:XLEN-1]
-    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
-    m <- MASK32(MB, ME)
-    RA <- r & m
+[[!inline pagenames="openpower/isa/fixedshift/srawi" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedshift/sraw" raw="yes"]]
 
-    CR0                    (if Rc=1)
+[[!inline pagenames="openpower/isa/fixedshift/sld" raw="yes"]]
 
-# Rotate Left Word Immediate then Mask Insert
+[[!inline pagenames="openpower/isa/fixedshift/srd" raw="yes"]]
 
-M-Form
+[[!inline pagenames="openpower/isa/fixedshift/sradi" raw="yes"]]
 
-* rlwimi RA,RS,SH,MB,ME (Rc=0)
-* rlwimi.  RA,RS,SH,MB,ME (Rc=1)
+[[!inline pagenames="openpower/isa/fixedshift/srad" raw="yes"]]
 
-Pseudo-code:
-
-    n <- SH
-    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
-    m <- MASK32(MB, ME)
-    RA <- r&m | (RA) & ¬m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Rotate Left Doubleword Immediate then Clear Left
-
-MD-Form
-
-* rldicl RA,RS,sh,mb (Rc=0)
-* rldicl.  RA,RS,sh,mb (Rc=1)
-
-Pseudo-code:
-
-    n <- sh
-    r <- ROTL64((RS), n)
-    b <- mb[5] || mb[0:4]
-    m <- MASK(b, (XLEN-1))
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Rotate Left Doubleword Immediate then Clear Right
-
-MD-Form
-
-* rldicr RA,RS,sh,me (Rc=0)
-* rldicr.  RA,RS,sh,me (Rc=1)
-
-Pseudo-code:
-
-    n <- sh
-    r <- ROTL64((RS), n)
-    e <- me[5] || me[0:4]
-    m <- MASK(0, e)
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Rotate Left Doubleword Immediate then Clear
-
-MD-Form
-
-* rldic RA,RS,sh,mb (Rc=0)
-* rldic.  RA,RS,sh,mb (Rc=1)
-
-Pseudo-code:
-
-    n <- sh
-    r <- ROTL64((RS), n)
-    b <- mb[5] || mb[0:4]
-    m <- MASK(b,  ¬n)
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Rotate Left Doubleword then Clear Left
-
-MDS-Form
-
-* rldcl RA,RS,RB,mb (Rc=0)
-* rldcl.  RA,RS,RB,mb (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[XLEN-5:XLEN-1]
-    r <- ROTL64((RS), n)
-    b <- mb[5] || mb[0:4]
-    m <- MASK(b, (XLEN-1))
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Rotate Left Doubleword then Clear Right
-
-MDS-Form
-
-* rldcr RA,RS,RB,me (Rc=0)
-* rldcr.  RA,RS,RB,me (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[XLEN-5:XLEN-1]
-    r <- ROTL64((RS), n)
-    e <- me[5] || me[0:4]
-    m <- MASK(0, e)
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Rotate Left Doubleword Immediate then Mask Insert
-
-MD-Form
-
-* rldimi RA,RS,sh,mb (Rc=0)
-* rldimi.  RA,RS,sh,mb (Rc=1)
-
-Pseudo-code:
-
-    n <- sh
-    r <- ROTL64((RS), n)
-    b <- mb[5] || mb[0:4]
-    m <- MASK(b,  ¬n)
-    RA <- r&m | (RA)& ¬m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-
-<!-- Section 3.3.14.2 Fixed-Point Shift Instructions pages 107 - 110 -->
-
-# Shift Left Word
-
-X-Form
-
-* slw RA,RS,RB (Rc=0)
-* slw.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[XLEN-5:XLEN-1]
-    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
-    if (RB)[XLEN-6] = 0 then
-         m <- MASK32(0, ((XLEN/2)-1-n))
-    else m <- [0]*XLEN
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Shift Right Word
-
-X-Form
-
-* srw RA,RS,RB (Rc=0)
-* srw.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[XLEN-5:XLEN-1]
-    r <- ROTL32((RS)[XLEN/2:XLEN-1], XLEN-n)
-    if (RB)[XLEN-6] = 0 then
-        m <- MASK32(n, ((XLEN/2)-1))
-    else m <- [0]*XLEN
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Shift Right Algebraic Word Immediate
-
-X-Form
-
-* srawi RA,RS,SH (Rc=0)
-* srawi.  RA,RS,SH (Rc=1)
-
-Pseudo-code:
-
-    n <- SH
-    r <- ROTL32((RS)[XLEN/2:XLEN-1], 64-n)
-    m <- MASK32(n, ((XLEN/2)-1))
-    s <- (RS)[XLEN/2]
-    RA <- r&m | ([s]*XLEN)& ¬m
-    carry <- s & ((r&¬m)[XLEN/2:XLEN-1] != 0)
-    CA    <- carry
-    CA32  <- carry
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                    (if Rc=1)
-
-# Shift Right Algebraic Word
-
-X-Form
-
-* sraw RA,RS,RB (Rc=0)
-* sraw.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[XLEN-5:XLEN-1]
-    r <- ROTL32((RS)[XLEN/2:XLEN-1], XLEN-n)
-    if (RB)[XLEN-6] = 0 then
-        m <- MASK32(n, ((XLEN/2)-1))
-    else m <- [0]*XLEN
-    s <- (RS)[XLEN/2]
-    RA <- r&m | ([s]*XLEN)& ¬m
-    carry <-  s & ((r&¬m)[XLEN/2:XLEN-1] != 0)
-    CA    <-  carry
-    CA32  <-  carry
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                    (if Rc=1)
-
-# Shift Left Doubleword
-
-X-Form
-
-* sld RA,RS,RB (Rc=0)
-* sld.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[XLEN-6:XLEN-1]
-    r <- ROTL64((RS), n)
-    if (RB)[XLEN-7] = 0 then
-         m <- MASK(0, XLEN-1-n)
-    else m <- [0]*XLEN
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Shift Right Doubleword
-
-X-Form
-
-* srd RA,RS,RB (Rc=0)
-* srd.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[XLEN-6:XLEN-1]
-    r <- ROTL64((RS), XLEN-n)
-    if (RB)[XLEN-7] = 0 then
-        m <-  MASK(n, (XLEN-1))
-    else m <- [0]*XLEN
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Shift Right Algebraic Doubleword Immediate
-
-XS-Form
-
-* sradi RA,RS,sh (Rc=0)
-* sradi.  RA,RS,sh (Rc=1)
-
-Pseudo-code:
-
-    n <- sh
-    r <- ROTL64((RS), XLEN-n)
-    m <- MASK(n, (XLEN-1))
-    s <- (RS)[0]
-    RA <- r&m | ([s]*XLEN)& ¬m
-    carry <- s & ((r& ¬m) != 0)
-    CA    <- carry
-    CA32  <- carry
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                    (if Rc=1)
-
-# Shift Right Algebraic Doubleword
-
-X-Form
-
-* srad RA,RS,RB (Rc=0)
-* srad.  RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[XLEN-6:XLEN-1]
-    r <- ROTL64((RS), XLEN-n)
-    if (RB)[XLEN-7] = 0 then
-        m <-  MASK(n, (XLEN-1))
-    else m <- [0]*XLEN
-    s <- (RS)[0]
-    RA <- r&m | ([s]*XLEN)& ¬m
-    carry <-  s & ((r&¬m) != 0)
-    CA    <-  carry
-    CA32  <-  carry
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                    (if Rc=1)
-
-# Extend-Sign Word and Shift Left Immediate
-
-XS-Form
-
-* extswsli RA,RS,sh (Rc=0)
-* extswsli.  RA,RS,sh (Rc=1)
-
-Pseudo-code:
-
-    n  <- sh
-    r  <- ROTL64(EXTS64(RS[XLEN/2:XLEN-1]), n)
-    m  <- MASK(0, XLEN-1-n)
-    RA <- r & m
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-<!-- Checked March 2021 -->
+[[!inline pagenames="openpower/isa/fixedshift/extswsli" raw="yes"]]

diff --git a/openpower/isa/fixedshift/extswsli.mdwn b/openpower/isa/fixedshift/extswsli.mdwn
new file mode 100644 (file)
index 0000000..28a08ed
--- /dev/null
+++ b/openpower/isa/fixedshift/extswsli.mdwn
@@ -0,0 +1,16 @@
+# Extend-Sign Word and Shift Left Immediate
+
+XS-Form
+
+* extswsli RA,RS,sh (Rc=0)
+* extswsli.  RA,RS,sh (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/extswsli_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+
+<!-- Checked March 2021 -->

diff --git a/openpower/isa/fixedshift/extswsli_code.mdwn b/openpower/isa/fixedshift/extswsli_code.mdwn
new file mode 100644 (file)
index 0000000..d859fc0
--- /dev/null
+++ b/openpower/isa/fixedshift/extswsli_code.mdwn
@@ -0,0 +1,4 @@
+    n  <- sh
+    r  <- ROTL64(EXTS64(RS[XLEN/2:XLEN-1]), n)
+    m  <- MASK(0, XLEN-1-n)
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/rldcl.mdwn b/openpower/isa/fixedshift/rldcl.mdwn
new file mode 100644 (file)
index 0000000..c780043
--- /dev/null
+++ b/openpower/isa/fixedshift/rldcl.mdwn
@@ -0,0 +1,14 @@
+# Rotate Left Doubleword then Clear Left
+
+MDS-Form
+
+* rldcl RA,RS,RB,mb (Rc=0)
+* rldcl.  RA,RS,RB,mb (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rldcl_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/rldcl_code.mdwn b/openpower/isa/fixedshift/rldcl_code.mdwn
new file mode 100644 (file)
index 0000000..ec6cee3
--- /dev/null
+++ b/openpower/isa/fixedshift/rldcl_code.mdwn
@@ -0,0 +1,5 @@
+    n <- (RB)[XLEN-5:XLEN-1]
+    r <- ROTL64((RS), n)
+    b <- mb[5] || mb[0:4]
+    m <- MASK(b, (XLEN-1))
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/rldcr.mdwn b/openpower/isa/fixedshift/rldcr.mdwn
new file mode 100644 (file)
index 0000000..3da3107
--- /dev/null
+++ b/openpower/isa/fixedshift/rldcr.mdwn
@@ -0,0 +1,14 @@
+# Rotate Left Doubleword then Clear Right
+
+MDS-Form
+
+* rldcr RA,RS,RB,me (Rc=0)
+* rldcr.  RA,RS,RB,me (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rldcr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/rldcr_code.mdwn b/openpower/isa/fixedshift/rldcr_code.mdwn
new file mode 100644 (file)
index 0000000..9889d10
--- /dev/null
+++ b/openpower/isa/fixedshift/rldcr_code.mdwn
@@ -0,0 +1,5 @@
+    n <- (RB)[XLEN-5:XLEN-1]
+    r <- ROTL64((RS), n)
+    e <- me[5] || me[0:4]
+    m <- MASK(0, e)
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/rldic.mdwn b/openpower/isa/fixedshift/rldic.mdwn
new file mode 100644 (file)
index 0000000..33907b0
--- /dev/null
+++ b/openpower/isa/fixedshift/rldic.mdwn
@@ -0,0 +1,14 @@
+# Rotate Left Doubleword Immediate then Clear
+
+MD-Form
+
+* rldic RA,RS,sh,mb (Rc=0)
+* rldic.  RA,RS,sh,mb (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rldic_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/rldic_code.mdwn b/openpower/isa/fixedshift/rldic_code.mdwn
new file mode 100644 (file)
index 0000000..ea49222
--- /dev/null
+++ b/openpower/isa/fixedshift/rldic_code.mdwn
@@ -0,0 +1,5 @@
+    n <- sh
+    r <- ROTL64((RS), n)
+    b <- mb[5] || mb[0:4]
+    m <- MASK(b,  ¬n)
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/rldicl.mdwn b/openpower/isa/fixedshift/rldicl.mdwn
new file mode 100644 (file)
index 0000000..ff039f8
--- /dev/null
+++ b/openpower/isa/fixedshift/rldicl.mdwn
@@ -0,0 +1,14 @@
+# Rotate Left Doubleword Immediate then Clear Left
+
+MD-Form
+
+* rldicl RA,RS,sh,mb (Rc=0)
+* rldicl.  RA,RS,sh,mb (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rldicl_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/rldicl_code.mdwn b/openpower/isa/fixedshift/rldicl_code.mdwn
new file mode 100644 (file)
index 0000000..a59670c
--- /dev/null
+++ b/openpower/isa/fixedshift/rldicl_code.mdwn
@@ -0,0 +1,5 @@
+    n <- sh
+    r <- ROTL64((RS), n)
+    b <- mb[5] || mb[0:4]
+    m <- MASK(b, (XLEN-1))
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/rldicr.mdwn b/openpower/isa/fixedshift/rldicr.mdwn
new file mode 100644 (file)
index 0000000..10af0d6
--- /dev/null
+++ b/openpower/isa/fixedshift/rldicr.mdwn
@@ -0,0 +1,14 @@
+# Rotate Left Doubleword Immediate then Clear Right
+
+MD-Form
+
+* rldicr RA,RS,sh,me (Rc=0)
+* rldicr.  RA,RS,sh,me (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rldicr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/rldicr_code.mdwn b/openpower/isa/fixedshift/rldicr_code.mdwn
new file mode 100644 (file)
index 0000000..5ade62a
--- /dev/null
+++ b/openpower/isa/fixedshift/rldicr_code.mdwn
@@ -0,0 +1,5 @@
+    n <- sh
+    r <- ROTL64((RS), n)
+    e <- me[5] || me[0:4]
+    m <- MASK(0, e)
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/rldimi.mdwn b/openpower/isa/fixedshift/rldimi.mdwn
new file mode 100644 (file)
index 0000000..9058362
--- /dev/null
+++ b/openpower/isa/fixedshift/rldimi.mdwn
@@ -0,0 +1,17 @@
+# Rotate Left Doubleword Immediate then Mask Insert
+
+MD-Form
+
+* rldimi RA,RS,sh,mb (Rc=0)
+* rldimi.  RA,RS,sh,mb (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rldimi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
+
+<!-- Section 3.3.14.2 Fixed-Point Shift Instructions pages 107 - 110 -->

diff --git a/openpower/isa/fixedshift/rldimi_code.mdwn b/openpower/isa/fixedshift/rldimi_code.mdwn
new file mode 100644 (file)
index 0000000..ad44a52
--- /dev/null
+++ b/openpower/isa/fixedshift/rldimi_code.mdwn
@@ -0,0 +1,5 @@
+    n <- sh
+    r <- ROTL64((RS), n)
+    b <- mb[5] || mb[0:4]
+    m <- MASK(b,  ¬n)
+    RA <- r&m | (RA)& ¬m

diff --git a/openpower/isa/fixedshift/rlwimi.mdwn b/openpower/isa/fixedshift/rlwimi.mdwn
new file mode 100644 (file)
index 0000000..44a6c60
--- /dev/null
+++ b/openpower/isa/fixedshift/rlwimi.mdwn
@@ -0,0 +1,14 @@
+# Rotate Left Word Immediate then Mask Insert
+
+M-Form
+
+* rlwimi RA,RS,SH,MB,ME (Rc=0)
+* rlwimi.  RA,RS,SH,MB,ME (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rlwimi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/rlwimi_code.mdwn b/openpower/isa/fixedshift/rlwimi_code.mdwn
new file mode 100644 (file)
index 0000000..f27808b
--- /dev/null
+++ b/openpower/isa/fixedshift/rlwimi_code.mdwn
@@ -0,0 +1,4 @@
+    n <- SH
+    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
+    m <- MASK32(MB, ME)
+    RA <- r&m | (RA) & ¬m

diff --git a/openpower/isa/fixedshift/rlwinm.mdwn b/openpower/isa/fixedshift/rlwinm.mdwn
new file mode 100644 (file)
index 0000000..ca1cc4a
--- /dev/null
+++ b/openpower/isa/fixedshift/rlwinm.mdwn
@@ -0,0 +1,14 @@
+# Rotate Left Word Immediate then AND with Mask
+
+M-Form
+
+* rlwinm RA,RS,SH,MB,ME (Rc=0)
+* rlwinm.  RA,RS,SH,MB,ME (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rlwinm_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/rlwinm_code.mdwn b/openpower/isa/fixedshift/rlwinm_code.mdwn
new file mode 100644 (file)
index 0000000..2311947
--- /dev/null
+++ b/openpower/isa/fixedshift/rlwinm_code.mdwn
@@ -0,0 +1,4 @@
+    n <- SH
+    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
+    m <- MASK32(MB, ME)
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/rlwnm.mdwn b/openpower/isa/fixedshift/rlwnm.mdwn
new file mode 100644 (file)
index 0000000..0bd03b8
--- /dev/null
+++ b/openpower/isa/fixedshift/rlwnm.mdwn
@@ -0,0 +1,14 @@
+# Rotate Left Word then AND with Mask
+
+M-Form
+
+* rlwnm RA,RS,RB,MB,ME (Rc=0)
+* rlwnm.  RA,RS,RB,MB,ME (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/rlwnm_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/rlwnm_code.mdwn b/openpower/isa/fixedshift/rlwnm_code.mdwn
new file mode 100644 (file)
index 0000000..d49d3ce
--- /dev/null
+++ b/openpower/isa/fixedshift/rlwnm_code.mdwn
@@ -0,0 +1,4 @@
+    n <- (RB)[XLEN-5:XLEN-1]
+    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
+    m <- MASK32(MB, ME)
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/sld.mdwn b/openpower/isa/fixedshift/sld.mdwn
new file mode 100644 (file)
index 0000000..9532832
--- /dev/null
+++ b/openpower/isa/fixedshift/sld.mdwn
@@ -0,0 +1,14 @@
+# Shift Left Doubleword
+
+X-Form
+
+* sld RA,RS,RB (Rc=0)
+* sld.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/sld_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/sld_code.mdwn b/openpower/isa/fixedshift/sld_code.mdwn
new file mode 100644 (file)
index 0000000..c961410
--- /dev/null
+++ b/openpower/isa/fixedshift/sld_code.mdwn
@@ -0,0 +1,6 @@
+    n <- (RB)[XLEN-6:XLEN-1]
+    r <- ROTL64((RS), n)
+    if (RB)[XLEN-7] = 0 then
+         m <- MASK(0, XLEN-1-n)
+    else m <- [0]*XLEN
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/slw.mdwn b/openpower/isa/fixedshift/slw.mdwn
new file mode 100644 (file)
index 0000000..f6c5ae6
--- /dev/null
+++ b/openpower/isa/fixedshift/slw.mdwn
@@ -0,0 +1,14 @@
+# Shift Left Word
+
+X-Form
+
+* slw RA,RS,RB (Rc=0)
+* slw.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/slw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/slw_code.mdwn b/openpower/isa/fixedshift/slw_code.mdwn
new file mode 100644 (file)
index 0000000..308b21f
--- /dev/null
+++ b/openpower/isa/fixedshift/slw_code.mdwn
@@ -0,0 +1,6 @@
+    n <- (RB)[XLEN-5:XLEN-1]
+    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
+    if (RB)[XLEN-6] = 0 then
+         m <- MASK32(0, ((XLEN/2)-1-n))
+    else m <- [0]*XLEN
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/srad.mdwn b/openpower/isa/fixedshift/srad.mdwn
new file mode 100644 (file)
index 0000000..7c014b4
--- /dev/null
+++ b/openpower/isa/fixedshift/srad.mdwn
@@ -0,0 +1,15 @@
+# Shift Right Algebraic Doubleword
+
+X-Form
+
+* srad RA,RS,RB (Rc=0)
+* srad.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/srad_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/srad_code.mdwn b/openpower/isa/fixedshift/srad_code.mdwn
new file mode 100644 (file)
index 0000000..96ab99d
--- /dev/null
+++ b/openpower/isa/fixedshift/srad_code.mdwn
@@ -0,0 +1,10 @@
+    n <- (RB)[XLEN-6:XLEN-1]
+    r <- ROTL64((RS), XLEN-n)
+    if (RB)[XLEN-7] = 0 then
+        m <-  MASK(n, (XLEN-1))
+    else m <- [0]*XLEN
+    s <- (RS)[0]
+    RA <- r&m | ([s]*XLEN)& ¬m
+    carry <-  s & ((r&¬m) != 0)
+    CA    <-  carry
+    CA32  <-  carry

diff --git a/openpower/isa/fixedshift/sradi.mdwn b/openpower/isa/fixedshift/sradi.mdwn
new file mode 100644 (file)
index 0000000..4fe2651
--- /dev/null
+++ b/openpower/isa/fixedshift/sradi.mdwn
@@ -0,0 +1,15 @@
+# Shift Right Algebraic Doubleword Immediate
+
+XS-Form
+
+* sradi RA,RS,sh (Rc=0)
+* sradi.  RA,RS,sh (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/sradi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/sradi_code.mdwn b/openpower/isa/fixedshift/sradi_code.mdwn
new file mode 100644 (file)
index 0000000..4e886f8
--- /dev/null
+++ b/openpower/isa/fixedshift/sradi_code.mdwn
@@ -0,0 +1,8 @@
+    n <- sh
+    r <- ROTL64((RS), XLEN-n)
+    m <- MASK(n, (XLEN-1))
+    s <- (RS)[0]
+    RA <- r&m | ([s]*XLEN)& ¬m
+    carry <- s & ((r& ¬m) != 0)
+    CA    <- carry
+    CA32  <- carry

diff --git a/openpower/isa/fixedshift/sraw.mdwn b/openpower/isa/fixedshift/sraw.mdwn
new file mode 100644 (file)
index 0000000..2cd9955
--- /dev/null
+++ b/openpower/isa/fixedshift/sraw.mdwn
@@ -0,0 +1,15 @@
+# Shift Right Algebraic Word
+
+X-Form
+
+* sraw RA,RS,RB (Rc=0)
+* sraw.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/sraw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/sraw_code.mdwn b/openpower/isa/fixedshift/sraw_code.mdwn
new file mode 100644 (file)
index 0000000..9f17043
--- /dev/null
+++ b/openpower/isa/fixedshift/sraw_code.mdwn
@@ -0,0 +1,10 @@
+    n <- (RB)[XLEN-5:XLEN-1]
+    r <- ROTL32((RS)[XLEN/2:XLEN-1], XLEN-n)
+    if (RB)[XLEN-6] = 0 then
+        m <- MASK32(n, ((XLEN/2)-1))
+    else m <- [0]*XLEN
+    s <- (RS)[XLEN/2]
+    RA <- r&m | ([s]*XLEN)& ¬m
+    carry <-  s & ((r&¬m)[XLEN/2:XLEN-1] != 0)
+    CA    <-  carry
+    CA32  <-  carry

diff --git a/openpower/isa/fixedshift/srawi.mdwn b/openpower/isa/fixedshift/srawi.mdwn
new file mode 100644 (file)
index 0000000..5fbfa1b
--- /dev/null
+++ b/openpower/isa/fixedshift/srawi.mdwn
@@ -0,0 +1,15 @@
+# Shift Right Algebraic Word Immediate
+
+X-Form
+
+* srawi RA,RS,SH (Rc=0)
+* srawi.  RA,RS,SH (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/srawi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/srawi_code.mdwn b/openpower/isa/fixedshift/srawi_code.mdwn
new file mode 100644 (file)
index 0000000..9aa7924
--- /dev/null
+++ b/openpower/isa/fixedshift/srawi_code.mdwn
@@ -0,0 +1,8 @@
+    n <- SH
+    r <- ROTL32((RS)[XLEN/2:XLEN-1], 64-n)
+    m <- MASK32(n, ((XLEN/2)-1))
+    s <- (RS)[XLEN/2]
+    RA <- r&m | ([s]*XLEN)& ¬m
+    carry <- s & ((r&¬m)[XLEN/2:XLEN-1] != 0)
+    CA    <- carry
+    CA32  <- carry

diff --git a/openpower/isa/fixedshift/srd.mdwn b/openpower/isa/fixedshift/srd.mdwn
new file mode 100644 (file)
index 0000000..fded2c8
--- /dev/null
+++ b/openpower/isa/fixedshift/srd.mdwn
@@ -0,0 +1,14 @@
+# Shift Right Doubleword
+
+X-Form
+
+* srd RA,RS,RB (Rc=0)
+* srd.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/srd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/srd_code.mdwn b/openpower/isa/fixedshift/srd_code.mdwn
new file mode 100644 (file)
index 0000000..a760812
--- /dev/null
+++ b/openpower/isa/fixedshift/srd_code.mdwn
@@ -0,0 +1,6 @@
+    n <- (RB)[XLEN-6:XLEN-1]
+    r <- ROTL64((RS), XLEN-n)
+    if (RB)[XLEN-7] = 0 then
+        m <-  MASK(n, (XLEN-1))
+    else m <- [0]*XLEN
+    RA <- r & m

diff --git a/openpower/isa/fixedshift/srw.mdwn b/openpower/isa/fixedshift/srw.mdwn
new file mode 100644 (file)
index 0000000..6f55320
--- /dev/null
+++ b/openpower/isa/fixedshift/srw.mdwn
@@ -0,0 +1,14 @@
+# Shift Right Word
+
+X-Form
+
+* srw RA,RS,RB (Rc=0)
+* srw.  RA,RS,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedshift/srw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/fixedshift/srw_code.mdwn b/openpower/isa/fixedshift/srw_code.mdwn
new file mode 100644 (file)
index 0000000..473038d
--- /dev/null
+++ b/openpower/isa/fixedshift/srw_code.mdwn
@@ -0,0 +1,6 @@
+    n <- (RB)[XLEN-5:XLEN-1]
+    r <- ROTL32((RS)[XLEN/2:XLEN-1], XLEN-n)
+    if (RB)[XLEN-6] = 0 then
+        m <- MASK32(n, ((XLEN/2)-1))
+    else m <- [0]*XLEN
+    RA <- r & m