add lq and CONST_DQ

diff --git a/openpower/isatables/LDSTRM-2P-1S1D.csv b/openpower/isatables/LDSTRM-2P-1S1D.csv
index f3b1c0921e4661ceda39f4695c189a3aa78833a2..02cfb5dcf0acd3464efb7d78cd16a39e5735258d 100644 (file)
--- a/openpower/isatables/LDSTRM-2P-1S1D.csv
+++ b/openpower/isatables/LDSTRM-2P-1S1D.csv
@@ -5,5 +5,6 @@ lhz,LDST_IMM,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
 lha,LDST_IMM,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
 lfs,LDST_IMM,,2P,EXTRA3,EN,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0
 lfd,LDST_IMM,,2P,EXTRA3,EN,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0
+lq,LDST_IMM,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
 ld,LDST_IMM,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
 lwa,LDST_IMM,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0

diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv
index a6e112bd6551cb68d4f2028aa89341edab7c460f..a091f45cd30b6dd1b833ecbf9539d136b733f6b6 100644 (file)
--- a/openpower/isatables/major.csv
+++ b/openpower/isatables/major.csv
@@ -22,6 +22,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D,
 32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D,
 33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D,
+56,LDST,OP_LOAD,RA_OR_ZERO,CONST_DQ,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lq,DQ,
 7,MUL,OP_MUL_L64,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D,
 24,LOGICAL,OP_OR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D,
 25,LOGICAL,OP_OR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D,

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index f3da7119cf0453b0b1e1d745ea103e2fb999ba63..7177776044eead71db5164b0f5f4f66d68fdd1df 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -745,6 +745,7 @@ class In2Sel(Enum):
     CONST_SVDS = 16  # for SVDS-Form
     CONST_XBI = 17
     CONST_DXHI4 = 18 # for addpcis
+    CONST_DQ = 19 # for ld/st-quad
 
 
 @unique

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 9227191802a11835efeac633aabf2448a256a5e0..107f60ff6b08f134fcb9a22d7f3548235e87a1fe 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -329,6 +329,23 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_22_ld(self):
+        expected = [
+                    "ld 4,0(5)",
+                    "ld 4,16(5)",       # sigh, needs magic-shift (D||0b00)
+                    "sv.ld 4,16(5)",    # ditto
+                        ]
+        self._do_tst(expected)
+
+    def test_23_lq(self):
+        expected = [
+                    "lq 4,0(5)",
+                    "lq 4,16(5)",      # ditto, magic-shift (DQ||0b0000)
+                    "lq 4,32(5)",      # ditto
+                    "sv.lq 4,16(5)",   # ditto
+                        ]
+        self._do_tst(expected)
+
 
 if __name__ == "__main__":
     unittest.main()