ct_reg.setup_internals_mem();
ct_reg.setup_stdcells_mem();
- for (auto &mod_it : design->modules_) {
- if (!design->selected_whole_module(mod_it.first)) {
- if (design->selected(mod_it.second))
- log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
+ for (auto mod : design->modules()) {
+ if (!design->selected_whole_module(mod->name)) {
+ if (design->selected(mod))
+ log("Skipping module %s as it is only partially selected.\n", id2cstr(mod->name));
continue;
}
- if (mod_it.second->processes.size() > 0) {
- log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
+ if (!mod->processes.empty()) {
+ log("Skipping module %s as it contains processes.\n", mod->name.c_str());
} else {
- rmunused_module(mod_it.second, purge_mode, true);
+ rmunused_module(mod, purge_mode, true);
}
}
count_rm_cells = 0;
count_rm_wires = 0;
- for (auto &mod_it : design->modules_) {
- if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0)
+ for (auto mod : design->modules()) {
+ if (design->selected_whole_module(mod->name) && mod->processes.empty())
do {
design->scratchpad_unset("opt.did_something");
- rmunused_module(mod_it.second, purge_mode, false);
+ rmunused_module(mod, purge_mode, false);
} while (design->scratchpad_get_bool("opt.did_something"));
}