change 0 bits in RA field to // for int/fp mv/cvts as luke requested

https://libre-soc.org/irclog/latest.log.html#t2023-04-07T00:34:47

diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
index 7bf99f9f176640599372e4a2e9f14a7405afe297..11468dc4accf34fd60aa419e729cb87e3f61eb0d 100644 (file)
--- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
+++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
@@ -45,7 +45,7 @@ File to another.
 
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form   |
 |-----|------|-------|-------|-------|----|--------|
-| PO  | RT   | 0     | FRB   | XO    | Rc | X-Form |
+| PO  | RT   | //    | FRB   | XO    | Rc | X-Form |
 
 ```
     RT <- (FRB)
@@ -75,7 +75,7 @@ Special Registers altered:
 
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form   |
 |-----|------|-------|-------|-------|----|--------|
-| PO  | RT   | 0     | FRB   | XO    | Rc | X-Form |
+| PO  | RT   | //    | FRB   | XO    | Rc | X-Form |
 
 ```
     RT <- [0] * 32 || SINGLE((FRB))  # SINGLE since that's what stfs uses
@@ -107,7 +107,7 @@ Special Registers altered:
 
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form   |
 |-----|------|-------|-------|-------|----|--------|
-| PO  | FRT  | 0     | RB    | XO    | Rc | X-Form |
+| PO  | FRT  | //    | RB    | XO    | Rc | X-Form |
 
 ```
     FRT <- (RB)
@@ -137,7 +137,7 @@ Special Registers altered:
 
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form   |
 |-----|------|-------|-------|-------|----|--------|
-| PO  | FRT  | 0     | RB    | XO    | Rc | X-Form |
+| PO  | FRT  | //    | RB    | XO    | Rc | X-Form |
 
 ```
     FRT <- DOUBLE((RB)[32:63])  # DOUBLE since that's what lfs uses
@@ -176,7 +176,7 @@ as exceptions.
 
 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form   |
 |-----|------|-------|-------|-------|-------|----|--------|
-| PO  | FRT  | IT    | 0     | RB    | XO    | Rc | X-Form |
+| PO  | FRT  | IT    | //    | RB    | XO    | Rc | X-Form |
 
 ```
     if IT[0] = 0 then  # 32-bit int -> 64-bit float
@@ -257,7 +257,7 @@ Special Registers altered:
 
 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form   |
 |-----|------|-------|-------|-------|-------|----|--------|
-| PO  | FRT  | IT    | 0     | RB    | XO    | Rc | X-Form |
+| PO  | FRT  | IT    | //    | RB    | XO    | Rc | X-Form |
 
 ```
     # rounding may be necessary. based off xscvuxdsp

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 59d80fe74d9632f19128838cf356acc9b51b0e59..d903b9e8e6d293287b47de2361946189a8862b0f 100644 (file)
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -118,10 +118,10 @@ Add the following entries to Book I 1.6.1.19 XO-FORM:
 Add the following entries to Book I 1.6.1.15 X-FORM:
 
 ```
-    |0   |6    |11  |13 |16   |21  |31  |
-    | PO | FRT | IT | 0 | RB  | XO | Rc |
-    | PO | FRT | 0      | RB  | XO | Rc |
-    | PO | RT  | 0      | FRB | XO | Rc |
+    |0   |6    |11  |13  |16   |21  |31  |
+    | PO | FRT | IT | // | RB  | XO | Rc |
+    | PO | FRT | //      | RB  | XO | Rc |
+    | PO | RT  | //      | FRB | XO | Rc |
 ```
 
 ## Instruction Fields