2006-07-19 Paul Brook <paul@codesourcery.com>

	gas/
	* config/tc-arm.c (insns): Fix rbit Arm opcode.
	gas/testsuite/
	* gas/arm/archv6t2.d: Adjust expected output for rbit.
	opcodes/
	* armd-dis.c (arm_opcodes): Fix rbit opcode.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6b414dc1f2c35ef0b9153b88cfadaeaf011f14ba..999b795b2d3a138d803c850f926d0c3fb7bd73d4 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2006-07-19  Paul Brook  <paul@codesourcery.com>
+
+       * config/tc-arm.c (insns): Fix rbit Arm opcode.
+
 2006-07-18  Paul Brook  <paul@codesourcery.com>
 
        * tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index fe9d77521fc733e2893642204752c69a1cf216b7..87240977e89eb1779cb8fd3deb683d37761b2a9e 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -14758,7 +14758,7 @@ static const struct asm_opcode insns[] =
  TCE(mls,      0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
  TCE(movw,     3000000, f2400000, 2, (RRnpc, HALF),                mov16, t_mov16),
  TCE(movt,     3400000, f2c00000, 2, (RRnpc, HALF),                mov16, t_mov16),
- TCE(rbit,     3ff0f30, fa90f0a0, 2, (RR, RR),                     rd_rm, t_rbit),
+ TCE(rbit,     6ff0f30, fa90f0a0, 2, (RR, RR),                     rd_rm, t_rbit),
 
  TC3(ldrht,    03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
  TC3(ldrsht,   03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index b3b6d3e31e288bbd883a139b7a0bf110d059e05f..9366e8d65e7df4a36b43b5fbd93cd1a7f178202c 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2006-07-19  Paul Brook  <paul@codesourcery.com>
+
+       * gas/arm/archv6t2.d: Adjust expected output for rbit.
+
 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 
        * gas/i386/opcode.s: Add sldt, smsw and str.

diff --git a/gas/testsuite/gas/arm/archv6t2.d b/gas/testsuite/gas/arm/archv6t2.d
index 8e8b0387a336fe132a3850ee21fc2855bb88e28c..a1a4120e45357a455cb7fca17636ae25365f564b 100644 (file)
--- a/gas/testsuite/gas/arm/archv6t2.d
+++ b/gas/testsuite/gas/arm/archv6t2.d
@@ -24,10 +24,10 @@ Disassembly of section .text:
 0+40 <[^>]+> e7a00059  sbfx    r0, r9, #0, #1
 0+44 <[^>]+> e7a008d0  sbfx    r0, r0, #17, #1
 0+48 <[^>]+> e7b10050  sbfx    r0, r0, #0, #18
-0+4c <[^>]+> e3ff0f30  rbit    r0, r0
-0+50 <[^>]+> 13ff0f30  rbitne  r0, r0
-0+54 <[^>]+> e3ff9f30  rbit    r9, r0
-0+58 <[^>]+> e3ff0f39  rbit    r0, r9
+0+4c <[^>]+> e6ff0f30  rbit    r0, r0
+0+50 <[^>]+> 16ff0f30  rbitne  r0, r0
+0+54 <[^>]+> e6ff9f30  rbit    r9, r0
+0+58 <[^>]+> e6ff0f39  rbit    r0, r9
 0+5c <[^>]+> e0600090  mls     r0, r0, r0, r0
 0+60 <[^>]+> 10600090  mlsne   r0, r0, r0, r0
 0+64 <[^>]+> e0690090  mls     r9, r0, r0, r0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index eefd66275215c8ec7fda7f41e5a34af64ba42680..d78cb7c2514c9c9dcec1c13d3da2771075c1b6d1 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2006-07-19  Paul Brook  <paul@codesourcery.com>
+
+       * armd-dis.c (arm_opcodes): Fix rbit opcode.
+
 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index a37557889b6f75e5314392c221aef7ac2907974b..147e149ecbe434abb3e69928e1bbe2a5d46cfdea 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -761,7 +761,7 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
   {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
   {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
-  {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
+  {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
   {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
 
   /* ARM V6Z instructions.  */