(no commit message)

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index baee7edf2a1b05ba7de5dc850edd9abb25ce640a..abcd595bd9ca86a4630f7d389ab3a2ce31165fc5 100644 (file)
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -23,11 +23,11 @@ explicit naming of the registers to be tagged (taking up 5 bits each time).
 
 non-SVP mode uses the extended format (see main VBLOCK spec [[vblock_format]])
 
-When P48 Mode is enabled (0b01), the P48 prefix follows the VBLOCK header
+When P48 Mode is enabled (0b01), the P48 prefix follows the VBLOCK header, and an additional itype may be applied to the src operand(s).
 
-| 15:11 | 10:0       |
-| -     | ---------- |
-| rsvd  | P48-Prefix |
+| 15:13 | 12:11 | 10:0       |
+| -     | -     | ---------- |
+| rsvd  | itype | P48-Prefix |
 
 When P64 Mode is enabled (0b10), the P64 prefix also follows:
 
@@ -41,6 +41,8 @@ registers. The reason why Twin-SVP's prefix is only P48 is because P64 can chang
 
 VL/MVL from a P64 prefix is applied as if a [[specification/sv.setvl]] instruction had been executed as a hidden (first, implicit) instruction in the VBLOCK. This *includes* modification of SV CSR STATE.
 
+itype is described in [[sv_prefix_ptoposal]]. The additional itype on the src operand(s) allows, for example, a LD of 8 bit vectors to be auto-converted to 16 bit signed in a single instruction.  More examples on elwidth polymorphism is in the [[appendix]].
+
 # Rules
 
 * SVP-VBLOCK is read (48/64), and indicates that certain registers are