READ_FREG not to return an alternative type

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 1f203542ccf938f6054db41d073036d4aac9e6d7..5c5d6285884f47b111fba2f00a57112fbc2e46cb 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -125,7 +125,7 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
     STATE.XPR.write(reg, wval);
 }
 
-sv_freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec)
+freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec)
 {
     reg_t reg = spec.reg;
     uint8_t elwidth = _insn->reg_elwidth(reg, true);

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index ab484bbb4d32cc0fc3ff8f602d73f3ac506d84f5..90f2791126da9435400d1116fd143b85cf26b193 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -85,7 +85,7 @@ public:
     void (WRITE_FRD)(sv_float64_t value);
     void (WRITE_FRD)(sv_float32_t value);
     reg_t (READ_REG)(reg_spec_t const& i);
-    sv_freg_t (READ_FREG)(reg_spec_t const& i);
+    freg_t (READ_FREG)(reg_spec_t const& i);
 
     processor_t *p;
     sv_insn_t *_insn;