OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
/* XXX this should not be so rigid and it still doesn't work right */
-OUT_CS_REG(R300_RB3D_COLORPITCH0, (w / 4) | R300_COLOR_TILE_ENABLE |
- R300_COLOR_FORMAT_ARGB8888);
+debug_printf("Buffer width (stride): %d\n", dest->stride);
+OUT_CS_REG(R300_RB3D_COLORPITCH0, (dest->stride >> 2) | R300_COLOR_FORMAT_ARGB8888);
OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
/* XXX Packet3 */
OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
/* Radeons enjoy things in multiples of 32. */
/* XXX NPOT -> 64, not 32 */
- stride = (base->nblocksx[i] * base->block.size + 31) & ~31;
+ stride = (base->nblocksx[i] * base->block.size + 63) & ~63;
size = stride * base->nblocksy[i] * base->depth[i];
/* XXX 64 for NPOT */
- tex->offset[i] = (tex->size + 31) & ~31;
+ tex->offset[i] = (tex->size + 63) & ~63;
tex->size = tex->offset[i] + size;
}
}
r300_setup_miptree(tex);
- tex->buffer = screen->buffer_create(screen, 32,
+ tex->buffer = screen->buffer_create(screen, 63,
PIPE_BUFFER_USAGE_PIXEL,
tex->size);
surface->nblocksy = texture->nblocksy[level];
/* XXX save the actual stride instead plz kthnxbai */
surface->stride =
- (texture->nblocksx[level] * texture->block.size + 31) & ~31;
+ (texture->nblocksx[level] * texture->block.size + 63) & ~63;
surface->offset = offset;
surface->usage = flags;
surface->status = PIPE_SURFACE_STATUS_DEFINED;