arch-power: Add fields for DX form instructions

This introduces the extended opcode field and the fields
d0, d1 and d2 for DX form instructions.

Change-Id: Iac52bca39993e4a5f299f33d356e36037c516130
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa
index fcf592f8a9cdfcdfb4bdfc44b3f8d41b3d72b776..dcecdd40e35ae97c3a433ad60e310327932e87d0 100644 (file)
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -39,6 +39,7 @@
 def bitfield PO            <31:26>;
 def bitfield A_XO          <5:1>;
 def bitfield DS_XO         <1:0>;
+def bitfield DX_XO         <5:1>;
 def bitfield X_XO          <10:1>;
 def bitfield XFL_XO        <10:1>;
 def bitfield XFX_XO        <10:1>;

diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index 929f765e08c2ae63e15d1bcc3d86e9f1340e1fe7..8f499bbf1b3ecc115a235f12e4e0eeeb48c4ed52 100644 (file)
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -55,6 +55,9 @@ BitUnion32(ExtMachInst)
     Bitfield<15,  0> si;
     Bitfield<15,  0> d;
     Bitfield<15,  2> ds;
+    Bitfield<15,  6> d0;
+    Bitfield<20, 16> d1;
+    Bitfield< 1,  0> d2;
 
     // Special purpose register identifier
     Bitfield<20, 11> spr;