Revert "Fold loop"
authorEddie Hung <eddie@fpgeh.com>
Wed, 27 Nov 2019 20:35:25 +0000 (12:35 -0800)
committerEddie Hung <eddie@fpgeh.com>
Wed, 27 Nov 2019 20:35:25 +0000 (12:35 -0800)
This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118.

backends/aiger/xaiger.cc

index f17a4c775cf3509753a8e031d53b51dd0aba59a2..8b809b2e22cf7f7e9f957a83af2c739e889a6f07 100644 (file)
@@ -184,7 +184,6 @@ struct XAigerWriter
                                        if (bit != wirebit)
                                                alias_map[bit] = wirebit;
                                        input_bits.insert(wirebit);
-                                       undriven_bits.erase(bit);
                                }
 
                                if (wire->port_output || keep) {
@@ -192,8 +191,6 @@ struct XAigerWriter
                                                if (bit != wirebit)
                                                        alias_map[wirebit] = bit;
                                                output_bits.insert(wirebit);
-                                               if (!wire->port_input)
-                                                       unused_bits.erase(bit);
                                        }
                                        else
                                                log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@@ -201,6 +198,12 @@ struct XAigerWriter
                        }
                }
 
+               for (auto bit : input_bits)
+                       undriven_bits.erase(sigmap(bit));
+               for (auto bit : output_bits)
+                       if (!bit.wire->port_input)
+                               unused_bits.erase(bit);
+
                // TODO: Speed up toposort -- ultimately we care about
                //       box ordering, but not individual AIG cells
                dict<SigBit, pool<IdString>> bit_drivers, bit_users;