cores/clock: add divclk_divide_range on S6PLL/S6DCM

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index e496673db4a100ba39e8e4a5072e8f9ad58a33ef..5757ad754372eb5eb293cb00898ce8ebd996cc9a 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -126,6 +126,7 @@ class S6PLL(XilinxClocking):
 
     def __init__(self, speedgrade=-1):
         XilinxClocking.__init__(self)
+        self.divclk_divide_range = (1, 52 + 1)
         self.vco_freq_range = {
             -1: (400e6, 1000e6),
             -2: (400e6, 1000e6),
@@ -164,6 +165,7 @@ class S6DCM(XilinxClocking):
 
     def __init__(self, speedgrade=-1):
         XilinxClocking.__init__(self)
+        self.divclk_divide_range = (1, 1) # FIXME
         self.clkin_freq_range = {
             -1: (0.5e6, 200e6),
             -2: (0.5e6, 333e6),