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isatables: split dsld/dsrd Rc versions
authorDmitry Selyutin <ghostmansd@gmail.com>
Sun, 18 Dec 2022 18:35:26 +0000 (21:35 +0300)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:16 +0000 (19:51 +0100)
openpower/isatables/RM-1P-3S1D.csv patch | blob | history
openpower/isatables/minor_4.csv patch | blob | history

diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv
index 9a3c6c150d45ea0ad96566cc88d9d9db9cf8c7a4..526af3f9e06270348698202c703c65929c325f48 100644 (file)
--- a/openpower/isatables/RM-1P-3S1D.csv
+++ b/openpower/isatables/RM-1P-3S1D.csv
@@ -40,9 +40,9 @@ divmod2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 absdacs,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
 absdacu,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
 dsld,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
-dsld,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
-dsrd,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
+dsld.,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
 dsrd,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
+dsrd.,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
 pcdec,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
 ternlogi,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
 ffmsubs,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv
index 3121bd7cc9d6e498f7da34bebb1d60af3749141d..869a50cad270f2c27aef4ea6258ab39c803de8b7 100644 (file)
--- a/openpower/isatables/minor_4.csv
+++ b/openpower/isatables/minor_4.csv
@@ -8,7 +8,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,,
 58,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-52,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-53,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-54,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-55,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+52,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+53,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,dsld.,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+54,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+55,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,dsrd.,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg