X86: Put ldst into the microcode (the earlier changeset didn't really).

Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.

--HG--
extra : convert_revision : 7c6050cb4798d287fe7d3cc4bb8c20dfa40ad2be

diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
index 87fbb796ce3c0810ebfe6f802a9445c676e14bf2..e58fc00d7de8d0e6119814bf2e88d62a2b3f99cb 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
@@ -68,7 +68,7 @@ def macroop ADD_R_I
 def macroop ADD_M_I
 {
     limm t2, imm
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -77,14 +77,14 @@ def macroop ADD_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, riprel, disp
 };
 
 def macroop ADD_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -92,7 +92,7 @@ def macroop ADD_M_R
 def macroop ADD_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, riprel, disp
 };
@@ -137,7 +137,7 @@ def macroop SUB_R_P
 def macroop SUB_M_I
 {
     limm t2, imm
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -146,14 +146,14 @@ def macroop SUB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, riprel, disp
 };
 
 def macroop SUB_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -161,7 +161,7 @@ def macroop SUB_M_R
 def macroop SUB_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, riprel, disp
 };
@@ -180,7 +180,7 @@ def macroop ADC_R_I
 def macroop ADC_M_I
 {
     limm t2, imm
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -189,14 +189,14 @@ def macroop ADC_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, riprel, disp
 };
 
 def macroop ADC_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -204,7 +204,7 @@ def macroop ADC_M_R
 def macroop ADC_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, riprel, disp
 };
@@ -249,7 +249,7 @@ def macroop SBB_R_P
 def macroop SBB_M_I
 {
     limm t2, imm
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -258,14 +258,14 @@ def macroop SBB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, riprel, disp
 };
 
 def macroop SBB_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -273,7 +273,7 @@ def macroop SBB_M_R
 def macroop SBB_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, seg, riprel, disp
 };
@@ -285,7 +285,7 @@ def macroop NEG_R
 
 def macroop NEG_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
     st t1, seg, sib, disp
 };
@@ -293,7 +293,7 @@ def macroop NEG_M
 def macroop NEG_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
     st t1, seg, riprel, disp
 };

diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
index 2a8024eee44350565f1515ca3f789807cc9dd825..7afd249925fe97c054ec56208ac58bd519fdbe85 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
@@ -61,7 +61,7 @@ def macroop INC_R
 
 def macroop INC_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     st t1, seg, sib, disp
 };
@@ -69,7 +69,7 @@ def macroop INC_M
 def macroop INC_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     st t1, seg, riprel, disp
 };
@@ -81,7 +81,7 @@ def macroop DEC_R
 
 def macroop DEC_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     st t1, seg, sib, disp
 };
@@ -89,7 +89,7 @@ def macroop DEC_M
 def macroop DEC_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     st t1, seg, riprel, disp
 };

diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
index 504e9ab0a7cc23a5b7123e8aa0e57d89e96f8588..f4f856974d1291e57680bd0d43afaf4bf2af80f5 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
@@ -61,8 +61,9 @@ def macroop CALL_NEAR_I
 
     limm t1, imm
     rdip t7
+    # Check target of call
+    st t7, ss, [0, t0, rsp], "-env.dataSize"
     subi rsp, rsp, dsz
-    st t7, ss, [0, t0, rsp]
     wrip t7, t1
 };
 
@@ -72,8 +73,9 @@ def macroop CALL_NEAR_R
     .adjust_env oszIn64Override
 
     rdip t1
+    # Check target of call
+    st t1, ss, [0, t0, rsp], "-env.dataSize"
     subi rsp, rsp, dsz
-    st t1, ss, [0, t0, rsp]
     wripi reg, 0
 };
 
@@ -84,8 +86,9 @@ def macroop CALL_NEAR_M
 
     rdip t7
     ld t1, seg, sib, disp
+    # Check target of call
+    st t7, ss, [0, t0, rsp], "-env.dataSize"
     subi rsp, rsp, dsz
-    st t7, ss, [0, t0, rsp]
     wripi t1, 0
 };
 
@@ -96,8 +99,9 @@ def macroop CALL_NEAR_P
 
     rdip t7
     ld t1, seg, riprel, disp
+    # Check target of call
+    st t7, ss, [0, t0, rsp], "-env.dataSize"
     subi rsp, rsp, dsz
-    st t7, ss, [0, t0, rsp]
     wripi t1, 0
 };
 '''

diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
index 1efddf1d204137dd13c320bf4b42f18b5de57e07..8993f5ac42c5797799c71a8ae8c0541e955a854c 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
@@ -60,6 +60,7 @@ def macroop RET_NEAR
     .adjust_env oszIn64Override
 
     ld t1, ss, [1, t0, rsp]
+    # Check address of return
     addi rsp, rsp, dsz
     wripi t1, 0
 };
@@ -71,6 +72,7 @@ def macroop RET_NEAR_I
 
     limm t2, imm
     ld t1, ss, [1, t0, rsp]
+    # Check address of return
     addi rsp, rsp, dsz
     add rsp, rsp, t2
     wripi t1, 0

diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
index 9e680703947f73cc4305d5cea9fe0b32d4d8ef1b..5fb2b21720a193165e2557976c8e062fa636b9f0 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
@@ -67,6 +67,7 @@ def macroop POP_M {
     .adjust_env oszIn64Override
 
     ld t1, ss, [1, t0, rsp]
+    # Check stack address
     addi rsp, rsp, dsz
     st t1, seg, sib, disp
 };
@@ -77,6 +78,7 @@ def macroop POP_P {
 
     rdip t7
     ld t1, ss, [1, t0, rsp]
+    # Check stack address
     addi rsp, rsp, dsz
     st t1, seg, riprel, disp
 };
@@ -96,8 +98,8 @@ def macroop PUSH_I {
     .adjust_env oszIn64Override
 
     limm t1, imm
+    st t1, ss, [1, t0, rsp], "-env.dataSize"
     subi rsp, rsp, dsz
-    st t1, ss, [1, t0, rsp]
 };
 
 def macroop PUSH_M {
@@ -105,8 +107,8 @@ def macroop PUSH_M {
     .adjust_env oszIn64Override
 
     ld t1, seg, sib, disp
+    st t1, ss, [1, t0, rsp], "-env.dataSize"
     subi rsp, rsp, dsz
-    st t1, ss, [1, t0, rsp]
 };
 
 def macroop PUSH_P {
@@ -115,11 +117,13 @@ def macroop PUSH_P {
 
     rdip t7
     ld t1, seg, riprel, disp
+    # Check stack address
     subi rsp, rsp, dsz
     st t1, ss, [1, t0, rsp]
 };
 
 def macroop PUSHA {
+    # Check all the stack addresses.
     st rax, ss, [1, t0, rsp], "-0 * env.dataSize"
     st rcx, ss, [1, t0, rsp], "-1 * env.dataSize"
     st rdx, ss, [1, t0, rsp], "-2 * env.dataSize"
@@ -132,6 +136,7 @@ def macroop PUSHA {
 };
 
 def macroop POPA {
+    # Check all the stack addresses.
     ld rdi, ss, [1, t0, rsp], "0 * env.dataSize"
     ld rsi, ss, [1, t0, rsp], "1 * env.dataSize"
     ld rbp, ss, [1, t0, rsp], "2 * env.dataSize"
@@ -146,8 +151,9 @@ def macroop LEAVE {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
 
-    mov rsp, rsp, rbp
-    ld rbp, ss, [1, t0, rsp]
+    mov t1, t1, rbp
+    ld rbp, ss, [1, t0, t1]
+    mov rsp, rsp, t1
     addi rsp, rsp, dsz
 };
 '''

diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
index 9478c71fca4b1869bd54efbfcc6e0e7d72223767..3f243f5d821f01ff2dd642829bc7a34f1c9616df 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
@@ -68,7 +68,7 @@ def macroop XCHG_R_R
 
 def macroop XCHG_R_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     st reg, seg, sib, disp
     mov reg, reg, t1
 };
@@ -76,14 +76,14 @@ def macroop XCHG_R_M
 def macroop XCHG_R_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     st reg, seg, riprel, disp
     mov reg, reg, t1
 };
 
 def macroop XCHG_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     st reg, seg, sib, disp
     mov reg, reg, t1
 };
@@ -91,7 +91,7 @@ def macroop XCHG_M_R
 def macroop XCHG_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     st reg, seg, riprel, disp
     mov reg, reg, t1
 };

diff --git a/src/arch/x86/isa/insts/general_purpose/logical.py b/src/arch/x86/isa/insts/general_purpose/logical.py
index 2137ae82f6bc8283a4d1740b5f99f4dd6233847c..a8b7c6a4553aeaaafab680e73e2fc35d4818c77c 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/logical.py
+++ b/src/arch/x86/isa/insts/general_purpose/logical.py
@@ -62,7 +62,7 @@ def macroop OR_R_R
 def macroop OR_M_I
 {
     limm t2, imm
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -71,14 +71,14 @@ def macroop OR_P_I
 {
     limm t2, imm
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, riprel, disp
 };
 
 def macroop OR_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -86,7 +86,7 @@ def macroop OR_M_R
 def macroop OR_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, riprel, disp
 };
@@ -124,7 +124,7 @@ def macroop XOR_R_I
 def macroop XOR_M_I
 {
     limm t2, imm
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -133,14 +133,14 @@ def macroop XOR_P_I
 {
     limm t2, imm
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, riprel, disp
 };
 
 def macroop XOR_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -148,7 +148,7 @@ def macroop XOR_M_R
 def macroop XOR_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, riprel, disp
 };
@@ -192,7 +192,7 @@ def macroop AND_R_I
 
 def macroop AND_M_I
 {
-    ld t2, seg, sib, disp
+    ldst t2, seg, sib, disp
     limm t1, imm
     and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
     st t2, seg, sib, disp
@@ -201,7 +201,7 @@ def macroop AND_M_I
 def macroop AND_P_I
 {
     rdip t7
-    ld t2, seg, riprel, disp
+    ldst t2, seg, riprel, disp
     limm t1, imm
     and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
     st t2, seg, riprel, disp
@@ -209,7 +209,7 @@ def macroop AND_P_I
 
 def macroop AND_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, sib, disp
 };
@@ -217,7 +217,7 @@ def macroop AND_M_R
 def macroop AND_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, seg, riprel, disp
 };
@@ -231,7 +231,7 @@ def macroop NOT_R
 def macroop NOT_M
 {
     limm t1, -1
-    ld t2, seg, sib, disp
+    ldst t2, seg, sib, disp
     xor t2, t2, t1
     st t2, seg, sib, disp
 };
@@ -240,7 +240,7 @@ def macroop NOT_P
 {
     limm t1, -1
     rdip t7
-    ld t2, seg, riprel, disp
+    ldst t2, seg, riprel, disp
     xor t2, t2, t1
     st t2, seg, riprel, disp
 };

diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py
index a13df3a6457419f1a4f31d4e58404943ab9615a1..b5ae9560e463120210a54e36ca2030ec924dec61 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py
+++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py
@@ -61,7 +61,7 @@ def macroop ROL_R_I
 
 def macroop ROL_M_I
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     roli t1, t1, imm
     st t1, seg, sib, disp
 };
@@ -69,7 +69,7 @@ def macroop ROL_M_I
 def macroop ROL_P_I
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     roli t1, t1, imm
     st t1, seg, riprel, disp
 };
@@ -81,7 +81,7 @@ def macroop ROL_1_R
 
 def macroop ROL_1_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     roli t1, t1, 1
     st t1, seg, sib, disp
 };
@@ -89,7 +89,7 @@ def macroop ROL_1_M
 def macroop ROL_1_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     roli t1, t1, 1
     st t1, seg, riprel, disp
 };
@@ -101,7 +101,7 @@ def macroop ROL_R_R
 
 def macroop ROL_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rol t1, t1, reg
     st t1, seg, sib, disp
 };
@@ -109,7 +109,7 @@ def macroop ROL_M_R
 def macroop ROL_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rol t1, t1, reg
     st t1, seg, riprel, disp
 };
@@ -121,7 +121,7 @@ def macroop ROR_R_I
 
 def macroop ROR_M_I
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rori t1, t1, imm
     st t1, seg, sib, disp
 };
@@ -129,7 +129,7 @@ def macroop ROR_M_I
 def macroop ROR_P_I
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rori t1, t1, imm
     st t1, seg, riprel, disp
 };
@@ -141,7 +141,7 @@ def macroop ROR_1_R
 
 def macroop ROR_1_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rori t1, t1, 1
     st t1, seg, sib, disp
 };
@@ -149,7 +149,7 @@ def macroop ROR_1_M
 def macroop ROR_1_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rori t1, t1, 1
     st t1, seg, riprel, disp
 };
@@ -161,7 +161,7 @@ def macroop ROR_R_R
 
 def macroop ROR_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     ror t1, t1, reg
     st t1, seg, sib, disp
 };
@@ -169,7 +169,7 @@ def macroop ROR_M_R
 def macroop ROR_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     ror t1, t1, reg
     st t1, seg, riprel, disp
 };
@@ -181,7 +181,7 @@ def macroop RCL_R_I
 
 def macroop RCL_M_I
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rcli t1, t1, imm
     st t1, seg, sib, disp
 };
@@ -189,7 +189,7 @@ def macroop RCL_M_I
 def macroop RCL_P_I
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rcli t1, t1, imm
     st t1, seg, riprel, disp
 };
@@ -201,7 +201,7 @@ def macroop RCL_1_R
 
 def macroop RCL_1_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rcli t1, t1, 1
     st t1, seg, sib, disp
 };
@@ -209,7 +209,7 @@ def macroop RCL_1_M
 def macroop RCL_1_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rcli t1, t1, 1
     st t1, seg, riprel, disp
 };
@@ -221,7 +221,7 @@ def macroop RCL_R_R
 
 def macroop RCL_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rcl t1, t1, reg
     st t1, seg, sib, disp
 };
@@ -229,7 +229,7 @@ def macroop RCL_M_R
 def macroop RCL_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rcl t1, t1, reg
     st t1, seg, riprel, disp
 };
@@ -241,7 +241,7 @@ def macroop RCR_R_I
 
 def macroop RCR_M_I
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rcri t1, t1, imm
     st t1, seg, sib, disp
 };
@@ -249,7 +249,7 @@ def macroop RCR_M_I
 def macroop RCR_P_I
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rcri t1, t1, imm
     st t1, seg, riprel, disp
 };
@@ -261,7 +261,7 @@ def macroop RCR_1_R
 
 def macroop RCR_1_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rcri t1, t1, 1
     st t1, seg, sib, disp
 };
@@ -269,7 +269,7 @@ def macroop RCR_1_M
 def macroop RCR_1_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rcri t1, t1, 1
     st t1, seg, riprel, disp
 };
@@ -281,7 +281,7 @@ def macroop RCR_R_R
 
 def macroop RCR_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     rcr t1, t1, reg
     st t1, seg, sib, disp
 };
@@ -289,7 +289,7 @@ def macroop RCR_M_R
 def macroop RCR_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     rcr t1, t1, reg
     st t1, seg, riprel, disp
 };

diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
index 6c688cca35ddcb3264fb235dfdfc28cfe1b5efbb..ed7d761b8fe3d90f415998f6d942db6944f449f5 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
@@ -61,7 +61,7 @@ def macroop SAL_R_I
 
 def macroop SAL_M_I
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     slli t1, t1, imm, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -69,7 +69,7 @@ def macroop SAL_M_I
 def macroop SAL_P_I
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     slli t1, t1, imm, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };
@@ -81,7 +81,7 @@ def macroop SAL_1_R
 
 def macroop SAL_1_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     slli t1, t1, 1, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -89,7 +89,7 @@ def macroop SAL_1_M
 def macroop SAL_1_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     slli t1, t1, 1, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };
@@ -101,7 +101,7 @@ def macroop SAL_R_R
 
 def macroop SAL_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     sll t1, t1, reg, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -109,7 +109,7 @@ def macroop SAL_M_R
 def macroop SAL_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     sll t1, t1, reg, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };
@@ -121,7 +121,7 @@ def macroop SHR_R_I
 
 def macroop SHR_M_I
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     srli t1, t1, imm, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -129,7 +129,7 @@ def macroop SHR_M_I
 def macroop SHR_P_I
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     srli t1, t1, imm, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };
@@ -141,7 +141,7 @@ def macroop SHR_1_R
 
 def macroop SHR_1_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     srli t1, t1, 1, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -149,7 +149,7 @@ def macroop SHR_1_M
 def macroop SHR_1_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     srli t1, t1, 1, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };
@@ -161,7 +161,7 @@ def macroop SHR_R_R
 
 def macroop SHR_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     srl t1, t1, reg, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -169,7 +169,7 @@ def macroop SHR_M_R
 def macroop SHR_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     srl t1, t1, reg, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };
@@ -181,7 +181,7 @@ def macroop SAR_R_I
 
 def macroop SAR_M_I
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     srai t1, t1, imm, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -189,7 +189,7 @@ def macroop SAR_M_I
 def macroop SAR_P_I
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     srai t1, t1, imm, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };
@@ -201,7 +201,7 @@ def macroop SAR_1_R
 
 def macroop SAR_1_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     srai t1, t1, 1, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -209,7 +209,7 @@ def macroop SAR_1_M
 def macroop SAR_1_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     srai t1, t1, 1, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };
@@ -221,7 +221,7 @@ def macroop SAR_R_R
 
 def macroop SAR_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     sra t1, t1, reg, flags=(SF,ZF,PF)
     st t1, seg, sib, disp
 };
@@ -229,7 +229,7 @@ def macroop SAR_M_R
 def macroop SAR_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     sra t1, t1, reg, flags=(SF,ZF,PF)
     st t1, seg, riprel, disp
 };

diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py b/src/arch/x86/isa/insts/general_purpose/semaphores.py
index 800f1b325365a39d32392ef12ad0fd63eeb551fa..27a31dbd94ac9a37a3b049a6d88ed89848f62d76 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/semaphores.py
+++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py
@@ -61,7 +61,7 @@ def macroop CMPXCHG_R_R {
 };
 
 def macroop CMPXCHG_M_R {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
 
     mov t1, t1, reg, flags=(CZF,)
@@ -71,7 +71,7 @@ def macroop CMPXCHG_M_R {
 
 def macroop CMPXCHG_P_R {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
 
     mov t1, t1, reg, flags=(CZF,)

diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
index de89005f2408c9a1d893003047e2ffcef7db966b..ee85a038affb34b12ac38d5375d3564fb44269e1 100644 (file)
--- a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
@@ -55,28 +55,33 @@
 
 microcode = '''
 def macroop MOVAPS_R_M {
+    # Check low address.
     ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
     ldfp xmml, seg, sib, disp, dataSize=8
 };
 
 def macroop MOVAPS_R_P {
     rdip t7
+    # Check low address.
     ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
     ldfp xmml, seg, riprel, disp, dataSize=8
 };
 
 def macroop MOVAPS_M_R {
+    # Check low address.
     stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
     stfp xmml, seg, sib, disp, dataSize=8
 };
 
 def macroop MOVAPS_P_R {
     rdip t7
+    # Check low address.
     stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
     stfp xmml, seg, riprel, disp, dataSize=8
 };
 
 def macroop MOVAPS_R_R {
+    # Check low address.
     movfp xmml, xmml, xmmlm, dataSize=8
     movfp xmmh, xmmh, xmmhm, dataSize=8
 };