SoCCore: use hex for integrated_rom/sram_size

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 59faef811bd0c66af8545a53c043e196e36d9ed5..ffe0546fbed1ed21557d759a77cebd036cfd8924 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -85,9 +85,9 @@ class SoCCore(Module):
                 # CPU parameters
                 cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
                 # ROM parameters
-                integrated_rom_size=32768, integrated_rom_init=[],
+                integrated_rom_size=0x8000, integrated_rom_init=[],
                 # SRAM parameters
-                integrated_sram_size=4096, integrated_sram_init=[],
+                integrated_sram_size=0x1000, integrated_sram_init=[],
                 # MAIN_RAM parameters
                 integrated_main_ram_size=0, integrated_main_ram_init=[],
                 # CSR parameters