radv: Set FLUSH_ON_BINNING_TRANSITION.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 72593f19ba5b3c49964e10f5ba1aba19bf28007c..3f4940e9c668682d9de0ca7152959d575a50bb4c 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -884,6 +884,47 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
        cmd_buffer->state.context_roll_without_scissor_emitted = true;
 }
 
+static void
+radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
+                         struct radv_pipeline *pipeline)
+{
+       const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
+
+
+       if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
+               return;
+
+       if (old_pipeline &&
+           old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
+           old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
+               return;
+
+       bool binning_flush = false;
+       if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
+           cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
+           cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
+           cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+               binning_flush = !old_pipeline ||
+                       G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
+                       G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
+       }
+
+       radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
+                              pipeline->graphics.binning.pa_sc_binner_cntl_0 |
+                              S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
+
+       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+               radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
+                                      pipeline->graphics.binning.db_dfsm_control);
+       } else {
+               radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
+                                      pipeline->graphics.binning.db_dfsm_control);
+       }
+
+       cmd_buffer->state.context_roll_without_scissor_emitted = true;
+}
+
+
 static void
 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
                          struct radv_shader_variant *shader)
@@ -1097,6 +1138,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
                return;
 
        radv_update_multisample_state(cmd_buffer, pipeline);
+       radv_update_binning_state(cmd_buffer, pipeline);
 
        cmd_buffer->scratch_size_needed =
                                  MAX2(cmd_buffer->scratch_size_needed,

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a7ff0e2d1397fd01c95291a6a15fcec88570320f..58eb6d9b07e1f45d3f5ba6b2714ede639003fc79 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3026,16 +3026,8 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
                        S_028C44_OPTIMAL_BIN_SELECTION(1);
        }
 
-       radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0,
-                              pa_sc_binner_cntl_0);
-
-       if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
-               radeon_set_context_reg(ctx_cs, R_028038_DB_DFSM_CONTROL,
-                                      db_dfsm_control);
-       } else {
-               radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
-                                      db_dfsm_control);
-       }
+       pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
+       pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
 }
 
 

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index f1f30887e0164314b8bdd572d18087da1e3244a0..466f0288399fa95ef3a6be899ad168280c21abcc 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1452,6 +1452,11 @@ struct radv_ia_multi_vgt_param_helpers {
        bool partial_vs_wave;
 };
 
+struct radv_binning_state {
+       uint32_t pa_sc_binner_cntl_0;
+       uint32_t db_dfsm_control;
+};
+
 #define SI_GS_PER_ES 128
 
 struct radv_pipeline {
@@ -1478,6 +1483,7 @@ struct radv_pipeline {
        union {
                struct {
                        struct radv_multisample_state ms;
+                       struct radv_binning_state binning;
                        uint32_t spi_baryc_cntl;
                        bool prim_restart_enable;
                        unsigned esgs_ring_size;