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mem: Avoid using invalid iterator in cache lock list traversal
author
Andreas Hansson
<andreas.hansson@arm.com>
Mon, 15 Feb 2016 08:40:04 +0000
(
03:40
-0500)
committer
Andreas Hansson
<andreas.hansson@arm.com>
Mon, 15 Feb 2016 08:40:04 +0000
(
03:40
-0500)
Fix up issue highlighted by Valgrind and the clang Address Sanitizer.
src/mem/cache/blk.hh
patch
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diff --git
a/src/mem/cache/blk.hh
b/src/mem/cache/blk.hh
index 6682dd4bb19c00ca237ef24ac428cdd894b2315c..39d45d6e134d05c1d9cc90326359193b5eae5669 100644
(file)
--- a/
src/mem/cache/blk.hh
+++ b/
src/mem/cache/blk.hh
@@
-347,15
+347,16
@@
class CacheBlk
bool success = false;
auto l = lockList.begin();
- while (
l != lockList.end() && !success
) {
+ while (
!success && l != lockList.end()
) {
if (l->matches(pkt->req)) {
// it's a store conditional, and as far as the
// memory system can tell, the requesting
// context's lock is still valid.
success = true;
lockList.erase(l);
+ } else {
+ ++l;
}
- ++l;
}
req->setExtraData(success ? 1 : 0);