ARM: Add in spots for the VFP control registers.

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 6e6eea5a89583672e0052404973a80e6ca40493e..ac7427dad0321ab81368b0232c9b37555f7ebd99 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -82,7 +82,10 @@ def operands {{
 
     'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
     'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
-    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
-    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
+    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42),
+    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43),
+    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44),
+    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45),
+    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46)
 
 }};

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 42065b0fdb839967807e1106271fd216094f13ae..3180669de334da800ca89ff497c46e541b9059e2 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -62,6 +62,9 @@ namespace ArmISA
         MISCREG_SPSR_UND,
         MISCREG_SPSR_ABT,
         MISCREG_FPSR,
+        MISCREG_FPSID,
+        MISCREG_FPSCR,
+        MISCREG_FPEXC,
        NUM_MISCREGS
     };