mips: Remove unused or misplaced values from isa_traits.hh.

Most of these values were unused, except the interrupt levels which were
moved to the interrupt controller, the only place they were used.
Unnecessary includes were also removed.

Change-Id: I783966413d51391663a9217ed672ec1f2b4719b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33197
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index ad2692f7221e907d36c97d6d00bda0015c9196d9..1cecfafb4193ef6bca5ec1da8d9c385dee73483c 100644 (file)
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -29,7 +29,6 @@
 
 #include "arch/mips/interrupts.hh"
 
-#include "arch/mips/isa_traits.hh"
 #include "arch/mips/pra_constants.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
@@ -38,6 +37,26 @@
 namespace MipsISA
 {
 
+enum InterruptLevels
+{
+    INTLEVEL_SOFTWARE_MIN = 4,
+    INTLEVEL_SOFTWARE_MAX = 19,
+
+    INTLEVEL_EXTERNAL_MIN = 20,
+    INTLEVEL_EXTERNAL_MAX = 34,
+
+    INTLEVEL_IRQ0 = 20,
+    INTLEVEL_IRQ1 = 21,
+    INTINDEX_ETHERNET = 0,
+    INTINDEX_SCSI = 1,
+    INTLEVEL_IRQ2 = 22,
+    INTLEVEL_IRQ3 = 23,
+
+    INTLEVEL_SERIAL = 33,
+
+    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
+};
+
 static inline uint8_t
 getCauseIP(ThreadContext *tc)
 {

diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index b97828fef68fd1c8c5e8bf1bfe1aa3a71c1a5a68..5aa167eb4baa88311b1ae5d3c9f5714bd0d3c7e4 100644 (file)
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -30,111 +30,15 @@
 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
 #define __ARCH_MIPS_ISA_TRAITS_HH__
 
-#include "arch/mips/types.hh"
 #include "base/types.hh"
-#include "cpu/static_inst_fwd.hh"
 
 namespace MipsISA
 {
 
 const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 
-StaticInstPtr decodeInst(ExtMachInst);
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;
-const Addr Page_Mask = ~(PageBytes - 1);
-const Addr PageOffset = PageBytes - 1;
-
-
-////////////////////////////////////////////////////////////////////////
-//
-//  Translation stuff
-//
-
-const Addr PteShift = 3;
-const Addr NPtePageShift = PageShift - PteShift;
-const Addr NPtePage = ULL(1) << NPtePageShift;
-const Addr PteMask = NPtePage - 1;
-
-//// All 'Mapped' segments go through the TLB
-//// All other segments are translated by dropping the MSB, to give
-//// the corresponding physical address
-// User Segment - Mapped
-const Addr USegBase = ULL(0x0);
-const Addr USegEnd = ULL(0x7FFFFFFF);
-
-// Kernel Segment 0 - Unmapped
-const Addr KSeg0End = ULL(0x9FFFFFFF);
-const Addr KSeg0Base =  ULL(0x80000000);
-const Addr KSeg0Mask = ULL(0x1FFFFFFF);
-
-// Kernel Segment 1 - Unmapped, Uncached
-const Addr KSeg1End = ULL(0xBFFFFFFF);
-const Addr KSeg1Base = ULL(0xA0000000);
-const Addr KSeg1Mask = ULL(0x1FFFFFFF);
-
-// Kernel/Supervisor Segment - Mapped
-const Addr KSSegEnd = ULL(0xDFFFFFFF);
-const Addr KSSegBase = ULL(0xC0000000);
-
-// Kernel Segment 3 - Mapped
-const Addr KSeg3End = ULL(0xFFFFFFFF);
-const Addr KSeg3Base = ULL(0xE0000000);
-
-
-inline Addr Phys2K0Seg(Addr addr)
-{
-    return addr | KSeg0Base;
-}
-
-
-const unsigned VABits = 32;
-const unsigned PABits = 32; // Is this correct?
-const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
-const Addr VAddrUnImplMask = ~VAddrImplMask;
-inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
-inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
-inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
-
-const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
-
-////////////////////////////////////////////////////////////////////////
-//
-//  Interrupt levels
-//
-enum InterruptLevels
-{
-    INTLEVEL_SOFTWARE_MIN = 4,
-    INTLEVEL_SOFTWARE_MAX = 19,
-
-    INTLEVEL_EXTERNAL_MIN = 20,
-    INTLEVEL_EXTERNAL_MAX = 34,
-
-    INTLEVEL_IRQ0 = 20,
-    INTLEVEL_IRQ1 = 21,
-    INTINDEX_ETHERNET = 0,
-    INTINDEX_SCSI = 1,
-    INTLEVEL_IRQ2 = 22,
-    INTLEVEL_IRQ3 = 23,
-
-    INTLEVEL_SERIAL = 33,
-
-    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
-};
-
-// MIPS modes
-enum mode_type
-{
-    mode_kernel = 0,        // kernel
-    mode_supervisor = 1,    // supervisor
-    mode_user = 2,          // user mode
-    mode_debug = 3,         // debug mode
-    mode_number             // number of modes
-};
-
-const int ANNOTE_NONE = 0;
-const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 
 } // namespace MipsISA