Add "verific -work" help message
authorClifford Wolf <clifford@clifford.at>
Wed, 22 Aug 2018 15:22:24 +0000 (17:22 +0200)
committerClifford Wolf <clifford@clifford.at>
Wed, 22 Aug 2018 15:22:24 +0000 (17:22 +0200)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
frontends/verific/verific.cc

index cb31634ddbe1312a4d2126b2c08f23f932e73c74..1dd6d7e24783646265ef28c2828ed648777a3be2 100644 (file)
@@ -1706,11 +1706,18 @@ struct VerificPass : public Pass {
                log("\n");
                log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
                log("\n");
+               log("\n");
                log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
                log("\n");
                log("Load the specified VHDL files into Verific.\n");
                log("\n");
                log("\n");
+               log("    verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
+               log("\n");
+               log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
+               log("(default library when -work is not present: \"work\")\n");
+               log("\n");
+               log("\n");
                log("    verific -vlog-incdir <directory>..\n");
                log("\n");
                log("Add Verilog include directories.\n");