[ARM] Simplify logical DImode iterators

Further simplify the logical DImode expander using code iterator and
obtab attributes.  This avoids adding unnecessary code_attr entries.

    gcc/
	* config/arm/arm.md (<logical_op>di3): Use <optab> and <CODE>.
	* config/arm/iterators.md (optab): Add and, ior, xor entries.
	(logical_op): Remove code attribute.
	(logical_OP): Likewise.

From-SVN: r275970

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ac055ef27a53881c9894cad01476e60bccd29e28..3be2b55523b648d9033541ff20e79e035e31f0d7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-09-19  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       * config/arm/arm.md (<logical_op>di3): Use <optab> and <CODE>.
+       * config/arm/iterators.md (optab): Add and, ior, xor entries.
+       (logical_op): Remove code attribute.
+       (logical_OP): Likewise.
+
 2019-09-19  Martin Liska  <mliska@suse.cz>
 
        * ipa-icf.c (sort_congruence_class_groups_by_decl_uid):

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index d54082b13dd702aa55a1465c0fbfa87baa89149a..d607f88cb05ffa9cd8a47b8c8e0c53ea3a5ca411 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2039,16 +2039,16 @@
 ; operands or complex immediates, which leads to fewer LDRD/STRD instructions.
 ; So an explicit expander is needed to generate better code.
 
-(define_expand "<logical_op>di3"
+(define_expand "<LOGICAL:optab>di3"
   [(set (match_operand:DI        0 "s_register_operand")
        (LOGICAL:DI (match_operand:DI 1 "s_register_operand")
-                   (match_operand:DI 2 "arm_<logical_op>di_operand")))]
+                   (match_operand:DI 2 "arm_<optab>di_operand")))]
   "TARGET_32BIT"
   {
-      rtx low  = simplify_gen_binary (<logical_OP>, SImode,
+      rtx low  = simplify_gen_binary (<CODE>, SImode,
                                      gen_lowpart (SImode, operands[1]),
                                      gen_lowpart (SImode, operands[2]));
-      rtx high = simplify_gen_binary (<logical_OP>, SImode,
+      rtx high = simplify_gen_binary (<CODE>, SImode,
                                      gen_highpart (SImode, operands[1]),
                                      gen_highpart_mode (SImode, DImode,
                                                         operands[2]));

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 5e3299e850813db2f3c0a25a6cde779d1d0d1d55..2d8ef3f5fbd5ca1a34c5dc66ddcd8780b138d5e0 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -287,9 +287,6 @@
 
 (define_code_attr vfml_op [(plus "a") (minus "s")])
 
-(define_code_attr logical_op [(ior "ior") (xor "xor") (and "and")])
-(define_code_attr logical_OP [(ior "IOR") (xor "XOR") (and "AND")])
-
 ;;----------------------------------------------------------------------------
 ;; Int iterators
 ;;----------------------------------------------------------------------------
@@ -797,7 +794,14 @@
                 (umax "u")])
 
 (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
-(define_code_attr optab [(ltu "ltu") (geu "geu")])
+
+;; Map rtl operator codes to optab names
+(define_code_attr optab
+ [(ltu "ltu")
+  (geu "geu")
+  (and "and")
+  (ior "ior")
+  (xor "xor")])
 
 ;; Assembler mnemonics for signedness of widening operations.
 (define_code_attr US [(sign_extend "s") (zero_extend "u")])