i965: Fix the maximum grf counting in the new FS backend.

glsl-algebraic-rcp-rsq managed to use 33 registers, and we claimed to
only use 32, so the write to g32 would go stomping over the precious
g0 of some other thread.

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index f8b06226d791723d7fd3ed0a25dd7837de89ac43..673a31c1dd6db32de2623e71919f2fbddc027d84 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1357,7 +1357,7 @@ fs_visitor::assign_regs()
       last_grf = MAX2(last_grf, inst->src[1].hw_reg);
    }
 
-   this->grf_used = last_grf;
+   this->grf_used = last_grf + 1;
 }
 
 static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)