* Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo.
(ALL_MACHINES_CFILES): Add cpu-tic6x.c.
(BFD32_BACKENDS): Add elf32-tic6x.lo.
(BFD32_BACKENDS_CFILES): Add elf32-tic6x.c.
* Makefile.in: Regenerate.
* archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New.
(bfd_archures_list): Update.
* config.bfd (tic6x-*-elf): New.
* configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec):
New.
* configure: Regenerate.
* cpu-tic6x.c, elf32-tic6x.c: New.
* reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12,
BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7,
BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16,
BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B,
BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W,
BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B,
BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W,
BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H,
BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W,
BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W,
BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31,
BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN,
BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New.
* targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New.
(_bfd_target_vector): Update.
* bfd-in2.h, libbfd.h: Regenerate.
binutils:
* MAINTAINERS: Add self as TI C6X maintainer.
* NEWS: Add news entry for TI C6X support.
* readelf.c: Include elf/tic6x.h.
(guess_is_rela): Handle EM_TI_C6000.
(dump_relocations): Likewise.
(get_tic6x_dynamic_type): New.
(get_dynamic_type): Call it.
(get_machine_flags): Handle EF_C6000_REL.
(get_osabi_name): Handle machine-specific values only for relevant
machines. Handle C6X values.
(get_tic6x_segment_type): New.
(get_segment_type): Call it.
(get_tic6x_section_type_name): New.
(get_section_type_name): Call it.
(is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle
EM_TI_C6000.
gas:
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
(TARGET_CPU_HFILES): Add config/tc-tic6x.h.
* Makefile.in: Regenerate.
* NEWS: Add news entry for TI C6X support.
* app.c (do_scrub_chars): Handle "||^" for TI C6X. Handle
TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR. Keep spaces in
operands if TC_KEEP_OPERAND_SPACES.
* configure.tgt (tic6x-*-*): New.
* config/tc-ia64.h (TC_PREDICATE_START_CHAR,
TC_PREDICATE_END_CHAR): Define.
* config/tc-tic6x.c, config/tc-tic6x.h: New.
* doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi (TIC6X): Define.
* doc/as.texinfo: Add TI C6X documentation. Include c-tic6x.texi.
* doc/c-tic6x.texi: New.
gas/testsuite:
* gas/tic6x: New directory and testcases.
include:
* dis-asm.h (print_insn_tic6x): Declare.
include/elf:
* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
* tic6x.h: New.
include/opcode:
* tic6x-control-registers.h, tic6x-insn-formats.h,
tic6x-opcode-table.h, tic6x.h: New.
ld:
* Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and
eelf32_tic6x_le.o.
(eelf32_tic6x_be.c, eelf32_tic6x_le.c): New.
* NEWS: Add news entry for TI C6X support.
* configure.tgt (tic6x-*-*): New.
* emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New.
ld/testsuite:
* ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x-*-*.
* ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x-*-*.
* ld-tic6x: New directory and testcases.
opcodes:
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
* Makefile.in: Regenerate.
* configure.in (bfd_tic6x_arch): New.
* configure: Regenerate.
* disassemble.c (ARCH_tic6x): Define if ARCH_all.
(disassembler): Handle TI C6X.
* tic6x-dis.c: New.
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo.
+ (ALL_MACHINES_CFILES): Add cpu-tic6x.c.
+ (BFD32_BACKENDS): Add elf32-tic6x.lo.
+ (BFD32_BACKENDS_CFILES): Add elf32-tic6x.c.
+ * Makefile.in: Regenerate.
+ * archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New.
+ (bfd_archures_list): Update.
+ * config.bfd (tic6x-*-elf): New.
+ * configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec):
+ New.
+ * configure: Regenerate.
+ * cpu-tic6x.c, elf32-tic6x.c: New.
+ * reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12,
+ BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7,
+ BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16,
+ BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B,
+ BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W,
+ BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B,
+ BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W,
+ BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H,
+ BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W,
+ BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W,
+ BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31,
+ BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN,
+ BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New.
+ * targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New.
+ (_bfd_target_vector): Update.
+ * bfd-in2.h, libbfd.h: Regenerate.
+
2010-03-24 H.J. Lu <hongjiu.lu@intel.com>
* aout-target.h: Update copyright year.
cpu-tic30.lo \
cpu-tic4x.lo \
cpu-tic54x.lo \
+ cpu-tic6x.lo \
cpu-tic80.lo \
cpu-v850.lo \
cpu-vax.lo \
cpu-tic30.c \
cpu-tic4x.c \
cpu-tic54x.c \
+ cpu-tic6x.c \
cpu-tic80.c \
cpu-v850.c \
cpu-vax.c \
elf32-sh64.lo \
elf32-sparc.lo \
elf32-spu.lo \
+ elf32-tic6x.lo \
elf32-v850.lo \
elf32-vax.lo \
elf32-xc16x.lo \
elf32-sh64.c \
elf32-sparc.c \
elf32-spu.c \
+ elf32-tic6x.c \
elf32-v850.c \
elf32-vax.c \
elf32-xc16x.c \
cpu-tic30.lo \
cpu-tic4x.lo \
cpu-tic54x.lo \
+ cpu-tic6x.lo \
cpu-tic80.lo \
cpu-v850.lo \
cpu-vax.lo \
cpu-tic30.c \
cpu-tic4x.c \
cpu-tic54x.c \
+ cpu-tic6x.c \
cpu-tic80.c \
cpu-v850.c \
cpu-vax.c \
elf32-sh64.lo \
elf32-sparc.lo \
elf32-spu.lo \
+ elf32-tic6x.lo \
elf32-v850.lo \
elf32-vax.lo \
elf32-xc16x.lo \
elf32-sh64.c \
elf32-sparc.c \
elf32-spu.c \
+ elf32-tic6x.c \
elf32-v850.c \
elf32-vax.c \
elf32-xc16x.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic30.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic4x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic54x.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic6x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic80.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-v850.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-vax.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-sh64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-sparc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-spu.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-tic6x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-v850.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-vax.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xc16x.Plo@am__quote@
.#define bfd_mach_tic3x 30
.#define bfd_mach_tic4x 40
. bfd_arch_tic54x, {* Texas Instruments TMS320C54X *}
+. bfd_arch_tic6x, {* Texas Instruments TMS320C6X *}
. bfd_arch_tic80, {* TI TMS320c80 (MVP) *}
. bfd_arch_v850, {* NEC V850 *}
.#define bfd_mach_v850 1
extern const bfd_arch_info_type bfd_tic30_arch;
extern const bfd_arch_info_type bfd_tic4x_arch;
extern const bfd_arch_info_type bfd_tic54x_arch;
+extern const bfd_arch_info_type bfd_tic6x_arch;
extern const bfd_arch_info_type bfd_tic80_arch;
extern const bfd_arch_info_type bfd_v850_arch;
extern const bfd_arch_info_type bfd_vax_arch;
&bfd_tic30_arch,
&bfd_tic4x_arch,
&bfd_tic54x_arch,
+ &bfd_tic6x_arch,
&bfd_tic80_arch,
&bfd_v850_arch,
&bfd_vax_arch,
#define bfd_mach_tic3x 30
#define bfd_mach_tic4x 40
bfd_arch_tic54x, /* Texas Instruments TMS320C54X */
+ bfd_arch_tic6x, /* Texas Instruments TMS320C6X */
bfd_arch_tic80, /* TI TMS320c80 (MVP) */
bfd_arch_v850, /* NEC V850 */
#define bfd_mach_v850 1
the opcode. */
BFD_RELOC_TIC54X_MS7_OF_23,
+/* TMS320C6000 relocations. */
+ BFD_RELOC_C6000_PCR_S21,
+ BFD_RELOC_C6000_PCR_S12,
+ BFD_RELOC_C6000_PCR_S10,
+ BFD_RELOC_C6000_PCR_S7,
+ BFD_RELOC_C6000_ABS_S16,
+ BFD_RELOC_C6000_ABS_L16,
+ BFD_RELOC_C6000_ABS_H16,
+ BFD_RELOC_C6000_SBR_U15_B,
+ BFD_RELOC_C6000_SBR_U15_H,
+ BFD_RELOC_C6000_SBR_U15_W,
+ BFD_RELOC_C6000_SBR_S16,
+ BFD_RELOC_C6000_SBR_L16_B,
+ BFD_RELOC_C6000_SBR_L16_H,
+ BFD_RELOC_C6000_SBR_L16_W,
+ BFD_RELOC_C6000_SBR_H16_B,
+ BFD_RELOC_C6000_SBR_H16_H,
+ BFD_RELOC_C6000_SBR_H16_W,
+ BFD_RELOC_C6000_SBR_GOT_U15_W,
+ BFD_RELOC_C6000_SBR_GOT_L16_W,
+ BFD_RELOC_C6000_SBR_GOT_H16_W,
+ BFD_RELOC_C6000_DSBT_INDEX,
+ BFD_RELOC_C6000_PREL31,
+ BFD_RELOC_C6000_COPY,
+ BFD_RELOC_C6000_ALIGN,
+ BFD_RELOC_C6000_FPHEAD,
+ BFD_RELOC_C6000_NOCMP,
+
/* This is a 48 bit reloc for the FR30 that stores 32 bits. */
BFD_RELOC_FR30_48,
;;
#endif
+ tic6x-*-elf)
+ targ_defvec=bfd_elf32_tic6x_le_vec
+ targ_selvecs=bfd_elf32_tic6x_be_vec
+ ;;
+
tic80*-*-*)
targ_defvec=tic80coff_vec
targ_underscore=yes
bfd_elf32_sparc_vec) tb="$tb elf32-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_sparc_vxworks_vec) tb="$tb elf32-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_spu_vec) tb="$tb elf32-spu.lo elf32.lo $elf" ;;
+ bfd_elf32_tic6x_be_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
+ bfd_elf32_tic6x_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_us_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;;
bfd_elf32_sparc_vec) tb="$tb elf32-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_sparc_vxworks_vec) tb="$tb elf32-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_spu_vec) tb="$tb elf32-spu.lo elf32.lo $elf" ;;
+ bfd_elf32_tic6x_be_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
+ bfd_elf32_tic6x_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_us_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;;
--- /dev/null
+/* BFD support for the TI C6X processor.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_tic6x_arch =
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_tic6x, /* Architecture. */
+ 0, /* No BFD machine numbers needed. */
+ "tic6x", /* Architecture name. */
+ "tic6x", /* Printable name. */
+ 2, /* Section alignment power. */
+ TRUE, /* Default machine for this architecture. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ 0,
+ };
--- /dev/null
+/* 32-bit ELF support for TI C6X
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "libiberty.h"
+#include "elf-bfd.h"
+#include "elf/tic6x.h"
+
+static reloc_howto_type elf32_tic6x_howto_table[] =
+{
+ HOWTO (R_C6000_NONE, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_NONE", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_ABS32, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_ABS32", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_ABS16, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_ABS16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_ABS8, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 8, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_ABS8", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x000000ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_PCR_S21, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 21, /* bitsize */
+ TRUE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_signed,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_PCR_S21", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0fffff80, /* dst_mask */
+ TRUE), /* pcrel_offset */
+ HOWTO (R_C6000_PCR_S12, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ TRUE, /* pc_relative */
+ 16, /* bitpos */
+ complain_overflow_signed,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_PCR_S12", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0fff0000, /* dst_mask */
+ TRUE), /* pcrel_offset */
+ HOWTO (R_C6000_PCR_S10, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 10, /* bitsize */
+ TRUE, /* pc_relative */
+ 13, /* bitpos */
+ complain_overflow_signed,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_PCR_S10", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fe000, /* dst_mask */
+ TRUE), /* pcrel_offset */
+ HOWTO (R_C6000_PCR_S7, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 7, /* bitsize */
+ TRUE, /* pc_relative */
+ 16, /* bitpos */
+ complain_overflow_signed,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_PCR_S7", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007f0000, /* dst_mask */
+ TRUE), /* pcrel_offset */
+ HOWTO (R_C6000_ABS_S16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_signed,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_ABS_S16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_ABS_L16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_ABS_L16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_ABS_H16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_ABS_H16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_U15_B, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 15, /* bitsize */
+ FALSE, /* pc_relative */
+ 8, /* bitpos */
+ complain_overflow_unsigned,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_U15_B", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_U15_H, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 15, /* bitsize */
+ FALSE, /* pc_relative */
+ 8, /* bitpos */
+ complain_overflow_unsigned,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_U15_H", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_U15_W, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 15, /* bitsize */
+ FALSE, /* pc_relative */
+ 8, /* bitpos */
+ complain_overflow_unsigned,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_U15_W", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_S16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_signed,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_S16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_L16_B, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_L16_B", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_L16_H, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_L16_H", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_L16_W, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_L16_W", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_H16_B, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_H16_B", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_H16_H, /* type */
+ 17, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_H16_H", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_H16_W, /* type */
+ 18, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_H16_W", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_GOT_U15_W, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 15, /* bitsize */
+ FALSE, /* pc_relative */
+ 8, /* bitpos */
+ complain_overflow_unsigned,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_GOT_U15_W",/* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_GOT_L16_W, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_GOT_L16_W",/* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_SBR_GOT_H16_W, /* type */
+ 18, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_SBR_GOT_H16_W",/* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_DSBT_INDEX, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 15, /* bitsize */
+ FALSE, /* pc_relative */
+ 8, /* bitpos */
+ complain_overflow_unsigned,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_DSBT_INDEX", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x007fff00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_PREL31, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 31, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_PREL31", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x7fffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_COPY, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_COPY", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ EMPTY_HOWTO (27),
+ EMPTY_HOWTO (28),
+ EMPTY_HOWTO (29),
+ EMPTY_HOWTO (30),
+ EMPTY_HOWTO (31),
+ EMPTY_HOWTO (32),
+ EMPTY_HOWTO (33),
+ EMPTY_HOWTO (34),
+ EMPTY_HOWTO (35),
+ EMPTY_HOWTO (36),
+ EMPTY_HOWTO (37),
+ EMPTY_HOWTO (38),
+ EMPTY_HOWTO (39),
+ EMPTY_HOWTO (40),
+ EMPTY_HOWTO (41),
+ EMPTY_HOWTO (42),
+ EMPTY_HOWTO (43),
+ EMPTY_HOWTO (44),
+ EMPTY_HOWTO (45),
+ EMPTY_HOWTO (46),
+ EMPTY_HOWTO (47),
+ EMPTY_HOWTO (48),
+ EMPTY_HOWTO (49),
+ EMPTY_HOWTO (50),
+ EMPTY_HOWTO (51),
+ EMPTY_HOWTO (52),
+ EMPTY_HOWTO (53),
+ EMPTY_HOWTO (54),
+ EMPTY_HOWTO (55),
+ EMPTY_HOWTO (56),
+ EMPTY_HOWTO (57),
+ EMPTY_HOWTO (58),
+ EMPTY_HOWTO (59),
+ EMPTY_HOWTO (60),
+ EMPTY_HOWTO (61),
+ EMPTY_HOWTO (62),
+ EMPTY_HOWTO (63),
+ EMPTY_HOWTO (64),
+ EMPTY_HOWTO (65),
+ EMPTY_HOWTO (66),
+ EMPTY_HOWTO (67),
+ EMPTY_HOWTO (68),
+ EMPTY_HOWTO (69),
+ EMPTY_HOWTO (70),
+ EMPTY_HOWTO (71),
+ EMPTY_HOWTO (72),
+ EMPTY_HOWTO (73),
+ EMPTY_HOWTO (74),
+ EMPTY_HOWTO (75),
+ EMPTY_HOWTO (76),
+ EMPTY_HOWTO (77),
+ EMPTY_HOWTO (78),
+ EMPTY_HOWTO (79),
+ EMPTY_HOWTO (80),
+ EMPTY_HOWTO (81),
+ EMPTY_HOWTO (82),
+ EMPTY_HOWTO (83),
+ EMPTY_HOWTO (84),
+ EMPTY_HOWTO (85),
+ EMPTY_HOWTO (86),
+ EMPTY_HOWTO (87),
+ EMPTY_HOWTO (88),
+ EMPTY_HOWTO (89),
+ EMPTY_HOWTO (90),
+ EMPTY_HOWTO (91),
+ EMPTY_HOWTO (92),
+ EMPTY_HOWTO (93),
+ EMPTY_HOWTO (94),
+ EMPTY_HOWTO (95),
+ EMPTY_HOWTO (96),
+ EMPTY_HOWTO (97),
+ EMPTY_HOWTO (98),
+ EMPTY_HOWTO (99),
+ EMPTY_HOWTO (100),
+ EMPTY_HOWTO (101),
+ EMPTY_HOWTO (102),
+ EMPTY_HOWTO (103),
+ EMPTY_HOWTO (104),
+ EMPTY_HOWTO (105),
+ EMPTY_HOWTO (106),
+ EMPTY_HOWTO (107),
+ EMPTY_HOWTO (108),
+ EMPTY_HOWTO (109),
+ EMPTY_HOWTO (110),
+ EMPTY_HOWTO (111),
+ EMPTY_HOWTO (112),
+ EMPTY_HOWTO (113),
+ EMPTY_HOWTO (114),
+ EMPTY_HOWTO (115),
+ EMPTY_HOWTO (116),
+ EMPTY_HOWTO (117),
+ EMPTY_HOWTO (118),
+ EMPTY_HOWTO (119),
+ EMPTY_HOWTO (120),
+ EMPTY_HOWTO (121),
+ EMPTY_HOWTO (122),
+ EMPTY_HOWTO (123),
+ EMPTY_HOWTO (124),
+ EMPTY_HOWTO (125),
+ EMPTY_HOWTO (126),
+ EMPTY_HOWTO (127),
+ EMPTY_HOWTO (128),
+ EMPTY_HOWTO (129),
+ EMPTY_HOWTO (130),
+ EMPTY_HOWTO (131),
+ EMPTY_HOWTO (132),
+ EMPTY_HOWTO (133),
+ EMPTY_HOWTO (134),
+ EMPTY_HOWTO (135),
+ EMPTY_HOWTO (136),
+ EMPTY_HOWTO (137),
+ EMPTY_HOWTO (138),
+ EMPTY_HOWTO (139),
+ EMPTY_HOWTO (140),
+ EMPTY_HOWTO (141),
+ EMPTY_HOWTO (142),
+ EMPTY_HOWTO (143),
+ EMPTY_HOWTO (144),
+ EMPTY_HOWTO (145),
+ EMPTY_HOWTO (146),
+ EMPTY_HOWTO (147),
+ EMPTY_HOWTO (148),
+ EMPTY_HOWTO (149),
+ EMPTY_HOWTO (150),
+ EMPTY_HOWTO (151),
+ EMPTY_HOWTO (152),
+ EMPTY_HOWTO (153),
+ EMPTY_HOWTO (154),
+ EMPTY_HOWTO (155),
+ EMPTY_HOWTO (156),
+ EMPTY_HOWTO (157),
+ EMPTY_HOWTO (158),
+ EMPTY_HOWTO (159),
+ EMPTY_HOWTO (160),
+ EMPTY_HOWTO (161),
+ EMPTY_HOWTO (162),
+ EMPTY_HOWTO (163),
+ EMPTY_HOWTO (164),
+ EMPTY_HOWTO (165),
+ EMPTY_HOWTO (166),
+ EMPTY_HOWTO (167),
+ EMPTY_HOWTO (168),
+ EMPTY_HOWTO (169),
+ EMPTY_HOWTO (170),
+ EMPTY_HOWTO (171),
+ EMPTY_HOWTO (172),
+ EMPTY_HOWTO (173),
+ EMPTY_HOWTO (174),
+ EMPTY_HOWTO (175),
+ EMPTY_HOWTO (176),
+ EMPTY_HOWTO (177),
+ EMPTY_HOWTO (178),
+ EMPTY_HOWTO (179),
+ EMPTY_HOWTO (180),
+ EMPTY_HOWTO (181),
+ EMPTY_HOWTO (182),
+ EMPTY_HOWTO (183),
+ EMPTY_HOWTO (184),
+ EMPTY_HOWTO (185),
+ EMPTY_HOWTO (186),
+ EMPTY_HOWTO (187),
+ EMPTY_HOWTO (188),
+ EMPTY_HOWTO (189),
+ EMPTY_HOWTO (190),
+ EMPTY_HOWTO (191),
+ EMPTY_HOWTO (192),
+ EMPTY_HOWTO (193),
+ EMPTY_HOWTO (194),
+ EMPTY_HOWTO (195),
+ EMPTY_HOWTO (196),
+ EMPTY_HOWTO (197),
+ EMPTY_HOWTO (198),
+ EMPTY_HOWTO (199),
+ EMPTY_HOWTO (200),
+ EMPTY_HOWTO (201),
+ EMPTY_HOWTO (202),
+ EMPTY_HOWTO (203),
+ EMPTY_HOWTO (204),
+ EMPTY_HOWTO (205),
+ EMPTY_HOWTO (206),
+ EMPTY_HOWTO (207),
+ EMPTY_HOWTO (208),
+ EMPTY_HOWTO (209),
+ EMPTY_HOWTO (210),
+ EMPTY_HOWTO (211),
+ EMPTY_HOWTO (212),
+ EMPTY_HOWTO (213),
+ EMPTY_HOWTO (214),
+ EMPTY_HOWTO (215),
+ EMPTY_HOWTO (216),
+ EMPTY_HOWTO (217),
+ EMPTY_HOWTO (218),
+ EMPTY_HOWTO (219),
+ EMPTY_HOWTO (220),
+ EMPTY_HOWTO (221),
+ EMPTY_HOWTO (222),
+ EMPTY_HOWTO (223),
+ EMPTY_HOWTO (224),
+ EMPTY_HOWTO (225),
+ EMPTY_HOWTO (226),
+ EMPTY_HOWTO (227),
+ EMPTY_HOWTO (228),
+ EMPTY_HOWTO (229),
+ EMPTY_HOWTO (230),
+ EMPTY_HOWTO (231),
+ EMPTY_HOWTO (232),
+ EMPTY_HOWTO (233),
+ EMPTY_HOWTO (234),
+ EMPTY_HOWTO (235),
+ EMPTY_HOWTO (236),
+ EMPTY_HOWTO (237),
+ EMPTY_HOWTO (238),
+ EMPTY_HOWTO (239),
+ EMPTY_HOWTO (240),
+ EMPTY_HOWTO (241),
+ EMPTY_HOWTO (242),
+ EMPTY_HOWTO (243),
+ EMPTY_HOWTO (244),
+ EMPTY_HOWTO (245),
+ EMPTY_HOWTO (246),
+ EMPTY_HOWTO (247),
+ EMPTY_HOWTO (248),
+ EMPTY_HOWTO (249),
+ EMPTY_HOWTO (250),
+ EMPTY_HOWTO (251),
+ EMPTY_HOWTO (252),
+ HOWTO (R_C6000_ALIGN, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_ALIGN", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_FPHEAD, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_FPHEAD", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+ HOWTO (R_C6000_NOCMP, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_C6000_NOCMP", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE) /* pcrel_offset */
+};
+
+/* Map BFD relocations to ELF relocations. */
+
+typedef struct
+{
+ bfd_reloc_code_real_type bfd_reloc_val;
+ enum elf_tic6x_reloc_type elf_reloc_val;
+} tic6x_reloc_map;
+
+static const tic6x_reloc_map elf32_tic6x_reloc_map[] =
+ {
+ { BFD_RELOC_NONE, R_C6000_NONE },
+ { BFD_RELOC_32, R_C6000_ABS32 },
+ { BFD_RELOC_16, R_C6000_ABS16 },
+ { BFD_RELOC_8, R_C6000_ABS8 },
+ { BFD_RELOC_C6000_PCR_S21, R_C6000_PCR_S21 },
+ { BFD_RELOC_C6000_PCR_S12, R_C6000_PCR_S12 },
+ { BFD_RELOC_C6000_PCR_S10, R_C6000_PCR_S10 },
+ { BFD_RELOC_C6000_PCR_S7, R_C6000_PCR_S7 },
+ { BFD_RELOC_C6000_ABS_S16, R_C6000_ABS_S16 },
+ { BFD_RELOC_C6000_ABS_L16, R_C6000_ABS_L16 },
+ { BFD_RELOC_C6000_ABS_H16, R_C6000_ABS_H16 },
+ { BFD_RELOC_C6000_SBR_U15_B, R_C6000_SBR_U15_B },
+ { BFD_RELOC_C6000_SBR_U15_H, R_C6000_SBR_U15_H },
+ { BFD_RELOC_C6000_SBR_U15_W, R_C6000_SBR_U15_W },
+ { BFD_RELOC_C6000_SBR_S16, R_C6000_SBR_S16 },
+ { BFD_RELOC_C6000_SBR_L16_B, R_C6000_SBR_L16_B },
+ { BFD_RELOC_C6000_SBR_L16_H, R_C6000_SBR_L16_H },
+ { BFD_RELOC_C6000_SBR_L16_W, R_C6000_SBR_L16_W },
+ { BFD_RELOC_C6000_SBR_H16_B, R_C6000_SBR_H16_B },
+ { BFD_RELOC_C6000_SBR_H16_H, R_C6000_SBR_H16_H },
+ { BFD_RELOC_C6000_SBR_H16_W, R_C6000_SBR_H16_W },
+ { BFD_RELOC_C6000_SBR_GOT_U15_W, R_C6000_SBR_GOT_U15_W },
+ { BFD_RELOC_C6000_SBR_GOT_L16_W, R_C6000_SBR_GOT_L16_W },
+ { BFD_RELOC_C6000_SBR_GOT_H16_W, R_C6000_SBR_GOT_H16_W },
+ { BFD_RELOC_C6000_DSBT_INDEX, R_C6000_DSBT_INDEX },
+ { BFD_RELOC_C6000_PREL31, R_C6000_PREL31 },
+ { BFD_RELOC_C6000_COPY, R_C6000_COPY },
+ { BFD_RELOC_C6000_ALIGN, R_C6000_ALIGN },
+ { BFD_RELOC_C6000_FPHEAD, R_C6000_FPHEAD },
+ { BFD_RELOC_C6000_NOCMP, R_C6000_NOCMP }
+ };
+
+static reloc_howto_type *
+elf32_tic6x_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (elf32_tic6x_reloc_map); i++)
+ if (elf32_tic6x_reloc_map[i].bfd_reloc_val == code)
+ return &elf32_tic6x_howto_table[elf32_tic6x_reloc_map[i].elf_reloc_val];
+
+ return NULL;
+}
+
+static reloc_howto_type *
+elf32_tic6x_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (elf32_tic6x_howto_table); i++)
+ if (elf32_tic6x_howto_table[i].name != NULL
+ && strcasecmp (elf32_tic6x_howto_table[i].name, r_name) == 0)
+ return &elf32_tic6x_howto_table[i];
+
+ return NULL;
+}
+
+static void
+elf32_tic6x_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, arelent *bfd_reloc,
+ Elf_Internal_Rela *elf_reloc)
+{
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (elf_reloc->r_info);
+ if (r_type >= ARRAY_SIZE (elf32_tic6x_howto_table))
+ bfd_reloc->howto = NULL;
+ else
+ bfd_reloc->howto = &elf32_tic6x_howto_table[r_type];
+}
+
+static bfd_boolean
+elf32_tic6x_relocate_section (bfd *output_bfd,
+ struct bfd_link_info *info,
+ bfd *input_bfd,
+ asection *input_section,
+ bfd_byte *contents,
+ Elf_Internal_Rela *relocs,
+ Elf_Internal_Sym *local_syms,
+ asection **local_sections)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **sym_hashes;
+ Elf_Internal_Rela *rel;
+ Elf_Internal_Rela *relend;
+ bfd_boolean ok = TRUE;
+
+ symtab_hdr = & elf_symtab_hdr (input_bfd);
+ sym_hashes = elf_sym_hashes (input_bfd);
+
+ relend = relocs + input_section->reloc_count;
+
+ for (rel = relocs; rel < relend; rel ++)
+ {
+ int r_type;
+ unsigned long r_symndx;
+ arelent bfd_reloc;
+ reloc_howto_type *howto;
+ Elf_Internal_Sym *sym;
+ asection *sec;
+ struct elf_link_hash_entry *h;
+ bfd_vma relocation;
+ bfd_boolean unresolved_reloc;
+ bfd_reloc_status_type r;
+ struct bfd_link_hash_entry *sbh;
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+ r_symndx = ELF32_R_SYM (rel->r_info);
+
+ elf32_tic6x_info_to_howto (input_bfd, &bfd_reloc, rel);
+ howto = bfd_reloc.howto;
+ if (howto == NULL)
+ {
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+ unresolved_reloc = FALSE;
+
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ sec = local_sections[r_symndx];
+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+ }
+ else
+ {
+ bfd_boolean warned;
+
+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ r_symndx, symtab_hdr, sym_hashes,
+ h, sec, relocation,
+ unresolved_reloc, warned);
+ }
+
+ if (sec != NULL && elf_discarded_section (sec))
+ {
+ /* For relocs against symbols from removed linkonce sections,
+ or sections discarded by a linker script, we just want the
+ section contents zeroed. Avoid any special processing. */
+ _bfd_clear_contents (howto, input_bfd, contents + rel->r_offset);
+ rel->r_info = 0;
+ rel->r_addend = 0;
+ continue;
+ }
+
+ if (info->relocatable)
+ continue;
+
+ switch (r_type)
+ {
+ case R_C6000_NONE:
+ case R_C6000_ALIGN:
+ case R_C6000_FPHEAD:
+ case R_C6000_NOCMP:
+ /* No action needed. */
+ continue;
+
+ case R_C6000_PCR_S21:
+ case R_C6000_PCR_S12:
+ case R_C6000_PCR_S10:
+ case R_C6000_PCR_S7:
+ /* Generic PC-relative handling produces a value relative to
+ the exact location of the relocation. Adjust it to be
+ relative to the start of the fetch packet instead. */
+ relocation += (input_section->output_section->vma
+ + input_section->output_offset
+ + rel->r_offset) & 0x1f;
+ /* Fall through. */
+ case R_C6000_ABS32:
+ case R_C6000_ABS16:
+ case R_C6000_ABS8:
+ case R_C6000_ABS_S16:
+ case R_C6000_ABS_L16:
+ case R_C6000_ABS_H16:
+ /* Generic logic OK. */
+ break;
+
+ case R_C6000_SBR_U15_B:
+ case R_C6000_SBR_U15_H:
+ case R_C6000_SBR_U15_W:
+ case R_C6000_SBR_S16:
+ case R_C6000_SBR_L16_B:
+ case R_C6000_SBR_L16_H:
+ case R_C6000_SBR_L16_W:
+ case R_C6000_SBR_H16_B:
+ case R_C6000_SBR_H16_H:
+ case R_C6000_SBR_H16_W:
+ sbh = bfd_link_hash_lookup (info->hash, "__c6xabi_DSBT_BASE",
+ FALSE, FALSE, TRUE);
+ if (sbh != NULL
+ && (sbh->type == bfd_link_hash_defined
+ || sbh->type == bfd_link_hash_defweak))
+ relocation -= (sbh->u.def.value
+ + sbh->u.def.section->output_section->vma
+ + sbh->u.def.section->output_offset);
+ else
+ {
+ (*_bfd_error_handler) (_("%B: SB-relative relocation but "
+ "__c6xabi_DSBT_BASE not defined"),
+ input_bfd);
+ ok = FALSE;
+ continue;
+ }
+ break;
+
+ case R_C6000_SBR_GOT_U15_W:
+ case R_C6000_SBR_GOT_L16_W:
+ case R_C6000_SBR_GOT_H16_W:
+ case R_C6000_DSBT_INDEX:
+ case R_C6000_PREL31:
+ /* Shared libraries and exception handling support not
+ implemented. */
+ (*_bfd_error_handler) (_("%B: relocation type %d not implemented"),
+ input_bfd, r_type);
+ ok = FALSE;
+ continue;
+
+ case R_C6000_COPY:
+ /* Invalid in relocatable object. */
+ default:
+ /* Unknown relocation. */
+ (*_bfd_error_handler) (_("%B: invalid relocation type %d"),
+ input_bfd, r_type);
+ ok = FALSE;
+ continue;
+ }
+
+ r = _bfd_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel->r_offset,
+ relocation, rel->r_addend);
+
+ if (r == bfd_reloc_ok
+ && howto->complain_on_overflow == complain_overflow_bitfield)
+ {
+ /* Generic overflow handling accepts cases the ABI says
+ should be rejected for R_C6000_ABS16 and
+ R_C6000_ABS8. */
+ bfd_vma value = (relocation + rel->r_addend) & 0xffffffff;
+ bfd_vma sbit = 1 << (howto->bitsize - 1);
+ bfd_vma sbits = (-(bfd_vma) sbit) & 0xffffffff;
+ bfd_vma value_sbits = value & sbits;
+
+ if (value_sbits != 0
+ && value_sbits != sbit
+ && value_sbits != sbits)
+ r = bfd_reloc_overflow;
+ }
+
+ if (r != bfd_reloc_ok)
+ {
+ const char *name;
+ const char *error_message;
+
+ if (h != NULL)
+ name = h->root.root.string;
+ else
+ {
+ name = bfd_elf_string_from_elf_section (input_bfd,
+ symtab_hdr->sh_link,
+ sym->st_name);
+ if (name == NULL)
+ return FALSE;
+ if (*name == '\0')
+ name = bfd_section_name (input_bfd, sec);
+ }
+
+ switch (r)
+ {
+ case bfd_reloc_overflow:
+ /* If the overflowing reloc was to an undefined symbol,
+ we have already printed one error message and there
+ is no point complaining again. */
+ if ((! h ||
+ h->root.type != bfd_link_hash_undefined)
+ && (!((*info->callbacks->reloc_overflow)
+ (info, (h ? &h->root : NULL), name, howto->name,
+ (bfd_vma) 0, input_bfd, input_section,
+ rel->r_offset))))
+ return FALSE;
+ break;
+
+ case bfd_reloc_undefined:
+ if (!((*info->callbacks->undefined_symbol)
+ (info, name, input_bfd, input_section,
+ rel->r_offset, TRUE)))
+ return FALSE;
+ break;
+
+ case bfd_reloc_outofrange:
+ error_message = _("out of range");
+ goto common_error;
+
+ case bfd_reloc_notsupported:
+ error_message = _("unsupported relocation");
+ goto common_error;
+
+ case bfd_reloc_dangerous:
+ error_message = _("dangerous relocation");
+ goto common_error;
+
+ default:
+ error_message = _("unknown error");
+ /* Fall through. */
+
+ common_error:
+ BFD_ASSERT (error_message != NULL);
+ if (!((*info->callbacks->reloc_dangerous)
+ (info, error_message, input_bfd, input_section,
+ rel->r_offset)))
+ return FALSE;
+ break;
+ }
+ }
+ }
+
+ return ok;
+}
+
+
+#define TARGET_LITTLE_SYM bfd_elf32_tic6x_le_vec
+#define TARGET_LITTLE_NAME "elf32-tic6x-le"
+#define TARGET_BIG_SYM bfd_elf32_tic6x_be_vec
+#define TARGET_BIG_NAME "elf32-tic6x-be"
+#define ELF_ARCH bfd_arch_tic6x
+#define ELF_MACHINE_CODE EM_TI_C6000
+#define ELF_MAXPAGESIZE 1
+#define bfd_elf32_bfd_reloc_type_lookup elf32_tic6x_reloc_type_lookup
+#define bfd_elf32_bfd_reloc_name_lookup elf32_tic6x_reloc_name_lookup
+#define elf_backend_can_gc_sections 1
+#define elf_backend_default_use_rela_p 1
+#define elf_backend_may_use_rel_p 1
+#define elf_backend_may_use_rela_p 1
+#define elf_backend_rela_normal 1
+#define elf_backend_relocate_section elf32_tic6x_relocate_section
+#define elf_info_to_howto elf32_tic6x_info_to_howto
+#define elf_info_to_howto_rel _bfd_elf_no_info_to_howto
+
+#include "elf32-target.h"
(This include file is not for users of the library.)
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
+ 2010
Free Software Foundation, Inc.
Written by Cygnus Support.
"BFD_RELOC_TIC54X_23",
"BFD_RELOC_TIC54X_16_OF_23",
"BFD_RELOC_TIC54X_MS7_OF_23",
+ "BFD_RELOC_C6000_PCR_S21",
+ "BFD_RELOC_C6000_PCR_S12",
+ "BFD_RELOC_C6000_PCR_S10",
+ "BFD_RELOC_C6000_PCR_S7",
+ "BFD_RELOC_C6000_ABS_S16",
+ "BFD_RELOC_C6000_ABS_L16",
+ "BFD_RELOC_C6000_ABS_H16",
+ "BFD_RELOC_C6000_SBR_U15_B",
+ "BFD_RELOC_C6000_SBR_U15_H",
+ "BFD_RELOC_C6000_SBR_U15_W",
+ "BFD_RELOC_C6000_SBR_S16",
+ "BFD_RELOC_C6000_SBR_L16_B",
+ "BFD_RELOC_C6000_SBR_L16_H",
+ "BFD_RELOC_C6000_SBR_L16_W",
+ "BFD_RELOC_C6000_SBR_H16_B",
+ "BFD_RELOC_C6000_SBR_H16_H",
+ "BFD_RELOC_C6000_SBR_H16_W",
+ "BFD_RELOC_C6000_SBR_GOT_U15_W",
+ "BFD_RELOC_C6000_SBR_GOT_L16_W",
+ "BFD_RELOC_C6000_SBR_GOT_H16_W",
+ "BFD_RELOC_C6000_DSBT_INDEX",
+ "BFD_RELOC_C6000_PREL31",
+ "BFD_RELOC_C6000_COPY",
+ "BFD_RELOC_C6000_ALIGN",
+ "BFD_RELOC_C6000_FPHEAD",
+ "BFD_RELOC_C6000_NOCMP",
"BFD_RELOC_FR30_48",
"BFD_RELOC_FR30_20",
"BFD_RELOC_FR30_6_IN_4",
significant 7 bits of a 23-bit extended address are placed into
the opcode.
+ENUM
+ BFD_RELOC_C6000_PCR_S21
+ENUMX
+ BFD_RELOC_C6000_PCR_S12
+ENUMX
+ BFD_RELOC_C6000_PCR_S10
+ENUMX
+ BFD_RELOC_C6000_PCR_S7
+ENUMX
+ BFD_RELOC_C6000_ABS_S16
+ENUMX
+ BFD_RELOC_C6000_ABS_L16
+ENUMX
+ BFD_RELOC_C6000_ABS_H16
+ENUMX
+ BFD_RELOC_C6000_SBR_U15_B
+ENUMX
+ BFD_RELOC_C6000_SBR_U15_H
+ENUMX
+ BFD_RELOC_C6000_SBR_U15_W
+ENUMX
+ BFD_RELOC_C6000_SBR_S16
+ENUMX
+ BFD_RELOC_C6000_SBR_L16_B
+ENUMX
+ BFD_RELOC_C6000_SBR_L16_H
+ENUMX
+ BFD_RELOC_C6000_SBR_L16_W
+ENUMX
+ BFD_RELOC_C6000_SBR_H16_B
+ENUMX
+ BFD_RELOC_C6000_SBR_H16_H
+ENUMX
+ BFD_RELOC_C6000_SBR_H16_W
+ENUMX
+ BFD_RELOC_C6000_SBR_GOT_U15_W
+ENUMX
+ BFD_RELOC_C6000_SBR_GOT_L16_W
+ENUMX
+ BFD_RELOC_C6000_SBR_GOT_H16_W
+ENUMX
+ BFD_RELOC_C6000_DSBT_INDEX
+ENUMX
+ BFD_RELOC_C6000_PREL31
+ENUMX
+ BFD_RELOC_C6000_COPY
+ENUMX
+ BFD_RELOC_C6000_ALIGN
+ENUMX
+ BFD_RELOC_C6000_FPHEAD
+ENUMX
+ BFD_RELOC_C6000_NOCMP
+ENUMDOC
+ TMS320C6000 relocations.
+
ENUM
BFD_RELOC_FR30_48
ENUMDOC
extern const bfd_target bfd_elf32_sparc_vec;
extern const bfd_target bfd_elf32_sparc_vxworks_vec;
extern const bfd_target bfd_elf32_spu_vec;
+extern const bfd_target bfd_elf32_tic6x_be_vec;
+extern const bfd_target bfd_elf32_tic6x_le_vec;
extern const bfd_target bfd_elf32_tradbigmips_vec;
extern const bfd_target bfd_elf32_tradlittlemips_vec;
extern const bfd_target bfd_elf32_us_cris_vec;
&bfd_elf32_sparc_vec,
&bfd_elf32_sparc_vxworks_vec,
&bfd_elf32_spu_vec,
+ &bfd_elf32_tic6x_be_vec,
+ &bfd_elf32_tic6x_le_vec,
&bfd_elf32_tradbigmips_vec,
&bfd_elf32_tradlittlemips_vec,
&bfd_elf32_us_cris_vec,
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * MAINTAINERS: Add self as TI C6X maintainer.
+ * NEWS: Add news entry for TI C6X support.
+ * readelf.c: Include elf/tic6x.h.
+ (guess_is_rela): Handle EM_TI_C6000.
+ (dump_relocations): Likewise.
+ (get_tic6x_dynamic_type): New.
+ (get_dynamic_type): Call it.
+ (get_machine_flags): Handle EF_C6000_REL.
+ (get_osabi_name): Handle machine-specific values only for relevant
+ machines. Handle C6X values.
+ (get_tic6x_segment_type): New.
+ (get_segment_type): Call it.
+ (get_tic6x_section_type_name): New.
+ (get_section_type_name): Call it.
+ (is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle
+ EM_TI_C6000.
+
2010-03-25 Thomas Schwinge <thomas@codesourcery.com>
* doc/binutils.texi (readelf) <unwind information>: Mention support for
SPU Alan Modra <amodra@gmail.com>
TIC4X Svein Seldal <svein@dev.seldal.com>
TIC54X Timothy Wall <twall@alum.mit.edu>
+ TIC6X Joseph Myers <joseph@codesourcery.com>
VAX Matt Thomas <matt@netbsd.org>
VAX Jan-Benedict Glaw <jbglaw@lug-owl.de>
VMS Tristan Gingold <gingold@adacore.com>
-*- text -*-
+* Add support for the TMS320C6000 (TI C6X) processor family.
+
* Readelf can now display ARM unwind tables (.ARM.exidx / .ARM.extab) using
the -u / --unwind option.
#include "elf/sh.h"
#include "elf/sparc.h"
#include "elf/spu.h"
+#include "elf/tic6x.h"
#include "elf/v850.h"
#include "elf/vax.h"
#include "elf/x86-64.h"
case EM_SPARC32PLUS:
case EM_SPARCV9:
case EM_SPU:
+ case EM_TI_C6000:
case EM_V850:
case EM_CYGNUS_V850:
case EM_VAX:
case EM_C166:
rtype = elf_xc16x_reloc_type (type);
break;
+
+ case EM_TI_C6000:
+ rtype = elf_tic6x_reloc_type (type);
+ break;
}
if (rtype == NULL)
}
}
+static const char *
+get_tic6x_dynamic_type (unsigned long type)
+{
+ switch (type)
+ {
+ case DT_C6000_GSYM_OFFSET: return "C6000_GSYM_OFFSET";
+ case DT_C6000_GSTR_OFFSET: return "C6000_GSTR_OFFSET";
+ case DT_C6000_DSBT_BASE: return "C6000_DSBT_BASE";
+ case DT_C6000_DSBT_SIZE: return "C6000_DSBT_SIZE";
+ case DT_C6000_PREEMPTMAP: return "C6000_PREEMPTMAP";
+ case DT_C6000_DSBT_INDEX: return "C6000_DSBT_INDEX";
+ default:
+ return NULL;
+ }
+}
static const char *
get_dynamic_type (unsigned long type)
case EM_SCORE:
result = get_score_dynamic_type (type);
break;
+ case EM_TI_C6000:
+ result = get_tic6x_dynamic_type (type);
+ break;
default:
result = NULL;
break;
case EM_S390:
if (e_flags & EF_S390_HIGH_GPRS)
strcat (buf, ", highgprs");
+
+ case EM_TI_C6000:
+ if ((e_flags & EF_C6000_REL))
+ strcat (buf, ", relocatable module");
}
}
case ELFOSABI_NSK: return "HP - Non-Stop Kernel";
case ELFOSABI_AROS: return "AROS";
case ELFOSABI_FENIXOS: return "FenixOS";
- case ELFOSABI_STANDALONE: return _("Standalone App");
- case ELFOSABI_ARM: return "ARM";
default:
+ if (osabi >= 64)
+ switch (elf_header.e_machine)
+ {
+ case EM_ARM:
+ switch (osabi)
+ {
+ case ELFOSABI_ARM: return "ARM";
+ default:
+ break;
+ }
+ break;
+
+ case EM_MSP430:
+ case EM_MSP430_OLD:
+ switch (osabi)
+ {
+ case ELFOSABI_STANDALONE: return _("Standalone App");
+ default:
+ break;
+ }
+ break;
+
+ case EM_TI_C6000:
+ switch (osabi)
+ {
+ case ELFOSABI_C6000_ELFABI: return _("Bare-metal C6000");
+ case ELFOSABI_C6000_LINUX: return "Linux C6000";
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
snprintf (buff, sizeof (buff), _("<unknown: %x>"), osabi);
return buff;
}
return NULL;
}
+static const char *
+get_tic6x_segment_type (unsigned long type)
+{
+ switch (type)
+ {
+ case PT_C6000_PHATTR: return "C6000_PHATTR";
+ default:
+ break;
+ }
+
+ return NULL;
+}
+
static const char *
get_segment_type (unsigned long p_type)
{
case EM_IA_64:
result = get_ia64_segment_type (p_type);
break;
+ case EM_TI_C6000:
+ result = get_tic6x_segment_type (p_type);
+ break;
default:
result = NULL;
break;
return NULL;
}
+static const char *
+get_tic6x_section_type_name (unsigned int sh_type)
+{
+ switch (sh_type)
+ {
+ case SHT_C6000_UNWIND:
+ return "C6000_UNWIND";
+ case SHT_C6000_PREEMPTMAP:
+ return "C6000_PREEMPTMAP";
+ case SHT_C6000_ATTRIBUTES:
+ return "C6000_ATTRIBUTES";
+ case SHT_TI_ICODE:
+ return "TI_ICODE";
+ case SHT_TI_XREF:
+ return "TI_XREF";
+ case SHT_TI_HANDLER:
+ return "TI_HANDLER";
+ case SHT_TI_INITINFO:
+ return "TI_INITINFO";
+ case SHT_TI_PHATTRS:
+ return "TI_PHATTRS";
+ default:
+ break;
+ }
+ return NULL;
+}
+
static const char *
get_section_type_name (unsigned int sh_type)
{
case EM_ARM:
result = get_arm_section_type_name (sh_type);
break;
+ case EM_TI_C6000:
+ result = get_tic6x_section_type_name (sh_type);
+ break;
default:
result = NULL;
break;
|| reloc_type == 23; /* R_SPARC_UA32. */
case EM_SPU:
return reloc_type == 6; /* R_SPU_ADDR32 */
+ case EM_TI_C6000:
+ return reloc_type == 1; /* R_C6000_ABS32. */
case EM_CYGNUS_V850:
case EM_V850:
return reloc_type == 6; /* R_V850_ABS32. */
case EM_ALTERA_NIOS2:
case EM_NIOS32:
return reloc_type == 9; /* R_NIOS_16. */
+ case EM_TI_C6000:
+ return reloc_type == 2; /* R_C6000_ABS16. */
case EM_XC16X:
case EM_C166:
return reloc_type == 2; /* R_XC16C_ABS_16. */
case EM_L1OM: /* R_X86_64_NONE. */
case EM_MN10300: /* R_MN10300_NONE. */
case EM_M32R: /* R_M32R_NONE. */
+ case EM_TI_C6000:/* R_C6000_NONE. */
case EM_XC16X:
case EM_C166: /* R_XC16X_NONE. */
return reloc_type == 0;
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
+ (TARGET_CPU_HFILES): Add config/tc-tic6x.h.
+ * Makefile.in: Regenerate.
+ * NEWS: Add news entry for TI C6X support.
+ * app.c (do_scrub_chars): Handle "||^" for TI C6X. Handle
+ TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR. Keep spaces in
+ operands if TC_KEEP_OPERAND_SPACES.
+ * configure.tgt (tic6x-*-*): New.
+ * config/tc-ia64.h (TC_PREDICATE_START_CHAR,
+ TC_PREDICATE_END_CHAR): Define.
+ * config/tc-tic6x.c, config/tc-tic6x.h: New.
+ * doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
+ * doc/Makefile.in: Regenerate.
+ * doc/all.texi (TIC6X): Define.
+ * doc/as.texinfo: Add TI C6X documentation. Include c-tic6x.texi.
+ * doc/c-tic6x.texi: New.
+
2010-03-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (lex_got): Use STRING_COMMA_LEN on gotrel.
config/tc-tic30.c \
config/tc-tic4x.c \
config/tc-tic54x.c \
+ config/tc-tic6x.c \
config/tc-vax.c \
config/tc-v850.c \
config/tc-xstormy16.c \
config/tc-tic30.h \
config/tc-tic4x.h \
config/tc-tic54x.h \
+ config/tc-tic6x.h \
config/tc-vax.h \
config/tc-v850.h \
config/tc-xstormy16.h \
config/tc-tic30.c \
config/tc-tic4x.c \
config/tc-tic54x.c \
+ config/tc-tic6x.c \
config/tc-vax.c \
config/tc-v850.c \
config/tc-xstormy16.c \
config/tc-tic30.h \
config/tc-tic4x.h \
config/tc-tic54x.h \
+ config/tc-tic6x.h \
config/tc-vax.h \
config/tc-v850.h \
config/tc-xstormy16.h \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-tic30.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-tic4x.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-tic54x.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-tic6x.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-v850.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-vax.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-xc16x.Po@am__quote@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-tic54x.obj `if test -f 'config/tc-tic54x.c'; then $(CYGPATH_W) 'config/tc-tic54x.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-tic54x.c'; fi`
+tc-tic6x.o: config/tc-tic6x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-tic6x.o -MD -MP -MF $(DEPDIR)/tc-tic6x.Tpo -c -o tc-tic6x.o `test -f 'config/tc-tic6x.c' || echo '$(srcdir)/'`config/tc-tic6x.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-tic6x.Tpo $(DEPDIR)/tc-tic6x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-tic6x.c' object='tc-tic6x.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-tic6x.o `test -f 'config/tc-tic6x.c' || echo '$(srcdir)/'`config/tc-tic6x.c
+
+tc-tic6x.obj: config/tc-tic6x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-tic6x.obj -MD -MP -MF $(DEPDIR)/tc-tic6x.Tpo -c -o tc-tic6x.obj `if test -f 'config/tc-tic6x.c'; then $(CYGPATH_W) 'config/tc-tic6x.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-tic6x.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-tic6x.Tpo $(DEPDIR)/tc-tic6x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-tic6x.c' object='tc-tic6x.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-tic6x.obj `if test -f 'config/tc-tic6x.c'; then $(CYGPATH_W) 'config/tc-tic6x.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-tic6x.c'; fi`
+
tc-vax.o: config/tc-vax.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-vax.o -MD -MP -MF $(DEPDIR)/tc-vax.Tpo -c -o tc-vax.o `test -f 'config/tc-vax.c' || echo '$(srcdir)/'`config/tc-vax.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-vax.Tpo $(DEPDIR)/tc-vax.Po
-*- text -*-
+* Add support for the TMS320C6000 (TI C6X) processor family.
+
* GAS now understands an extended syntax in the .section directive flags
for COFF targets that allows the section's alignment to be specified. This
feature has also been backported to the 2.20 release series, starting with
/* This is the Assembler Pre-Processor
Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008
+ 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
13: After seeing a vertical bar, looking for a second
vertical bar as a parallel expression separator.
#endif
-#ifdef TC_IA64
- 14: After seeing a `(' at state 0, looking for a `)' as
- predicate.
- 15: After seeing a `(' at state 1, looking for a `)' as
- predicate.
+#ifdef TC_PREDICATE_START_CHAR
+ 14: After seeing a predicate start character at state 0, looking
+ for a predicate end character as predicate.
+ 15: After seeing a predicate start character at state 1, looking
+ for a predicate end character as predicate.
#endif
#ifdef TC_Z80
16: After seeing an 'a' or an 'A' at the start of a symbol
line from just after the first white space. */
state = 1;
PUT ('|');
+#ifdef TC_TIC6X
+ /* "||^" is used for SPMASKed instructions. */
+ ch = GET ();
+ if (ch == EOF)
+ goto fromeof;
+ else if (ch == '^')
+ PUT ('^');
+ else
+ UNGET (ch);
+#endif
continue;
#endif
#ifdef TC_Z80
/* flushchar: */
ch = GET ();
-#ifdef TC_IA64
- if (ch == '(' && (state == 0 || state == 1))
+#ifdef TC_PREDICATE_START_CHAR
+ if (ch == TC_PREDICATE_START_CHAR && (state == 0 || state == 1))
{
state += 14;
PUT (ch);
}
else if (state == 14 || state == 15)
{
- if (ch == ')')
+ if (ch == TC_PREDICATE_END_CHAR)
{
state -= 14;
PUT (ch);
PUT (' ');
break;
case 3:
+#ifndef TC_KEEP_OPERAND_SPACES
+ /* For TI C6X, we keep these spaces as they may separate
+ functional unit specifiers from operands. */
if (scrub_m68k_mri)
+#endif
{
/* In MRI mode, we keep these spaces. */
UNGET (ch);
goto recycle; /* Sp in operands */
case 9:
case 10:
+#ifndef TC_KEEP_OPERAND_SPACES
if (scrub_m68k_mri)
+#endif
{
/* In MRI mode, we keep these spaces. */
state = 3;
/* tc-ia64.h -- Header file for tc-ia64.c.
Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008,
- 2009 Free Software Foundation, Inc.
+ 2009, 2010 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GAS, the GNU Assembler.
#define LEX_QM (LEX_NAME|LEX_BEGIN_NAME) /* allow `?' inside name */
#define LEX_HASH LEX_END_NAME /* allow `#' ending a name */
+#define TC_PREDICATE_START_CHAR '('
+#define TC_PREDICATE_END_CHAR ')'
+
extern const char ia64_symbol_chars[];
#define tc_symbol_chars ia64_symbol_chars
--- /dev/null
+/* TI C6X assembler.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#include "as.h"
+#include "dwarf2dbg.h"
+#include "safe-ctype.h"
+#include "subsegs.h"
+#include "opcode/tic6x.h"
+
+/* Truncate and sign-extend at 32 bits, so that building on a 64-bit
+ host gives identical results to a 32-bit host. */
+#define TRUNC(X) ((valueT) (X) & 0xffffffffU)
+#define SEXT(X) ((TRUNC (X) ^ 0x80000000U) - 0x80000000U)
+
+const char comment_chars[] = ";";
+const char line_comment_chars[] = "#*;";
+const char line_separator_chars[] = "@";
+
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "dDfF";
+
+const char *md_shortopts = "";
+
+enum
+ {
+ OPTION_MARCH = OPTION_MD_BASE,
+ OPTION_MATOMIC,
+ OPTION_MNO_ATOMIC,
+ OPTION_MBIG_ENDIAN,
+ OPTION_MLITTLE_ENDIAN
+ };
+
+struct option md_longopts[] =
+ {
+ { "march", required_argument, NULL, OPTION_MARCH },
+ { "matomic", no_argument, NULL, OPTION_MATOMIC },
+ { "mno-atomic", no_argument, NULL, OPTION_MNO_ATOMIC },
+ { "mbig-endian", no_argument, NULL, OPTION_MBIG_ENDIAN },
+ { "mlittle-endian", no_argument, NULL, OPTION_MLITTLE_ENDIAN },
+ { NULL, no_argument, NULL, 0 }
+ };
+size_t md_longopts_size = sizeof (md_longopts);
+
+/* Whether to enable atomic instructions. 1 to enable them, 0 to
+ disable, -1 to default from architecture. */
+static int tic6x_atomic = -1;
+
+/* The instructions enabled based only on the selected architecture
+ (all instructions, if no architecture specified). Atomic
+ instructions may be enabled or disabled separately. */
+static unsigned short tic6x_arch_enable = (TIC6X_INSN_C62X
+ | TIC6X_INSN_C64X
+ | TIC6X_INSN_C64XP
+ | TIC6X_INSN_C67X
+ | TIC6X_INSN_C67XP
+ | TIC6X_INSN_C674X
+ | TIC6X_INSN_ATOMIC);
+
+/* The instructions enabled based on the current set of features
+ (architecture, as modified by other options). */
+static unsigned short tic6x_features;
+
+/* The number of registers in each register file supported by the
+ current architecture. */
+static unsigned int tic6x_num_registers;
+
+/* Whether predication on A0 is possible. */
+static bfd_boolean tic6x_predicate_a0;
+
+/* Whether execute packets can cross fetch packet boundaries. */
+static bfd_boolean tic6x_can_cross_fp_boundary;
+
+/* Whether there are constraints on simultaneous reads and writes of
+ 40-bit data. */
+static bfd_boolean tic6x_long_data_constraints;
+
+/* Whether compact instructions are available. */
+static bfd_boolean tic6x_compact_insns;
+
+/* Table of supported architecture variants. */
+typedef struct
+{
+ const char *arch;
+ unsigned short features;
+} tic6x_arch_table;
+static const tic6x_arch_table tic6x_arches[] =
+ {
+ { "c62x", TIC6X_INSN_C62X },
+ { "c64x", TIC6X_INSN_C62X | TIC6X_INSN_C64X },
+ { "c64x+", TIC6X_INSN_C62X | TIC6X_INSN_C64X | TIC6X_INSN_C64XP },
+ { "c67x", TIC6X_INSN_C62X | TIC6X_INSN_C67X },
+ { "c67x+", TIC6X_INSN_C62X | TIC6X_INSN_C67X | TIC6X_INSN_C67XP },
+ { "c674x", (TIC6X_INSN_C62X
+ | TIC6X_INSN_C64X
+ | TIC6X_INSN_C64XP
+ | TIC6X_INSN_C67X
+ | TIC6X_INSN_C67XP
+ | TIC6X_INSN_C674X) }
+ };
+
+/* Update the selected architecture based on ARCH, giving an error if
+ ARCH is an invalid value. Does not call tic6x_update_features; the
+ caller must do that if necessary. */
+
+static void
+tic6x_use_arch (const char *arch)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (tic6x_arches); i++)
+ if (strcmp (arch, tic6x_arches[i].arch) == 0)
+ {
+ tic6x_arch_enable = tic6x_arches[i].features;
+ return;
+ }
+
+ as_bad (_("unknown architecture '%s'"), arch);
+}
+
+/* Parse a target-specific option. */
+
+int
+md_parse_option (int c, char *arg)
+{
+ switch (c)
+ {
+ case OPTION_MARCH:
+ tic6x_use_arch (arg);
+ break;
+
+ case OPTION_MATOMIC:
+ tic6x_atomic = 1;
+ break;
+
+ case OPTION_MNO_ATOMIC:
+ tic6x_atomic = 0;
+ break;
+
+ case OPTION_MBIG_ENDIAN:
+ target_big_endian = 1;
+ break;
+
+ case OPTION_MLITTLE_ENDIAN:
+ target_big_endian = 0;
+ break;
+
+ default:
+ return 0;
+ }
+ return 1;
+}
+
+void
+md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
+{
+ unsigned int i;
+
+ fputc ('\n', stream);
+ fprintf (stream, _("TMS320C6000 options:\n"));
+ fprintf (stream, _(" -march=ARCH enable instructions from architecture ARCH\n"));
+ fprintf (stream, _(" -matomic enable atomic operation instructions\n"));
+ fprintf (stream, _(" -mno-atomic disable atomic operation instructions\n"));
+ fprintf (stream, _(" -mbig-endian generate big-endian code\n"));
+ fprintf (stream, _(" -mlittle-endian generate little-endian code\n"));
+
+ fputc ('\n', stream);
+ fprintf (stream, _("Supported ARCH values are:"));
+ for (i = 0; i < ARRAY_SIZE (tic6x_arches); i++)
+ fprintf (stream, " %s", tic6x_arches[i].arch);
+ fputc ('\n', stream);
+}
+
+/* Update enabled features based on the current architecture and
+ related settings. */
+static void
+tic6x_update_features (void)
+{
+ switch (tic6x_atomic)
+ {
+ case -1:
+ tic6x_features = tic6x_arch_enable;
+ break;
+
+ case 0:
+ tic6x_features = tic6x_arch_enable & ~TIC6X_INSN_ATOMIC;
+ break;
+
+ case 1:
+ tic6x_features = tic6x_arch_enable | TIC6X_INSN_ATOMIC;
+ break;
+
+ default:
+ abort ();
+ }
+
+ tic6x_num_registers
+ = (tic6x_arch_enable & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) ? 32 : 16;
+
+ tic6x_predicate_a0 = (tic6x_arch_enable & TIC6X_INSN_C64X) ? TRUE : FALSE;
+
+ tic6x_can_cross_fp_boundary
+ = (tic6x_arch_enable
+ & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) ? TRUE : FALSE;
+
+ tic6x_long_data_constraints
+ = (tic6x_arch_enable & TIC6X_INSN_C64X) ? FALSE : TRUE;
+
+ tic6x_compact_insns = (tic6x_arch_enable & TIC6X_INSN_C64XP) ? TRUE : FALSE;
+}
+
+/* Do configuration after all options have been parsed. */
+
+void
+tic6x_after_parse_args (void)
+{
+ tic6x_update_features ();
+}
+
+/* Parse a .arch directive. */
+
+static void
+s_tic6x_arch (int ignored ATTRIBUTE_UNUSED)
+{
+ char c;
+ char *arch;
+
+ arch = input_line_pointer;
+ while (*input_line_pointer && !ISSPACE (*input_line_pointer))
+ input_line_pointer++;
+ c = *input_line_pointer;
+ *input_line_pointer = 0;
+
+ tic6x_use_arch (arch);
+ tic6x_update_features ();
+ *input_line_pointer = c;
+ demand_empty_rest_of_line ();
+}
+
+/* Parse a .atomic directive. */
+
+static void
+s_tic6x_atomic (int ignored ATTRIBUTE_UNUSED)
+{
+ tic6x_atomic = 1;
+ tic6x_update_features ();
+ demand_empty_rest_of_line ();
+}
+
+/* Parse a .noatomic directive. */
+
+static void
+s_tic6x_noatomic (int ignored ATTRIBUTE_UNUSED)
+{
+ tic6x_atomic = 0;
+ tic6x_update_features ();
+ demand_empty_rest_of_line ();
+}
+
+/* Parse a .nocmp directive. */
+
+static void
+s_tic6x_nocmp (int ignored ATTRIBUTE_UNUSED)
+{
+ seg_info (now_seg)->tc_segment_info_data.nocmp = TRUE;
+ demand_empty_rest_of_line ();
+}
+
+const pseudo_typeS md_pseudo_table[] =
+ {
+ { "arch", s_tic6x_arch, 0 },
+ { "atomic", s_tic6x_atomic, 0 },
+ { "noatomic", s_tic6x_noatomic, 0 },
+ { "nocmp", s_tic6x_nocmp, 0 },
+ { "word", cons, 4 },
+ { 0, 0, 0 }
+ };
+
+/* Hash table of opcodes. For each opcode name, this stores a pointer
+ to a tic6x_opcode_list listing (in an arbitrary order) all opcode
+ table entries with that name. */
+static struct hash_control *opcode_hash;
+
+/* Initialize the assembler (called once at assembler startup). */
+
+void
+md_begin (void)
+{
+ tic6x_opcode_id id;
+
+ bfd_set_arch_mach (stdoutput, TARGET_ARCH, 0);
+
+ /* Insert opcodes into the hash table. */
+ opcode_hash = hash_new ();
+ for (id = 0; id < tic6x_opcode_max; id++)
+ {
+ const char *errmsg;
+ tic6x_opcode_list *opc = xmalloc (sizeof (tic6x_opcode_list));
+
+ opc->id = id;
+ opc->next = hash_find (opcode_hash, tic6x_opcode_table[id].name);
+ if ((errmsg = hash_jam (opcode_hash, tic6x_opcode_table[id].name, opc))
+ != NULL)
+ as_fatal ("%s", _(errmsg));
+ }
+}
+
+/* Whether the current line being parsed had the "||" parallel bars. */
+static bfd_boolean tic6x_line_parallel;
+
+/* Whether the current line being parsed started "||^" to indicate an
+ SPMASKed parallel instruction. */
+static bfd_boolean tic6x_line_spmask;
+
+/* If the current line being parsed had an instruction predicate, the
+ creg value for that predicate (which must be nonzero); otherwise
+ 0. */
+static unsigned int tic6x_line_creg;
+
+/* If the current line being parsed had an instruction predicate, the
+ z value for that predicate; otherwise 0. */
+static unsigned int tic6x_line_z;
+
+/* Return 1 (updating input_line_pointer as appropriate) if the line
+ starting with C (immediately before input_line_pointer) starts with
+ pre-opcode text appropriate for this target, 0 otherwise. */
+
+int
+tic6x_unrecognized_line (int c)
+{
+ char *p, *endp;
+ unsigned int z;
+ bfd_boolean areg;
+ bfd_boolean bad_predicate;
+
+ switch (c)
+ {
+ case '|':
+ if (input_line_pointer[0] == '|')
+ {
+ if (input_line_pointer[1] == '^')
+ {
+ tic6x_line_spmask = TRUE;
+ input_line_pointer += 2;
+ }
+ else
+ input_line_pointer += 1;
+ if (tic6x_line_parallel)
+ as_bad (_("multiple '||' on same line"));
+ tic6x_line_parallel = TRUE;
+ if (tic6x_line_creg)
+ as_bad (_("'||' after predicate"));
+ return 1;
+ }
+ return 0;
+
+ case '[':
+ /* If it doesn't look like a predicate at all, just return 0.
+ If it looks like one but not a valid one, give a better
+ error. */
+ p = input_line_pointer;
+ while (*p != ']' && !is_end_of_line[(unsigned char) *p])
+ p++;
+ if (*p != ']')
+ return 0;
+ endp = p + 1;
+ p = input_line_pointer;
+ z = 0;
+ bad_predicate = FALSE;
+ if (*p == '!')
+ {
+ z = 1;
+ p++;
+ }
+ if (*p == 'A' || *p == 'a')
+ areg = TRUE;
+ else if (*p == 'B' || *p == 'b')
+ areg = FALSE;
+ else
+ {
+ areg = TRUE; /* Avoid uninitialized warning. */
+ bad_predicate = TRUE;
+ }
+ if (!bad_predicate)
+ {
+ p++;
+ if (*p != '0' && *p != '1' && *p != '2')
+ bad_predicate = TRUE;
+ else if (p[1] != ']')
+ bad_predicate = TRUE;
+ else
+ input_line_pointer = p + 2;
+ }
+
+ if (tic6x_line_creg)
+ as_bad (_("multiple predicates on same line"));
+
+ if (bad_predicate)
+ {
+ char ctmp = *endp;
+ *endp = 0;
+ as_bad (_("bad predicate '%s'"), input_line_pointer - 1);
+ *endp = ctmp;
+ input_line_pointer = endp;
+ return 1;
+ }
+
+ switch (*p)
+ {
+ case '0':
+ tic6x_line_creg = (areg ? 6 : 1);
+ if (areg && !tic6x_predicate_a0)
+ as_bad (_("predication on A0 not supported on this architecture"));
+ break;
+
+ case '1':
+ tic6x_line_creg = (areg ? 4 : 2);
+ break;
+
+ case '2':
+ tic6x_line_creg = (areg ? 5 : 3);
+ break;
+
+ default:
+ abort ();
+ }
+
+ tic6x_line_z = z;
+ return 1;
+
+ default:
+ return 0;
+ }
+}
+
+/* Do any target-specific handling of a label required. */
+
+void
+tic6x_frob_label (symbolS *sym ATTRIBUTE_UNUSED)
+{
+ if (tic6x_line_parallel)
+ {
+ as_bad (_("label after '||'"));
+ tic6x_line_parallel = FALSE;
+ tic6x_line_spmask = FALSE;
+ }
+ if (tic6x_line_creg)
+ {
+ as_bad (_("label after predicate"));
+ tic6x_line_creg = 0;
+ tic6x_line_z = 0;
+ }
+
+ seg_info (now_seg)->tc_segment_info_data.seen_label = TRUE;
+
+ /* Defining tc_frob_label overrides the ELF definition of
+ obj_frob_label, so we need to apply its effects here. */
+ dwarf2_emit_label (sym);
+}
+
+/* At end-of-line, give errors for start-of-line decorations that
+ needed an instruction but were not followed by one. */
+
+static void
+tic6x_end_of_line (void)
+{
+ if (tic6x_line_parallel)
+ {
+ as_bad (_("'||' not followed by instruction"));
+ tic6x_line_parallel = FALSE;
+ tic6x_line_spmask = FALSE;
+ }
+ if (tic6x_line_creg)
+ {
+ as_bad (_("predicate not followed by instruction"));
+ tic6x_line_creg = 0;
+ tic6x_line_z = 0;
+ }
+}
+
+/* Do any target-specific handling of the start of a logical line. */
+
+void
+tic6x_start_line_hook (void)
+{
+ tic6x_end_of_line ();
+}
+
+/* Do target-specific handling immediately after all input files have
+ been read. */
+
+void
+tic6x_cleanup (void)
+{
+ tic6x_end_of_line ();
+}
+
+/* Handle a data alignment of N bytes. */
+
+void
+tic6x_cons_align (int n ATTRIBUTE_UNUSED)
+{
+ segment_info_type *seginfo = seg_info (now_seg);
+
+ /* Data means there is no current execute packet, and that any label
+ applies to that data rather than a subsequent instruction. */
+ seginfo->tc_segment_info_data.num_execute_packet_insns = 0;
+ seginfo->tc_segment_info_data.seen_label = FALSE;
+ seginfo->tc_segment_info_data.last_insn_lsb = NULL;
+ seginfo->tc_segment_info_data.spmask_addr = NULL;
+}
+
+/* Types of operand for parsing purposes. These are used as bit-masks
+ to tell tic6x_parse_operand what forms of operand are
+ permitted. */
+#define TIC6X_OP_EXP 0x0001u
+#define TIC6X_OP_REG 0x0002u
+#define TIC6X_OP_REGPAIR 0x0004u
+#define TIC6X_OP_IRP 0x0008u
+#define TIC6X_OP_NRP 0x0010u
+/* With TIC6X_OP_MEM_NOUNREG, the contents of a () offset are always
+ interpreted as an expression, which may be a symbol with the same
+ name as a register that ends up being implicitly DP-relative. With
+ TIC6X_OP_MEM_UNREG, the contents of a () offset are interpreted as
+ a register if they match one, and failing that as an expression,
+ which must be constant. */
+#define TIC6X_OP_MEM_NOUNREG 0x0020u
+#define TIC6X_OP_MEM_UNREG 0x0040u
+#define TIC6X_OP_CTRL 0x0080u
+#define TIC6X_OP_FUNC_UNIT 0x0100u
+
+/* A register or register pair read by the assembler. */
+typedef struct
+{
+ /* The side the register is on (1 or 2). */
+ unsigned int side;
+ /* The register number (0 to 31). */
+ unsigned int num;
+} tic6x_register;
+
+/* Types of modification of a base address. */
+typedef enum
+ {
+ tic6x_mem_mod_none,
+ tic6x_mem_mod_plus,
+ tic6x_mem_mod_minus,
+ tic6x_mem_mod_preinc,
+ tic6x_mem_mod_predec,
+ tic6x_mem_mod_postinc,
+ tic6x_mem_mod_postdec
+ } tic6x_mem_mod;
+
+/* Scaled [] or unscaled () nature of an offset. */
+typedef enum
+ {
+ tic6x_offset_none,
+ tic6x_offset_scaled,
+ tic6x_offset_unscaled
+ } tic6x_mem_scaling;
+
+/* A memory operand read by the assembler. */
+typedef struct
+{
+ /* The base register. */
+ tic6x_register base_reg;
+ /* How the base register is modified. */
+ tic6x_mem_mod mod;
+ /* Whether there is an offset (required with plain "+" and "-"), and
+ whether it is scaled or unscaled if so. */
+ tic6x_mem_scaling scaled;
+ /* Whether the offset is a register (TRUE) or an expression
+ (FALSE). */
+ bfd_boolean offset_is_reg;
+ /* The offset. */
+ union
+ {
+ expressionS exp;
+ tic6x_register reg;
+ } offset;
+} tic6x_mem_ref;
+
+/* A functional unit in SPMASK operands read by the assembler. */
+typedef struct
+{
+ /* The basic unit. */
+ tic6x_func_unit_base base;
+ /* The side (1 or 2). */
+ unsigned int side;
+} tic6x_func_unit_operand;
+
+/* An operand read by the assembler. */
+typedef struct
+{
+ /* The syntactic form of the operand, as one of the bit-masks
+ above. */
+ unsigned int form;
+ /* The operand value. */
+ union
+ {
+ /* An expression: TIC6X_OP_EXP. */
+ expressionS exp;
+ /* A register: TIC6X_OP_REG, TIC6X_OP_REGPAIR. */
+ tic6x_register reg;
+ /* A memory reference: TIC6X_OP_MEM_NOUNREG,
+ TIC6X_OP_MEM_UNREG. */
+ tic6x_mem_ref mem;
+ /* A control register: TIC6X_OP_CTRL. */
+ tic6x_ctrl_id ctrl;
+ /* A functional unit: TIC6X_OP_FUNC_UNIT. */
+ tic6x_func_unit_operand func_unit;
+ } value;
+} tic6x_operand;
+
+#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
+
+/* Parse a register operand, or part of an operand, starting at *P.
+ If syntactically OK (including that the number is in the range 0 to
+ 31, but not necessarily in range for this architecture), return
+ TRUE, putting the register side and number in *REG and update *P to
+ point immediately after the register number; otherwise return FALSE
+ without changing *P (but possibly changing *REG). Do not print any
+ diagnostics. */
+
+static bfd_boolean
+tic6x_parse_register (char **p, tic6x_register *reg)
+{
+ char *r = *p;
+
+ switch (*r)
+ {
+ case 'a':
+ case 'A':
+ reg->side = 1;
+ break;
+
+ case 'b':
+ case 'B':
+ reg->side = 2;
+ break;
+
+ default:
+ return FALSE;
+ }
+ r++;
+
+ if (*r >= '0' && *r <= '9')
+ {
+ reg->num = *r - '0';
+ r++;
+ }
+ else
+ return FALSE;
+
+ if (reg->num > 0 && *r >= '0' && *r <= '9')
+ {
+ reg->num = reg->num * 10 + (*r - '0');
+ r++;
+ }
+
+ if (*r >= '0' && *r <= '9')
+ return FALSE;
+
+ if (reg->num >= 32)
+ return FALSE;
+ *p = r;
+ return TRUE;
+}
+
+/* Parse the initial two characters of a functional unit name starting
+ at *P. If OK, set *BASE and *SIDE and return TRUE; otherwise,
+ return FALSE. */
+
+static bfd_boolean
+tic6x_parse_func_unit_base (char *p, tic6x_func_unit_base *base,
+ unsigned int *side)
+{
+ bfd_boolean good_func_unit = TRUE;
+ tic6x_func_unit_base maybe_base = tic6x_func_unit_nfu;
+ unsigned int maybe_side = 0;
+
+ switch (p[0])
+ {
+ case 'd':
+ case 'D':
+ maybe_base = tic6x_func_unit_d;
+ break;
+
+ case 'l':
+ case 'L':
+ maybe_base = tic6x_func_unit_l;
+ break;
+
+ case 'm':
+ case 'M':
+ maybe_base = tic6x_func_unit_m;
+ break;
+
+ case 's':
+ case 'S':
+ maybe_base = tic6x_func_unit_s;
+ break;
+
+ default:
+ good_func_unit = FALSE;
+ break;
+ }
+
+ if (good_func_unit)
+ switch (p[1])
+ {
+ case '1':
+ maybe_side = 1;
+ break;
+
+ case '2':
+ maybe_side = 2;
+ break;
+
+ default:
+ good_func_unit = FALSE;
+ break;
+ }
+
+ if (good_func_unit)
+ {
+ *base = maybe_base;
+ *side = maybe_side;
+ }
+
+ return good_func_unit;
+}
+
+/* Parse an operand starting at *P. If the operand parses OK, return
+ TRUE and store the value in *OP; otherwise return FALSE (possibly
+ changing *OP). In any case, update *P to point to the following
+ comma or end of line. The possible operand forms are given by
+ OP_FORMS. For diagnostics, this is operand OPNO of an opcode
+ starting at STR, length OPC_LEN. */
+
+static bfd_boolean
+tic6x_parse_operand (char **p, tic6x_operand *op, unsigned int op_forms,
+ char *str, int opc_len, unsigned int opno)
+{
+ bfd_boolean operand_parsed = FALSE;
+ char *q = *p;
+
+ if ((op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG))
+ == (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG))
+ abort ();
+
+ /* Check for functional unit names for SPMASK and SPMASKR. */
+ if (!operand_parsed && (op_forms & TIC6X_OP_FUNC_UNIT))
+ {
+ tic6x_func_unit_base base = tic6x_func_unit_nfu;
+ unsigned int side = 0;
+
+ if (tic6x_parse_func_unit_base (q, &base, &side))
+ {
+ char *rq = q + 2;
+
+ skip_whitespace (rq);
+ if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
+ {
+ op->form = TIC6X_OP_FUNC_UNIT;
+ op->value.func_unit.base = base;
+ op->value.func_unit.side = side;
+ operand_parsed = TRUE;
+ q = rq;
+ }
+ }
+ }
+
+ /* Check for literal "irp". */
+ if (!operand_parsed && (op_forms & TIC6X_OP_IRP))
+ {
+ if ((q[0] == 'i' || q[0] == 'I')
+ && (q[1] == 'r' || q[1] == 'R')
+ && (q[2] == 'p' || q[2] == 'P'))
+ {
+ char *rq = q + 3;
+
+ skip_whitespace (rq);
+ if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
+ {
+ op->form = TIC6X_OP_IRP;
+ operand_parsed = TRUE;
+ q = rq;
+ }
+ }
+ }
+
+ /* Check for literal "nrp". */
+ if (!operand_parsed && (op_forms & TIC6X_OP_NRP))
+ {
+ if ((q[0] == 'n' || q[0] == 'N')
+ && (q[1] == 'r' || q[1] == 'R')
+ && (q[2] == 'p' || q[2] == 'P'))
+ {
+ char *rq = q + 3;
+
+ skip_whitespace (rq);
+ if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
+ {
+ op->form = TIC6X_OP_NRP;
+ operand_parsed = TRUE;
+ q = rq;
+ }
+ }
+ }
+
+ /* Check for control register names. */
+ if (!operand_parsed && (op_forms & TIC6X_OP_CTRL))
+ {
+ tic6x_ctrl_id crid;
+
+ for (crid = 0; crid < tic6x_ctrl_max; crid++)
+ {
+ size_t len = strlen (tic6x_ctrl_table[crid].name);
+
+ if (strncasecmp (tic6x_ctrl_table[crid].name, q, len) == 0)
+ {
+ char *rq = q + len;
+
+ skip_whitespace (rq);
+ if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
+ {
+ op->form = TIC6X_OP_CTRL;
+ op->value.ctrl = crid;
+ operand_parsed = TRUE;
+ q = rq;
+ if (!(tic6x_ctrl_table[crid].isa_variants & tic6x_features))
+ as_bad (_("control register '%s' not supported "
+ "on this architecture"),
+ tic6x_ctrl_table[crid].name);
+ }
+ }
+ }
+ }
+
+ /* See if this looks like a memory reference. */
+ if (!operand_parsed
+ && (op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG)))
+ {
+ bfd_boolean mem_ok = TRUE;
+ char *mq = q;
+ tic6x_mem_mod mem_mod = tic6x_mem_mod_none;
+ tic6x_register base_reg;
+ bfd_boolean require_offset, permit_offset;
+ tic6x_mem_scaling scaled;
+ bfd_boolean offset_is_reg;
+ expressionS offset_exp;
+ tic6x_register offset_reg;
+
+ if (*mq == '*')
+ mq++;
+ else
+ mem_ok = FALSE;
+
+ if (mem_ok)
+ {
+ skip_whitespace (mq);
+ switch (*mq)
+ {
+ case '+':
+ if (mq[1] == '+')
+ {
+ mem_mod = tic6x_mem_mod_preinc;
+ mq += 2;
+ }
+ else
+ {
+ mem_mod = tic6x_mem_mod_plus;
+ mq++;
+ }
+ break;
+
+ case '-':
+ if (mq[1] == '-')
+ {
+ mem_mod = tic6x_mem_mod_predec;
+ mq += 2;
+ }
+ else
+ {
+ mem_mod = tic6x_mem_mod_minus;
+ mq++;
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (mem_ok)
+ {
+ skip_whitespace (mq);
+ mem_ok = tic6x_parse_register (&mq, &base_reg);
+ }
+
+ if (mem_ok && mem_mod == tic6x_mem_mod_none)
+ {
+ skip_whitespace (mq);
+ if (mq[0] == '+' && mq[1] == '+')
+ {
+ mem_mod = tic6x_mem_mod_postinc;
+ mq += 2;
+ }
+ else if (mq[0] == '-' && mq[1] == '-')
+ {
+ mem_mod = tic6x_mem_mod_postdec;
+ mq += 2;
+ }
+ }
+
+ if (mem_mod == tic6x_mem_mod_none)
+ permit_offset = FALSE;
+ else
+ permit_offset = TRUE;
+ if (mem_mod == tic6x_mem_mod_plus || mem_mod == tic6x_mem_mod_minus)
+ require_offset = TRUE;
+ else
+ require_offset = FALSE;
+ scaled = tic6x_offset_none;
+ offset_is_reg = FALSE;
+
+ if (mem_ok && permit_offset)
+ {
+ char endc = 0;
+
+ skip_whitespace (mq);
+ switch (*mq)
+ {
+ case '[':
+ scaled = tic6x_offset_scaled;
+ mq++;
+ endc = ']';
+ break;
+
+ case '(':
+ scaled = tic6x_offset_unscaled;
+ mq++;
+ endc = ')';
+ break;
+
+ default:
+ break;
+ }
+ if (scaled != tic6x_offset_none)
+ {
+ skip_whitespace (mq);
+ if (scaled == tic6x_offset_scaled
+ || (op_forms & TIC6X_OP_MEM_UNREG))
+ {
+ bfd_boolean reg_ok;
+ char *rq = mq;
+
+ reg_ok = tic6x_parse_register (&rq, &offset_reg);
+ if (reg_ok)
+ {
+ skip_whitespace (rq);
+ if (*rq == endc)
+ {
+ mq = rq;
+ offset_is_reg = TRUE;
+ }
+ }
+ }
+ if (!offset_is_reg)
+ {
+ char *save_input_line_pointer;
+
+ save_input_line_pointer = input_line_pointer;
+ input_line_pointer = mq;
+ expression (&offset_exp);
+ mq = input_line_pointer;
+ input_line_pointer = save_input_line_pointer;
+ }
+ skip_whitespace (mq);
+ if (*mq == endc)
+ mq++;
+ else
+ mem_ok = FALSE;
+ }
+ }
+
+ if (mem_ok && require_offset && scaled == tic6x_offset_none)
+ mem_ok = FALSE;
+
+ if (mem_ok)
+ {
+ skip_whitespace (mq);
+ if (!is_end_of_line[(unsigned char) *mq] && *mq != ',')
+ mem_ok = FALSE;
+ }
+
+ if (mem_ok)
+ {
+ op->form = op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG);
+ op->value.mem.base_reg = base_reg;
+ op->value.mem.mod = mem_mod;
+ op->value.mem.scaled = scaled;
+ op->value.mem.offset_is_reg = offset_is_reg;
+ if (offset_is_reg)
+ op->value.mem.offset.reg = offset_reg;
+ else
+ op->value.mem.offset.exp = offset_exp;
+ operand_parsed = TRUE;
+ q = mq;
+ if (base_reg.num >= tic6x_num_registers)
+ as_bad (_("register number %u not supported on this architecture"),
+ base_reg.num);
+ if (offset_is_reg && offset_reg.num >= tic6x_num_registers)
+ as_bad (_("register number %u not supported on this architecture"),
+ offset_reg.num);
+ }
+ }
+
+ /* See if this looks like a register or register pair. */
+ if (!operand_parsed && (op_forms & (TIC6X_OP_REG | TIC6X_OP_REGPAIR)))
+ {
+ tic6x_register first_reg, second_reg;
+ bfd_boolean reg_ok;
+ char *rq = q;
+
+ reg_ok = tic6x_parse_register (&rq, &first_reg);
+
+ if (reg_ok)
+ {
+ if (*rq == ':' && (op_forms & TIC6X_OP_REGPAIR))
+ {
+ rq++;
+ reg_ok = tic6x_parse_register (&rq, &second_reg);
+ if (reg_ok)
+ {
+ skip_whitespace (rq);
+ if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
+ {
+ if ((second_reg.num & 1)
+ || (first_reg.num != second_reg.num + 1)
+ || (first_reg.side != second_reg.side))
+ as_bad (_("register pair for operand %u of '%.*s'"
+ " not a valid even/odd pair"), opno,
+ opc_len, str);
+ op->form = TIC6X_OP_REGPAIR;
+ op->value.reg = second_reg;
+ operand_parsed = TRUE;
+ q = rq;
+ }
+ }
+ }
+ else if (op_forms & TIC6X_OP_REG)
+ {
+ skip_whitespace (rq);
+ if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
+ {
+ op->form = TIC6X_OP_REG;
+ op->value.reg = first_reg;
+ operand_parsed = TRUE;
+ q = rq;
+ }
+ }
+ }
+ if (operand_parsed)
+ {
+ if (first_reg.num >= tic6x_num_registers)
+ as_bad (_("register number %u not supported on this architecture"),
+ first_reg.num);
+ if (op->form == TIC6X_OP_REGPAIR
+ && second_reg.num >= tic6x_num_registers)
+ as_bad (_("register number %u not supported on this architecture"),
+ second_reg.num);
+ }
+ }
+
+ /* Otherwise, parse it as an expression. */
+ if (!operand_parsed && (op_forms & TIC6X_OP_EXP))
+ {
+ char *save_input_line_pointer;
+
+ save_input_line_pointer = input_line_pointer;
+ input_line_pointer = q;
+ op->form = TIC6X_OP_EXP;
+ expression (&op->value.exp);
+ q = input_line_pointer;
+ input_line_pointer = save_input_line_pointer;
+ operand_parsed = TRUE;
+ }
+
+ if (operand_parsed)
+ {
+ /* Now the operand has been parsed, there must be nothing more
+ before the comma or end of line. */
+ skip_whitespace (q);
+ if (!is_end_of_line[(unsigned char) *q] && *q != ',')
+ {
+ operand_parsed = FALSE;
+ as_bad (_("junk after operand %u of '%.*s'"), opno,
+ opc_len, str);
+ while (!is_end_of_line[(unsigned char) *q] && *q != ',')
+ q++;
+ }
+ }
+ else
+ {
+ /* This could not be parsed as any acceptable form of
+ operand. */
+ switch (op_forms)
+ {
+ case TIC6X_OP_REG | TIC6X_OP_REGPAIR:
+ as_bad (_("bad register or register pair for operand %u of '%.*s'"),
+ opno, opc_len, str);
+ break;
+
+ case TIC6X_OP_REG | TIC6X_OP_CTRL:
+ case TIC6X_OP_REG:
+ as_bad (_("bad register for operand %u of '%.*s'"),
+ opno, opc_len, str);
+ break;
+
+ case TIC6X_OP_REGPAIR:
+ as_bad (_("bad register pair for operand %u of '%.*s'"),
+ opno, opc_len, str);
+ break;
+
+ case TIC6X_OP_FUNC_UNIT:
+ as_bad (_("bad functional unit for operand %u of '%.*s'"),
+ opno, opc_len, str);
+ break;
+
+ default:
+ as_bad (_("bad operand %u of '%.*s'"),
+ opno, opc_len, str);
+ break;
+
+ }
+ while (!is_end_of_line[(unsigned char) *q] && *q != ',')
+ q++;
+ }
+ *p = q;
+ return operand_parsed;
+}
+
+/* Table of assembler operators and associated O_* values. */
+typedef struct
+{
+ const char *name;
+ operatorT op;
+} tic6x_operator_table;
+static const tic6x_operator_table tic6x_operators[] = {
+#define O_dsbt_index O_md1
+ { "dsbt_index", O_dsbt_index },
+#define O_got O_md2
+ { "got", O_got },
+#define O_dpr_got O_md3
+ { "dpr_got", O_dpr_got },
+#define O_dpr_byte O_md4
+ { "dpr_byte", O_dpr_byte },
+#define O_dpr_hword O_md5
+ { "dpr_hword", O_dpr_hword },
+#define O_dpr_word O_md6
+ { "dpr_word", O_dpr_word },
+};
+
+/* Parse a name in some machine-specific way. Used on C6X to handle
+ assembler operators. */
+
+int
+tic6x_parse_name (const char *name, expressionS *exprP,
+ enum expr_mode mode ATTRIBUTE_UNUSED, char *nextchar)
+{
+ char *p = input_line_pointer;
+ char c, *name_start, *name_end;
+ const char *inner_name;
+ unsigned int i;
+ operatorT op = O_illegal;
+ symbolS *sym;
+
+ if (*name != '$')
+ return 0;
+
+ for (i = 0; i < ARRAY_SIZE (tic6x_operators); i++)
+ if (strcasecmp (name + 1, tic6x_operators[i].name) == 0)
+ {
+ op = tic6x_operators[i].op;
+ break;
+ }
+
+ if (op == O_illegal)
+ return 0;
+
+ *input_line_pointer = *nextchar;
+ skip_whitespace (p);
+
+ if (*p != '(')
+ {
+ *input_line_pointer = 0;
+ return 0;
+ }
+ p++;
+ skip_whitespace (p);
+
+ if (!is_name_beginner (*p))
+ {
+ *input_line_pointer = 0;
+ return 0;
+ }
+
+ name_start = p;
+ p++;
+ while (is_part_of_name (*p))
+ p++;
+ name_end = p;
+ skip_whitespace (p);
+
+ if (*p != ')')
+ {
+ *input_line_pointer = 0;
+ return 0;
+ }
+
+ input_line_pointer = p + 1;
+ *nextchar = *input_line_pointer;
+ *input_line_pointer = 0;
+
+ c = *name_end;
+ *name_end = 0;
+ inner_name = name_start;
+ if (op == O_dsbt_index && strcmp (inner_name, "__c6xabi_DSBT_BASE") != 0)
+ {
+ as_bad (_("$DSBT_INDEX must be used with __c6xabi_DSBT_BASE"));
+ inner_name = "__c6xabi_DSBT_BASE";
+ }
+ sym = symbol_find_or_make (inner_name);
+ *name_end = c;
+
+ exprP->X_op = op;
+ exprP->X_add_symbol = sym;
+ exprP->X_add_number = 0;
+ exprP->X_op_symbol = NULL;
+ exprP->X_md = 0;
+
+ return 1;
+}
+
+/* Create a fixup for an expression. Same arguments as fix_new_exp,
+ plus FIX_ADDA which is TRUE for ADDA instructions (to indicate that
+ fixes resolving to constants should have those constants implicitly
+ shifted) and FALSE otherwise, but look for C6X-specific expression
+ types and adjust the relocations or give errors accordingly. */
+
+static void
+tic6x_fix_new_exp (fragS *frag, int where, int size, expressionS *exp,
+ int pcrel, bfd_reloc_code_real_type r_type,
+ bfd_boolean fix_adda)
+{
+ bfd_reloc_code_real_type new_reloc = BFD_RELOC_UNUSED;
+ fixS *fix;
+
+ switch (exp->X_op)
+ {
+ case O_dsbt_index:
+ switch (r_type)
+ {
+ case BFD_RELOC_C6000_SBR_U15_W:
+ new_reloc = BFD_RELOC_C6000_DSBT_INDEX;
+ break;
+
+ default:
+ as_bad (_("$DSBT_INDEX not supported in this context"));
+ return;
+ }
+ break;
+
+ case O_got:
+ switch (r_type)
+ {
+ case BFD_RELOC_C6000_SBR_U15_W:
+ new_reloc = BFD_RELOC_C6000_SBR_GOT_U15_W;
+ break;
+
+ default:
+ as_bad (_("$GOT not supported in this context"));
+ return;
+ }
+ break;
+
+ case O_dpr_got:
+ switch (r_type)
+ {
+ case BFD_RELOC_C6000_ABS_L16:
+ new_reloc = BFD_RELOC_C6000_SBR_GOT_L16_W;
+ break;
+
+ case BFD_RELOC_C6000_ABS_H16:
+ new_reloc = BFD_RELOC_C6000_SBR_GOT_H16_W;
+ break;
+
+ default:
+ as_bad (_("$DPR_GOT not supported in this context"));
+ return;
+ }
+ break;
+
+ case O_dpr_byte:
+ switch (r_type)
+ {
+ case BFD_RELOC_C6000_ABS_S16:
+ new_reloc = BFD_RELOC_C6000_SBR_S16;
+ break;
+
+ case BFD_RELOC_C6000_ABS_L16:
+ new_reloc = BFD_RELOC_C6000_SBR_L16_B;
+ break;
+
+ case BFD_RELOC_C6000_ABS_H16:
+ new_reloc = BFD_RELOC_C6000_SBR_H16_B;
+ break;
+
+ default:
+ as_bad (_("$DPR_BYTE not supported in this context"));
+ return;
+ }
+ break;
+
+ case O_dpr_hword:
+ switch (r_type)
+ {
+ case BFD_RELOC_C6000_ABS_L16:
+ new_reloc = BFD_RELOC_C6000_SBR_L16_H;
+ break;
+
+ case BFD_RELOC_C6000_ABS_H16:
+ new_reloc = BFD_RELOC_C6000_SBR_H16_H;
+ break;
+
+ default:
+ as_bad (_("$DPR_HWORD not supported in this context"));
+ return;
+ }
+ break;
+
+ case O_dpr_word:
+ switch (r_type)
+ {
+ case BFD_RELOC_C6000_ABS_L16:
+ new_reloc = BFD_RELOC_C6000_SBR_L16_W;
+ break;
+
+ case BFD_RELOC_C6000_ABS_H16:
+ new_reloc = BFD_RELOC_C6000_SBR_H16_W;
+ break;
+
+ default:
+ as_bad (_("$DPR_WORD not supported in this context"));
+ return;
+ }
+ break;
+
+ case O_symbol:
+ break;
+
+ default:
+ if (pcrel)
+ {
+ as_bad (_("invalid PC-relative operand"));
+ return;
+ }
+ break;
+ }
+
+ if (new_reloc == BFD_RELOC_UNUSED)
+ fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
+ else
+ fix = fix_new (frag, where, size, exp->X_add_symbol, exp->X_add_number,
+ pcrel, new_reloc);
+ fix->tc_fix_data.fix_adda = fix_adda;
+}
+
+/* Generate a fix for a constant (.word etc.). Needed to ensure these
+ go through the error checking in tic6x_fix_new_exp. */
+
+void
+tic6x_cons_fix_new (fragS *frag, int where, int size, expressionS *exp)
+{
+ bfd_reloc_code_real_type r_type;
+
+ switch (size)
+ {
+ case 1:
+ r_type = BFD_RELOC_8;
+ break;
+
+ case 2:
+ r_type = BFD_RELOC_16;
+ break;
+
+ case 4:
+ r_type = BFD_RELOC_32;
+ break;
+
+ default:
+ as_bad (_("no %d-byte relocations available"), size);
+ return;
+ }
+
+ tic6x_fix_new_exp (frag, where, size, exp, 0, r_type, FALSE);
+}
+
+/* Initialize target-specific fix data. */
+
+void
+tic6x_init_fix_data (fixS *fixP)
+{
+ fixP->tc_fix_data.fix_adda = FALSE;
+}
+
+/* Given the fine-grained form of an operand, return the coarse
+ (bit-mask) form. */
+
+static unsigned int
+tic6x_coarse_operand_form (tic6x_operand_form form)
+{
+ switch (form)
+ {
+ case tic6x_operand_asm_const:
+ case tic6x_operand_link_const:
+ return TIC6X_OP_EXP;
+
+ case tic6x_operand_reg:
+ case tic6x_operand_xreg:
+ case tic6x_operand_dreg:
+ case tic6x_operand_areg:
+ case tic6x_operand_retreg:
+ return TIC6X_OP_REG;
+
+ case tic6x_operand_regpair:
+ case tic6x_operand_xregpair:
+ case tic6x_operand_dregpair:
+ return TIC6X_OP_REGPAIR;
+
+ case tic6x_operand_irp:
+ return TIC6X_OP_IRP;
+
+ case tic6x_operand_nrp:
+ return TIC6X_OP_NRP;
+
+ case tic6x_operand_ctrl:
+ return TIC6X_OP_CTRL;
+
+ case tic6x_operand_mem_short:
+ case tic6x_operand_mem_long:
+ case tic6x_operand_mem_deref:
+ return TIC6X_OP_MEM_NOUNREG;
+
+ case tic6x_operand_mem_ndw:
+ return TIC6X_OP_MEM_UNREG;
+
+ case tic6x_operand_func_unit:
+ return TIC6X_OP_FUNC_UNIT;
+
+ default:
+ abort ();
+ }
+}
+
+/* How an operand may match or not match a desired form. If different
+ instruction alternatives fail in different ways, the first failure
+ in this list determines the diagnostic. */
+typedef enum
+ {
+ /* Matches. */
+ tic6x_match_matches,
+ /* Bad coarse form. */
+ tic6x_match_coarse,
+ /* Not constant. */
+ tic6x_match_non_const,
+ /* Register on wrong side. */
+ tic6x_match_wrong_side,
+ /* Not a valid address register. */
+ tic6x_match_bad_address,
+ /* Not a valid return address register. */
+ tic6x_match_bad_return,
+ /* Control register not readable. */
+ tic6x_match_ctrl_write_only,
+ /* Control register not writable. */
+ tic6x_match_ctrl_read_only,
+ /* Not a valid memory reference for this instruction. */
+ tic6x_match_bad_mem
+ } tic6x_operand_match;
+
+/* Return whether an operand matches the given fine-grained form and
+ read/write usage, and, if it does not match, how it fails to match.
+ The main functional unit side is SIDE; the cross-path side is CROSS
+ (the same as SIDE if a cross path not used); the data side is
+ DATA_SIDE. */
+static tic6x_operand_match
+tic6x_operand_matches_form (const tic6x_operand *op, tic6x_operand_form form,
+ tic6x_rw rw, unsigned int side, unsigned int cross,
+ unsigned int data_side)
+{
+ unsigned int coarse = tic6x_coarse_operand_form (form);
+
+ if (coarse != op->form)
+ return tic6x_match_coarse;
+
+ switch (form)
+ {
+ case tic6x_operand_asm_const:
+ if (op->value.exp.X_op == O_constant)
+ return tic6x_match_matches;
+ else
+ return tic6x_match_non_const;
+
+ case tic6x_operand_link_const:
+ case tic6x_operand_irp:
+ case tic6x_operand_nrp:
+ case tic6x_operand_func_unit:
+ /* All expressions are link-time constants, although there may
+ not be relocations to express them in the output file. "irp"
+ and "nrp" are unique operand values. All parsed functional
+ unit names are valid. */
+ return tic6x_match_matches;
+
+ case tic6x_operand_reg:
+ case tic6x_operand_regpair:
+ if (op->value.reg.side == side)
+ return tic6x_match_matches;
+ else
+ return tic6x_match_wrong_side;
+
+ case tic6x_operand_xreg:
+ case tic6x_operand_xregpair:
+ if (op->value.reg.side == cross)
+ return tic6x_match_matches;
+ else
+ return tic6x_match_wrong_side;
+
+ case tic6x_operand_dreg:
+ case tic6x_operand_dregpair:
+ if (op->value.reg.side == data_side)
+ return tic6x_match_matches;
+ else
+ return tic6x_match_wrong_side;
+
+ case tic6x_operand_areg:
+ if (op->value.reg.side != cross)
+ return tic6x_match_wrong_side;
+ else if (op->value.reg.side == 2
+ && (op->value.reg.num == 14 || op->value.reg.num == 15))
+ return tic6x_match_matches;
+ else
+ return tic6x_match_bad_address;
+
+ case tic6x_operand_retreg:
+ if (op->value.reg.side != side)
+ return tic6x_match_wrong_side;
+ else if (op->value.reg.num != 3)
+ return tic6x_match_bad_return;
+ else
+ return tic6x_match_matches;
+
+ case tic6x_operand_ctrl:
+ switch (rw)
+ {
+ case tic6x_rw_read:
+ if (tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read
+ || tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read_write)
+ return tic6x_match_matches;
+ else
+ return tic6x_match_ctrl_write_only;
+
+ case tic6x_rw_write:
+ if (tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_write
+ || tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read_write)
+ return tic6x_match_matches;
+ else
+ return tic6x_match_ctrl_read_only;
+
+ default:
+ abort ();
+ }
+
+ case tic6x_operand_mem_deref:
+ if (op->value.mem.mod != tic6x_mem_mod_none)
+ return tic6x_match_bad_mem;
+ else if (op->value.mem.scaled != tic6x_offset_none)
+ abort ();
+ else if (op->value.mem.base_reg.side != side)
+ return tic6x_match_bad_mem;
+ else
+ return tic6x_match_matches;
+
+ case tic6x_operand_mem_short:
+ case tic6x_operand_mem_ndw:
+ if (op->value.mem.base_reg.side != side)
+ return tic6x_match_bad_mem;
+ if (op->value.mem.mod == tic6x_mem_mod_none)
+ {
+ if (op->value.mem.scaled != tic6x_offset_none)
+ abort ();
+ return tic6x_match_matches;
+ }
+ if (op->value.mem.scaled == tic6x_offset_none)
+ {
+ if (op->value.mem.mod == tic6x_mem_mod_plus
+ || op->value.mem.mod == tic6x_mem_mod_minus)
+ abort ();
+ return tic6x_match_matches;
+ }
+ if (op->value.mem.offset_is_reg)
+ {
+ if (op->value.mem.scaled == tic6x_offset_unscaled
+ && form != tic6x_operand_mem_ndw)
+ abort ();
+ if (op->value.mem.offset.reg.side == side)
+ return tic6x_match_matches;
+ else
+ return tic6x_match_bad_mem;
+ }
+ else
+ {
+ if (op->value.mem.offset.exp.X_op == O_constant)
+ return tic6x_match_matches;
+ else
+ return tic6x_match_bad_mem;
+ }
+
+ case tic6x_operand_mem_long:
+ if (op->value.mem.base_reg.side == 2
+ && (op->value.mem.base_reg.num == 14
+ || op->value.mem.base_reg.num == 15))
+ {
+ switch (op->value.mem.mod)
+ {
+ case tic6x_mem_mod_none:
+ if (op->value.mem.scaled != tic6x_offset_none)
+ abort ();
+ return tic6x_match_matches;
+
+ case tic6x_mem_mod_plus:
+ if (op->value.mem.scaled == tic6x_offset_none)
+ abort ();
+ if (op->value.mem.offset_is_reg)
+ return tic6x_match_bad_mem;
+ else if (op->value.mem.scaled == tic6x_offset_scaled
+ && op->value.mem.offset.exp.X_op != O_constant)
+ return tic6x_match_bad_mem;
+ else
+ return tic6x_match_matches;
+
+ case tic6x_mem_mod_minus:
+ case tic6x_mem_mod_preinc:
+ case tic6x_mem_mod_predec:
+ case tic6x_mem_mod_postinc:
+ case tic6x_mem_mod_postdec:
+ return tic6x_match_bad_mem;
+
+ default:
+ abort ();
+ }
+
+ }
+ else
+ return tic6x_match_bad_mem;
+
+ default:
+ abort ();
+ }
+}
+
+/* Return the number of bits shift used with DP-relative coding method
+ CODING. */
+
+static unsigned int
+tic6x_dpr_shift (tic6x_coding_method coding)
+{
+ switch (coding)
+ {
+ case tic6x_coding_ulcst_dpr_byte:
+ return 0;
+
+ case tic6x_coding_ulcst_dpr_half:
+ return 1;
+
+ case tic6x_coding_ulcst_dpr_word:
+ return 2;
+
+ default:
+ abort ();
+ }
+}
+
+/* Return the relocation used with DP-relative coding method
+ CODING. */
+
+static bfd_reloc_code_real_type
+tic6x_dpr_reloc (tic6x_coding_method coding)
+{
+ switch (coding)
+ {
+ case tic6x_coding_ulcst_dpr_byte:
+ return BFD_RELOC_C6000_SBR_U15_B;
+
+ case tic6x_coding_ulcst_dpr_half:
+ return BFD_RELOC_C6000_SBR_U15_H;
+
+ case tic6x_coding_ulcst_dpr_word:
+ return BFD_RELOC_C6000_SBR_U15_W;
+
+ default:
+ abort ();
+ }
+}
+
+/* Given a memory reference *MEM_REF as originally parsed, fill in
+ defaults for missing offsets. */
+
+static void
+tic6x_default_mem_ref (tic6x_mem_ref *mem_ref)
+{
+ switch (mem_ref->mod)
+ {
+ case tic6x_mem_mod_none:
+ if (mem_ref->scaled != tic6x_offset_none)
+ abort ();
+ mem_ref->mod = tic6x_mem_mod_plus;
+ mem_ref->scaled = tic6x_offset_unscaled;
+ mem_ref->offset_is_reg = FALSE;
+ memset (&mem_ref->offset.exp, 0, sizeof mem_ref->offset.exp);
+ mem_ref->offset.exp.X_op = O_constant;
+ mem_ref->offset.exp.X_add_number = 0;
+ mem_ref->offset.exp.X_unsigned = 0;
+ break;
+
+ case tic6x_mem_mod_plus:
+ case tic6x_mem_mod_minus:
+ if (mem_ref->scaled == tic6x_offset_none)
+ abort ();
+ break;
+
+ case tic6x_mem_mod_preinc:
+ case tic6x_mem_mod_predec:
+ case tic6x_mem_mod_postinc:
+ case tic6x_mem_mod_postdec:
+ if (mem_ref->scaled != tic6x_offset_none)
+ break;
+ mem_ref->scaled = tic6x_offset_scaled;
+ mem_ref->offset_is_reg = FALSE;
+ memset (&mem_ref->offset.exp, 0, sizeof mem_ref->offset.exp);
+ mem_ref->offset.exp.X_op = O_constant;
+ mem_ref->offset.exp.X_add_number = 1;
+ mem_ref->offset.exp.X_unsigned = 0;
+ break;
+
+ default:
+ abort ();
+ }
+}
+
+/* Return the encoding in the 8-bit field of an SPMASK or SPMASKR
+ instruction of the specified UNIT, side SIDE. */
+
+static unsigned int
+tic6x_encode_spmask (tic6x_func_unit_base unit, unsigned int side)
+{
+ switch (unit)
+ {
+ case tic6x_func_unit_l:
+ return 1 << (side - 1);
+
+ case tic6x_func_unit_s:
+ return 1 << (side + 1);
+
+ case tic6x_func_unit_d:
+ return 1 << (side + 3);
+
+ case tic6x_func_unit_m:
+ return 1 << (side + 5);
+
+ default:
+ abort ();
+ }
+}
+
+/* Try to encode the instruction with opcode number ID and operands
+ OPERANDS (number NUM_OPERANDS), creg value THIS_LINE_CREG and z
+ value THIS_LINE_Z; FUNC_UNIT_SIDE, FUNC_UNIT_CROSS and
+ FUNC_UNIT_DATA_SIDE describe the functional unit specification;
+ SPLOOP_II is the ii value from the previous SPLOOP-family
+ instruction, or 0 if not in such a loop; the only possible problems
+ are operands being out of range (they already match the
+ fine-grained form), and inappropriate predication. If this
+ succeeds, return the encoding and set *OK to TRUE; otherwise return
+ 0 and set *OK to FALSE. If a fix is needed, set *FIX_NEEDED to
+ true and fill in *FIX_EXP, *FIX_PCREL, *FX_R_TYPE and *FIX_ADDA.
+ Print error messages for failure if PRINT_ERRORS is TRUE; the
+ opcode starts at STR and has length OPC_LEN. */
+
+static unsigned int
+tic6x_try_encode (tic6x_opcode_id id, tic6x_operand *operands,
+ unsigned int num_operands, unsigned int this_line_creg,
+ unsigned int this_line_z, unsigned int func_unit_side,
+ unsigned int func_unit_cross,
+ unsigned int func_unit_data_side, int sploop_ii,
+ expressionS **fix_exp, int *fix_pcrel,
+ bfd_reloc_code_real_type *fx_r_type, bfd_boolean *fix_adda,
+ bfd_boolean *fix_needed, bfd_boolean *ok,
+ bfd_boolean print_errors, char *str, int opc_len)
+{
+ const tic6x_opcode *opct;
+ const tic6x_insn_format *fmt;
+ unsigned int opcode_value;
+ unsigned int fld;
+
+ opct = &tic6x_opcode_table[id];
+ fmt = &tic6x_insn_format_table[opct->format];
+ opcode_value = fmt->cst_bits;
+
+ for (fld = 0; fld < opct->num_fixed_fields; fld++)
+ {
+ if (opct->fixed_fields[fld].min_val == opct->fixed_fields[fld].max_val)
+ {
+ const tic6x_insn_field *fldd;
+ fldd = tic6x_field_from_fmt (fmt, opct->fixed_fields[fld].field_id);
+ if (fldd == NULL)
+ abort ();
+ opcode_value |= opct->fixed_fields[fld].min_val << fldd->low_pos;
+ }
+ }
+
+ for (fld = 0; fld < opct->num_variable_fields; fld++)
+ {
+ const tic6x_insn_field *fldd;
+ unsigned int value;
+ unsigned int opno;
+ unsigned int ffld;
+ offsetT sign_value;
+ unsigned int bits;
+ unsigned int fcyc_bits;
+ expressionS *expp;
+ expressionS ucexp;
+ tic6x_mem_ref mem;
+
+ fldd = tic6x_field_from_fmt (fmt, opct->variable_fields[fld].field_id);
+ if (fldd == NULL)
+ abort ();
+ opno = opct->variable_fields[fld].operand_num;
+ switch (opct->variable_fields[fld].coding_method)
+ {
+ case tic6x_coding_ucst:
+ if (operands[opno].form != TIC6X_OP_EXP)
+ abort ();
+ if (operands[opno].value.exp.X_op != O_constant)
+ abort ();
+ ucexp = operands[opno].value.exp;
+ unsigned_constant:
+ if (ucexp.X_add_number < 0
+ || ucexp.X_add_number >= (1 << fldd->width))
+ {
+ if (print_errors)
+ as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
+ opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ value = ucexp.X_add_number;
+ break;
+
+ case tic6x_coding_scst:
+ if (operands[opno].form != TIC6X_OP_EXP)
+ abort ();
+ if (operands[opno].value.exp.X_op != O_constant)
+ {
+ value = 0;
+ /* Opcode table should not permit non-constants without
+ a known relocation for them. */
+ if (fldd->low_pos != 7 || fldd->width != 16)
+ abort ();
+ *fix_needed = TRUE;
+ *fix_exp = &operands[opno].value.exp;
+ *fix_pcrel = 0;
+ *fx_r_type = BFD_RELOC_C6000_ABS_S16;
+ *fix_adda = FALSE;
+ break;
+ }
+ sign_value = SEXT (operands[opno].value.exp.X_add_number);
+ signed_constant:
+ if (sign_value < -(1 << (fldd->width - 1))
+ || (sign_value >= (1 << (fldd->width - 1))))
+ {
+ if (print_errors)
+ as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
+ opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ value = sign_value + (1 << (fldd->width - 1));
+ value ^= (1 << (fldd->width - 1));
+ break;
+
+ case tic6x_coding_ucst_minus_one:
+ if (operands[opno].form != TIC6X_OP_EXP)
+ abort ();
+ if (operands[opno].value.exp.X_op != O_constant)
+ abort ();
+ if (operands[opno].value.exp.X_add_number <= 0
+ || operands[opno].value.exp.X_add_number > (1 << fldd->width))
+ {
+ if (print_errors)
+ as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
+ opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ value = operands[opno].value.exp.X_add_number - 1;
+ break;
+
+ case tic6x_coding_scst_negate:
+ if (operands[opno].form != TIC6X_OP_EXP)
+ abort ();
+ if (operands[opno].value.exp.X_op != O_constant)
+ abort ();
+ sign_value = SEXT (-operands[opno].value.exp.X_add_number);
+ goto signed_constant;
+
+ case tic6x_coding_ulcst_dpr_byte:
+ case tic6x_coding_ulcst_dpr_half:
+ case tic6x_coding_ulcst_dpr_word:
+ bits = tic6x_dpr_shift (opct->variable_fields[fld].coding_method);
+ switch (operands[opno].form)
+ {
+ case TIC6X_OP_EXP:
+ if (operands[opno].value.exp.X_op == O_constant)
+ {
+ ucexp = operands[opno].value.exp;
+ goto unsigned_constant;
+ }
+ expp = &operands[opno].value.exp;
+ break;
+
+ case TIC6X_OP_MEM_NOUNREG:
+ mem = operands[opno].value.mem;
+ tic6x_default_mem_ref (&mem);
+ if (mem.offset_is_reg)
+ abort ();
+ if (mem.offset.exp.X_op == O_constant)
+ {
+ ucexp = mem.offset.exp;
+ if (mem.scaled == tic6x_offset_unscaled)
+ {
+ if (ucexp.X_add_number & ((1 << bits) - 1))
+ {
+ if (print_errors)
+ as_bad (_("offset in operand %u of '%.*s' not "
+ "divisible by %u"), opno + 1, opc_len,
+ str, 1u << bits);
+ *ok = FALSE;
+ return 0;
+ }
+ ucexp.X_add_number >>= bits;
+ }
+ goto unsigned_constant;
+ }
+ if (mem.scaled != tic6x_offset_unscaled)
+ abort ();
+ if (operands[opno].value.mem.mod == tic6x_mem_mod_none
+ || operands[opno].value.mem.scaled != tic6x_offset_unscaled
+ || operands[opno].value.mem.offset_is_reg)
+ abort ();
+ expp = &operands[opno].value.mem.offset.exp;
+ break;
+
+ default:
+ abort ();
+ }
+ value = 0;
+ /* Opcode table should not use this encoding without a known
+ relocation. */
+ if (fldd->low_pos != 8 || fldd->width != 15)
+ abort ();
+ /* We do not check for offset divisibility here; such a
+ check is not needed at this point to encode the value,
+ and if there is eventually a problem it will be detected
+ either in md_apply_fix or at link time. */
+ *fix_needed = TRUE;
+ *fix_exp = expp;
+ *fix_pcrel = 0;
+ *fx_r_type
+ = tic6x_dpr_reloc (opct->variable_fields[fld].coding_method);
+ if (operands[opno].form == TIC6X_OP_EXP)
+ *fix_adda = TRUE;
+ else
+ *fix_adda = FALSE;
+ break;
+
+ case tic6x_coding_lcst_low16:
+ if (operands[opno].form != TIC6X_OP_EXP)
+ abort ();
+ if (operands[opno].value.exp.X_op == O_constant)
+ value = operands[opno].value.exp.X_add_number & 0xffff;
+ else
+ {
+ value = 0;
+ /* Opcode table should not use this encoding without a
+ known relocation. */
+ if (fldd->low_pos != 7 || fldd->width != 16)
+ abort ();
+ *fix_needed = TRUE;
+ *fix_exp = &operands[opno].value.exp;
+ *fix_pcrel = 0;
+ *fx_r_type = BFD_RELOC_C6000_ABS_L16;
+ *fix_adda = FALSE;
+ }
+ break;
+
+ case tic6x_coding_lcst_high16:
+ if (operands[opno].form != TIC6X_OP_EXP)
+ abort ();
+ if (operands[opno].value.exp.X_op == O_constant)
+ value = (operands[opno].value.exp.X_add_number >> 16) & 0xffff;
+ else
+ {
+ value = 0;
+ /* Opcode table should not use this encoding without a
+ known relocation. */
+ if (fldd->low_pos != 7 || fldd->width != 16)
+ abort ();
+ *fix_needed = TRUE;
+ *fix_exp = &operands[opno].value.exp;
+ *fix_pcrel = 0;
+ *fx_r_type = BFD_RELOC_C6000_ABS_H16;
+ *fix_adda = FALSE;
+ }
+ break;
+
+ case tic6x_coding_pcrel:
+ case tic6x_coding_pcrel_half:
+ if (operands[opno].form != TIC6X_OP_EXP)
+ abort ();
+ value = 0;
+ *fix_needed = TRUE;
+ *fix_exp = &operands[opno].value.exp;
+ *fix_pcrel = 1;
+ if (fldd->low_pos == 7 && fldd->width == 21)
+ *fx_r_type = BFD_RELOC_C6000_PCR_S21;
+ else if (fldd->low_pos == 16 && fldd->width == 12)
+ *fx_r_type = BFD_RELOC_C6000_PCR_S12;
+ else if (fldd->low_pos == 13 && fldd->width == 10)
+ *fx_r_type = BFD_RELOC_C6000_PCR_S10;
+ else if (fldd->low_pos == 16 && fldd->width == 7)
+ *fx_r_type = BFD_RELOC_C6000_PCR_S7;
+ else
+ /* Opcode table should not use this encoding without a
+ known relocation. */
+ abort ();
+ *fix_adda = FALSE;
+ break;
+
+ case tic6x_coding_reg:
+ switch (operands[opno].form)
+ {
+ case TIC6X_OP_REG:
+ case TIC6X_OP_REGPAIR:
+ value = operands[opno].value.reg.num;
+ break;
+
+ case TIC6X_OP_MEM_NOUNREG:
+ case TIC6X_OP_MEM_UNREG:
+ value = operands[opno].value.mem.base_reg.num;
+ break;
+
+ default:
+ abort ();
+ }
+ break;
+
+ case tic6x_coding_areg:
+ switch (operands[opno].form)
+ {
+ case TIC6X_OP_REG:
+ value = (operands[opno].value.reg.num == 15 ? 1 : 0);
+ break;
+
+ case TIC6X_OP_MEM_NOUNREG:
+ value = (operands[opno].value.mem.base_reg.num == 15 ? 1 : 0);
+ break;
+
+ default:
+ abort ();
+ }
+ break;
+
+ case tic6x_coding_crlo:
+ if (operands[opno].form != TIC6X_OP_CTRL)
+ abort ();
+ value = tic6x_ctrl_table[operands[opno].value.ctrl].crlo;
+ break;
+
+ case tic6x_coding_crhi:
+ if (operands[opno].form != TIC6X_OP_CTRL)
+ abort ();
+ value = 0;
+ break;
+
+ case tic6x_coding_reg_shift:
+ if (operands[opno].form != TIC6X_OP_REGPAIR)
+ abort ();
+ value = operands[opno].value.reg.num >> 1;
+ break;
+
+ case tic6x_coding_mem_offset:
+ if (operands[opno].form != TIC6X_OP_MEM_NOUNREG)
+ abort ();
+ mem = operands[opno].value.mem;
+ tic6x_default_mem_ref (&mem);
+ if (mem.offset_is_reg)
+ {
+ if (mem.scaled != tic6x_offset_scaled)
+ abort ();
+ value = mem.offset.reg.num;
+ }
+ else
+ {
+ int scale;
+
+ if (mem.offset.exp.X_op != O_constant)
+ abort ();
+ switch (mem.scaled)
+ {
+ case tic6x_offset_scaled:
+ scale = 1;
+ break;
+
+ case tic6x_offset_unscaled:
+ scale = opct->operand_info[opno].size;
+ if (scale != 1 && scale != 2 && scale != 4 && scale != 8)
+ abort ();
+ break;
+
+ default:
+ abort ();
+ }
+ if (mem.offset.exp.X_add_number < 0
+ || mem.offset.exp.X_add_number >= (1 << fldd->width) * scale)
+ {
+ if (print_errors)
+ as_bad (_("offset in operand %u of '%.*s' out of range"),
+ opno + 1, opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ if (mem.offset.exp.X_add_number % scale)
+ {
+ if (print_errors)
+ as_bad (_("offset in operand %u of '%.*s' not "
+ "divisible by %u"),
+ opno + 1, opc_len, str, scale);
+ *ok = FALSE;
+ return 0;
+ }
+ value = mem.offset.exp.X_add_number / scale;
+ }
+ break;
+
+ case tic6x_coding_mem_offset_noscale:
+ if (operands[opno].form != TIC6X_OP_MEM_UNREG)
+ abort ();
+ mem = operands[opno].value.mem;
+ tic6x_default_mem_ref (&mem);
+ if (mem.offset_is_reg)
+ value = mem.offset.reg.num;
+ else
+ {
+ if (mem.offset.exp.X_op != O_constant)
+ abort ();
+ if (mem.offset.exp.X_add_number < 0
+ || mem.offset.exp.X_add_number >= (1 << fldd->width))
+ {
+ if (print_errors)
+ as_bad (_("offset in operand %u of '%.*s' out of range"),
+ opno + 1, opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ value = mem.offset.exp.X_add_number;
+ }
+ break;
+
+ case tic6x_coding_mem_mode:
+ if (operands[opno].form != TIC6X_OP_MEM_NOUNREG
+ && operands[opno].form != TIC6X_OP_MEM_UNREG)
+ abort ();
+ mem = operands[opno].value.mem;
+ tic6x_default_mem_ref (&mem);
+ switch (mem.mod)
+ {
+ case tic6x_mem_mod_plus:
+ value = 1;
+ break;
+
+ case tic6x_mem_mod_minus:
+ value = 0;
+ break;
+
+ case tic6x_mem_mod_preinc:
+ value = 9;
+ break;
+
+ case tic6x_mem_mod_predec:
+ value = 8;
+ break;
+
+ case tic6x_mem_mod_postinc:
+ value = 11;
+ break;
+
+ case tic6x_mem_mod_postdec:
+ value = 10;
+ break;
+
+ default:
+ abort ();
+ }
+ value += (mem.offset_is_reg ? 4 : 0);
+ break;
+
+ case tic6x_coding_scaled:
+ if (operands[opno].form != TIC6X_OP_MEM_UNREG)
+ abort ();
+ mem = operands[opno].value.mem;
+ tic6x_default_mem_ref (&mem);
+ switch (mem.scaled)
+ {
+ case tic6x_offset_unscaled:
+ value = 0;
+ break;
+
+ case tic6x_offset_scaled:
+ value = 1;
+ break;
+
+ default:
+ abort ();
+ }
+ break;
+
+ case tic6x_coding_spmask:
+ /* The position of such a field is hardcoded in the handling
+ of "||^". */
+ if (fldd->low_pos != 18)
+ abort ();
+ value = 0;
+ for (opno = 0; opno < num_operands; opno++)
+ {
+ unsigned int v;
+
+ v = tic6x_encode_spmask (operands[opno].value.func_unit.base,
+ operands[opno].value.func_unit.side);
+ if (value & v)
+ {
+ if (print_errors)
+ as_bad (_("functional unit already masked for operand "
+ "%u of '%.*s'"), opno + 1, opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ value |= v;
+ }
+ break;
+
+ case tic6x_coding_reg_unused:
+ /* This is a placeholder; correct handling goes along with
+ resource constraint checks. */
+ value = 0;
+ break;
+
+ case tic6x_coding_fstg:
+ case tic6x_coding_fcyc:
+ if (operands[opno].form != TIC6X_OP_EXP)
+ abort ();
+ if (operands[opno].value.exp.X_op != O_constant)
+ abort ();
+ if (!sploop_ii)
+ {
+ if (print_errors)
+ as_bad (_("'%.*s' instruction not in a software "
+ "pipelined loop"),
+ opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+
+ if (sploop_ii <= 1)
+ fcyc_bits = 0;
+ else if (sploop_ii <= 2)
+ fcyc_bits = 1;
+ else if (sploop_ii <= 4)
+ fcyc_bits = 2;
+ else if (sploop_ii <= 8)
+ fcyc_bits = 3;
+ else if (sploop_ii <= 14)
+ fcyc_bits = 4;
+ else
+ abort ();
+ if (fcyc_bits > fldd->width)
+ abort ();
+
+ if (opct->variable_fields[fld].coding_method == tic6x_coding_fstg)
+ {
+ if (operands[opno].value.exp.X_add_number < 0
+ || (operands[opno].value.exp.X_add_number
+ >= (1 << (fldd->width - fcyc_bits))))
+ {
+ if (print_errors)
+ as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
+ opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ value = operands[opno].value.exp.X_add_number << fcyc_bits;
+ }
+ else
+ {
+ if (operands[opno].value.exp.X_add_number < 0
+ || (operands[opno].value.exp.X_add_number >= sploop_ii))
+ {
+ if (print_errors)
+ as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
+ opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ value = operands[opno].value.exp.X_add_number;
+ }
+ break;
+
+ case tic6x_coding_fu:
+ value = func_unit_side == 2 ? 1 : 0;
+ break;
+
+ case tic6x_coding_data_fu:
+ value = func_unit_data_side == 2 ? 1 : 0;
+ break;
+
+ case tic6x_coding_xpath:
+ value = func_unit_cross;
+ break;
+
+ default:
+ abort ();
+ }
+
+ for (ffld = 0; ffld < opct->num_fixed_fields; ffld++)
+ if ((opct->fixed_fields[ffld].field_id
+ == opct->variable_fields[fld].field_id)
+ && (value < opct->fixed_fields[ffld].min_val
+ || value > opct->fixed_fields[ffld].max_val))
+ {
+ if (print_errors)
+ as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
+ opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+
+ opcode_value |= value << fldd->low_pos;
+ }
+
+ if (this_line_creg)
+ {
+ const tic6x_insn_field *creg;
+ const tic6x_insn_field *z;
+
+ creg = tic6x_field_from_fmt (fmt, tic6x_field_creg);
+ if (creg == NULL)
+ {
+ if (print_errors)
+ as_bad (_("instruction '%.*s' cannot be predicated"),
+ opc_len, str);
+ *ok = FALSE;
+ return 0;
+ }
+ z = tic6x_field_from_fmt (fmt, tic6x_field_z);
+ /* If there is a creg field, there must be a z field; otherwise
+ there is an error in the format table. */
+ if (z == NULL)
+ abort ();
+
+ opcode_value |= this_line_creg << creg->low_pos;
+ opcode_value |= this_line_z << z->low_pos;
+ }
+
+ *ok = TRUE;
+ return opcode_value;
+}
+
+/* Convert the target integer stored in N bytes in BUF to a host
+ integer, returning that value. */
+
+static valueT
+md_chars_to_number (char *buf, int n)
+{
+ valueT result = 0;
+ unsigned char *p = (unsigned char *) buf;
+
+ if (target_big_endian)
+ {
+ while (n--)
+ {
+ result <<= 8;
+ result |= (*p++ & 0xff);
+ }
+ }
+ else
+ {
+ while (n--)
+ {
+ result <<= 8;
+ result |= (p[n] & 0xff);
+ }
+ }
+
+ return result;
+}
+
+/* Assemble the instruction starting at STR (an opcode, with the
+ opcode name all-lowercase). */
+
+void
+md_assemble (char *str)
+{
+ char *p;
+ int opc_len;
+ bfd_boolean this_line_parallel;
+ bfd_boolean this_line_spmask;
+ unsigned int this_line_creg;
+ unsigned int this_line_z;
+ bfd_boolean this_insn_label;
+ segment_info_type *seginfo;
+ tic6x_opcode_list *opc_list, *opc;
+ tic6x_func_unit_base func_unit_base = tic6x_func_unit_nfu;
+ unsigned int func_unit_side = 0;
+ unsigned int func_unit_cross = 0;
+ unsigned int cross_side = 0;
+ unsigned int func_unit_data_side = 0;
+ unsigned int max_matching_opcodes, num_matching_opcodes;
+ tic6x_opcode_id *opcm = NULL;
+ unsigned int opc_rank[TIC6X_NUM_PREFER];
+ const tic6x_opcode *opct = NULL;
+ int min_rank, try_rank, max_rank;
+ bfd_boolean num_operands_permitted[TIC6X_MAX_SOURCE_OPERANDS + 1]
+ = { FALSE };
+ unsigned int operand_forms[TIC6X_MAX_SOURCE_OPERANDS] = { 0 };
+ tic6x_operand operands[TIC6X_MAX_SOURCE_OPERANDS];
+ unsigned int max_num_operands;
+ unsigned int num_operands_read;
+ bfd_boolean ok_this_arch, ok_this_fu, ok_this_arch_fu;
+ bfd_boolean bad_operands = FALSE;
+ unsigned int opcode_value;
+ bfd_boolean encoded_ok;
+ bfd_boolean fix_needed = FALSE;
+ expressionS *fix_exp = NULL;
+ int fix_pcrel = 0;
+ bfd_reloc_code_real_type fx_r_type = BFD_RELOC_UNUSED;
+ bfd_boolean fix_adda = FALSE;
+ char *output;
+
+ p = str;
+ while (*p && !is_end_of_line[(unsigned char) *p] && *p != ' ')
+ p++;
+
+ /* This function should only have been called when there is actually
+ an instruction to assemble. */
+ if (p == str)
+ abort ();
+
+ /* Reset global settings for parallel bars and predicates now to
+ avoid extra errors if there are problems with this opcode. */
+ this_line_parallel = tic6x_line_parallel;
+ this_line_spmask = tic6x_line_spmask;
+ this_line_creg = tic6x_line_creg;
+ this_line_z = tic6x_line_z;
+ tic6x_line_parallel = FALSE;
+ tic6x_line_spmask = FALSE;
+ tic6x_line_creg = 0;
+ tic6x_line_z = 0;
+ seginfo = seg_info (now_seg);
+ this_insn_label = seginfo->tc_segment_info_data.seen_label;
+ seginfo->tc_segment_info_data.seen_label = FALSE;
+
+ opc_list = hash_find_n (opcode_hash, str, p - str);
+ if (opc_list == NULL)
+ {
+ char c = *p;
+ *p = 0;
+ as_bad (_("unknown opcode '%s'"), str);
+ *p = c;
+ return;
+ }
+
+ opc_len = p - str;
+ skip_whitespace (p);
+
+ /* See if there is something that looks like a functional unit
+ specifier. */
+ if (*p == '.')
+ {
+ bfd_boolean good_func_unit;
+ tic6x_func_unit_base maybe_base = tic6x_func_unit_nfu;
+ unsigned int maybe_side = 0;
+ unsigned int maybe_cross = 0;
+ unsigned int maybe_data_side = 0;
+
+ good_func_unit = tic6x_parse_func_unit_base (p + 1, &maybe_base,
+ &maybe_side);
+
+ if (good_func_unit)
+ {
+ if (p[3] == ' ' || is_end_of_line[(unsigned char) p[3]])
+ p += 3;
+ else if ((p[3] == 'x' || p[3] == 'X')
+ && (p[4] == ' ' || is_end_of_line[(unsigned char) p[4]]))
+ {
+ maybe_cross = 1;
+ p += 4;
+ }
+ else if (maybe_base == tic6x_func_unit_d
+ && (p[3] == 't' || p[3] == 'T')
+ && (p[4] == '1' || p[4] == '2')
+ && (p[5] == ' ' || is_end_of_line[(unsigned char) p[5]]))
+ {
+ maybe_data_side = p[4] - '0';
+ p += 5;
+ }
+ else
+ good_func_unit = FALSE;
+ }
+
+ if (good_func_unit)
+ {
+ func_unit_base = maybe_base;
+ func_unit_side = maybe_side;
+ func_unit_cross = maybe_cross;
+ cross_side = (func_unit_cross ? 3 - func_unit_side : func_unit_side);
+ func_unit_data_side = maybe_data_side;
+ }
+
+ skip_whitespace (p);
+ }
+
+ /* Determine which entries in the opcode table match, and the
+ associated permitted forms of operands. */
+ max_matching_opcodes = 0;
+ for (opc = opc_list; opc; opc = opc->next)
+ max_matching_opcodes++;
+ num_matching_opcodes = 0;
+ opcm = xmalloc (max_matching_opcodes * sizeof (*opcm));
+ max_num_operands = 0;
+ ok_this_arch = FALSE;
+ ok_this_fu = FALSE;
+ ok_this_arch_fu = FALSE;
+ for (opc = opc_list; opc; opc = opc->next)
+ {
+ unsigned int num_operands;
+ unsigned int i;
+ bfd_boolean this_opc_arch_ok = TRUE;
+ bfd_boolean this_opc_fu_ok = TRUE;
+
+ if (tic6x_insn_format_table[tic6x_opcode_table[opc->id].format].num_bits
+ != 32)
+ continue;
+ if (!(tic6x_opcode_table[opc->id].isa_variants & tic6x_features))
+ this_opc_arch_ok = FALSE;
+ if (tic6x_opcode_table[opc->id].func_unit != func_unit_base)
+ this_opc_fu_ok = FALSE;
+ if (func_unit_side == 1
+ && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SIDE_B_ONLY))
+ this_opc_fu_ok = FALSE;
+ if (func_unit_cross
+ && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_NO_CROSS))
+ this_opc_fu_ok = FALSE;
+ if (!func_unit_data_side
+ && (tic6x_opcode_table[opc->id].flags
+ & (TIC6X_FLAG_LOAD | TIC6X_FLAG_STORE)))
+ this_opc_fu_ok = FALSE;
+ if (func_unit_data_side
+ && !(tic6x_opcode_table[opc->id].flags
+ & (TIC6X_FLAG_LOAD | TIC6X_FLAG_STORE)))
+ this_opc_fu_ok = FALSE;
+ if (func_unit_data_side == 1
+ && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SIDE_T2_ONLY))
+ this_opc_fu_ok = FALSE;
+ if (this_opc_arch_ok)
+ ok_this_arch = TRUE;
+ if (this_opc_fu_ok)
+ ok_this_fu = TRUE;
+ if (!this_opc_arch_ok || !this_opc_fu_ok)
+ continue;
+ ok_this_arch_fu = TRUE;
+ opcm[num_matching_opcodes] = opc->id;
+ num_matching_opcodes++;
+ num_operands = tic6x_opcode_table[opc->id].num_operands;
+
+ if (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SPMASK)
+ {
+ if (num_operands != 1
+ || (tic6x_opcode_table[opc->id].operand_info[0].form
+ != tic6x_operand_func_unit))
+ abort ();
+ num_operands = 8;
+ for (i = 0; i < num_operands; i++)
+ {
+ operand_forms[i]
+ |= tic6x_coarse_operand_form (tic6x_operand_func_unit);
+ num_operands_permitted[i] = TRUE;
+ }
+ }
+ else
+ {
+ for (i = 0; i < num_operands; i++)
+ {
+ tic6x_operand_form f
+ = tic6x_opcode_table[opc->id].operand_info[i].form;
+
+ operand_forms[i] |= tic6x_coarse_operand_form (f);
+ }
+ }
+ num_operands_permitted[num_operands] = TRUE;
+ if (num_operands > max_num_operands)
+ max_num_operands = num_operands;
+ }
+
+ if (!ok_this_arch)
+ {
+ as_bad (_("'%.*s' instruction not supported on this architecture"),
+ opc_len, str);
+ free (opcm);
+ return;
+ }
+
+ if (!ok_this_fu)
+ {
+ as_bad (_("'%.*s' instruction not supported on this functional unit"),
+ opc_len, str);
+ free (opcm);
+ return;
+ }
+
+ if (!ok_this_arch_fu)
+ {
+ as_bad (_("'%.*s' instruction not supported on this functional unit"
+ " for this architecture"),
+ opc_len, str);
+ free (opcm);
+ return;
+ }
+
+ /* If there were no instructions matching the above availability
+ checks, we should now have given an error and returned. */
+ if (num_matching_opcodes == 0)
+ abort ();
+
+ num_operands_read = 0;
+ while (TRUE)
+ {
+ skip_whitespace (p);
+ if (is_end_of_line[(unsigned char) *p])
+ {
+ if (num_operands_read > 0)
+ {
+ as_bad (_("missing operand after comma"));
+ bad_operands = TRUE;
+ }
+ break;
+ }
+
+ if (max_num_operands == 0)
+ {
+ as_bad (_("too many operands to '%.*s'"), opc_len, str);
+ bad_operands = TRUE;
+ break;
+ }
+
+ if (!tic6x_parse_operand (&p, &operands[num_operands_read],
+ operand_forms[num_operands_read], str, opc_len,
+ num_operands_read + 1))
+ bad_operands = TRUE;
+ num_operands_read++;
+
+ if (is_end_of_line[(unsigned char) *p])
+ break;
+ else if (*p == ',')
+ {
+ p++;
+ if (num_operands_read == max_num_operands)
+ {
+ as_bad (_("too many operands to '%.*s'"), opc_len, str);
+ bad_operands = TRUE;
+ break;
+ }
+ continue;
+ }
+ else
+ /* Operand parsing should consume whole operands. */
+ abort ();
+ }
+
+ if (!bad_operands && !num_operands_permitted[num_operands_read])
+ {
+ as_bad (_("bad number of operands to '%.*s'"), opc_len, str);
+ bad_operands = TRUE;
+ }
+
+ if (!bad_operands)
+ {
+ /* Each operand is of the right syntactic form for some opcode
+ choice, and the number of operands is valid. Check that each
+ operand is OK in detail for some opcode choice with the right
+ number of operands. */
+ unsigned int i;
+
+ for (i = 0; i < num_operands_read; i++)
+ {
+ bfd_boolean coarse_ok = FALSE;
+ bfd_boolean fine_ok = FALSE;
+ tic6x_operand_match fine_failure = tic6x_match_matches;
+ unsigned int j;
+
+ for (j = 0; j < num_matching_opcodes; j++)
+ {
+ tic6x_operand_form f;
+ tic6x_rw rw;
+ unsigned int cf;
+ tic6x_operand_match this_fine_failure;
+
+ if (tic6x_opcode_table[opcm[j]].flags & TIC6X_FLAG_SPMASK)
+ {
+ f = tic6x_operand_func_unit;
+ rw = tic6x_rw_none;
+ }
+ else
+ {
+ if (tic6x_opcode_table[opcm[j]].num_operands
+ != num_operands_read)
+ continue;
+
+ f = tic6x_opcode_table[opcm[j]].operand_info[i].form;
+ rw = tic6x_opcode_table[opcm[j]].operand_info[i].rw;
+ }
+ cf = tic6x_coarse_operand_form (f);
+
+ if (operands[i].form != cf)
+ continue;
+
+ coarse_ok = TRUE;
+ this_fine_failure
+ = tic6x_operand_matches_form (&operands[i], f, rw,
+ func_unit_side,
+ cross_side,
+ func_unit_data_side);
+ if (this_fine_failure == tic6x_match_matches)
+ {
+ fine_ok = TRUE;
+ break;
+ }
+ if (fine_failure == tic6x_match_matches
+ || fine_failure > this_fine_failure)
+ fine_failure = this_fine_failure;
+ }
+
+ /* No instructions should have operand syntactic forms only
+ acceptable with certain numbers of operands, so no
+ diagnostic for this case. */
+ if (!coarse_ok)
+ abort ();
+
+ if (!fine_ok)
+ {
+ switch (fine_failure)
+ {
+ case tic6x_match_non_const:
+ as_bad (_("operand %u of '%.*s' not constant"),
+ i + 1, opc_len, str);
+ break;
+
+ case tic6x_match_wrong_side:
+ as_bad (_("operand %u of '%.*s' on wrong side"),
+ i + 1, opc_len, str);
+ break;
+
+ case tic6x_match_bad_return:
+ as_bad (_("operand %u of '%.*s' not a valid return "
+ "address register"),
+ i + 1, opc_len, str);
+ break;
+
+ case tic6x_match_ctrl_write_only:
+ as_bad (_("operand %u of '%.*s' is write-only"),
+ i + 1, opc_len, str);
+ break;
+
+ case tic6x_match_ctrl_read_only:
+ as_bad (_("operand %u of '%.*s' is read-only"),
+ i + 1, opc_len, str);
+ break;
+
+ case tic6x_match_bad_mem:
+ as_bad (_("operand %u of '%.*s' not a valid memory "
+ "reference"),
+ i + 1, opc_len, str);
+ break;
+
+ case tic6x_match_bad_address:
+ as_bad (_("operand %u of '%.*s' not a valid base "
+ "address register"),
+ i + 1, opc_len, str);
+ break;
+
+ default:
+ abort ();
+ }
+ bad_operands = TRUE;
+ break;
+ }
+ }
+ }
+
+ if (!bad_operands)
+ {
+ /* Each operand is OK for some opcode choice, and the number of
+ operands is valid. Check whether there is an opcode choice
+ for which all operands are simultaneously valid. */
+ unsigned int i;
+ bfd_boolean found_match = FALSE;
+
+ for (i = 0; i < TIC6X_NUM_PREFER; i++)
+ opc_rank[i] = (unsigned int) -1;
+
+ min_rank = TIC6X_NUM_PREFER - 1;
+ max_rank = 0;
+
+ for (i = 0; i < num_matching_opcodes; i++)
+ {
+ unsigned int j;
+ bfd_boolean this_matches = TRUE;
+
+ if (!(tic6x_opcode_table[opcm[i]].flags & TIC6X_FLAG_SPMASK)
+ && tic6x_opcode_table[opcm[i]].num_operands != num_operands_read)
+ continue;
+
+ for (j = 0; j < num_operands_read; j++)
+ {
+ tic6x_operand_form f;
+ tic6x_rw rw;
+
+ if (tic6x_opcode_table[opcm[i]].flags & TIC6X_FLAG_SPMASK)
+ {
+ f = tic6x_operand_func_unit;
+ rw = tic6x_rw_none;
+ }
+ else
+ {
+ f = tic6x_opcode_table[opcm[i]].operand_info[j].form;
+ rw = tic6x_opcode_table[opcm[i]].operand_info[j].rw;
+ }
+ if (tic6x_operand_matches_form (&operands[j], f, rw,
+ func_unit_side,
+ cross_side,
+ func_unit_data_side)
+ != tic6x_match_matches)
+ {
+ this_matches = FALSE;
+ break;
+ }
+ }
+
+ if (this_matches)
+ {
+ int rank = TIC6X_PREFER_VAL (tic6x_opcode_table[opcm[i]].flags);
+
+ if (rank < min_rank)
+ min_rank = rank;
+ if (rank > max_rank)
+ max_rank = rank;
+
+ if (opc_rank[rank] == (unsigned int) -1)
+ opc_rank[rank] = i;
+ else
+ /* The opcode table should provide a total ordering
+ for all cases where multiple matches may get
+ here. */
+ abort ();
+
+ found_match = TRUE;
+ }
+ }
+
+ if (!found_match)
+ {
+ as_bad (_("bad operand combination for '%.*s'"), opc_len, str);
+ bad_operands = TRUE;
+ }
+ }
+
+ if (bad_operands)
+ {
+ free (opcm);
+ return;
+ }
+
+ opcode_value = 0;
+ encoded_ok = FALSE;
+ for (try_rank = max_rank; try_rank >= min_rank; try_rank--)
+ {
+ fix_needed = FALSE;
+
+ if (opc_rank[try_rank] == (unsigned int) -1)
+ continue;
+
+ opcode_value = tic6x_try_encode (opcm[opc_rank[try_rank]], operands,
+ num_operands_read, this_line_creg,
+ this_line_z, func_unit_side,
+ func_unit_cross, func_unit_data_side,
+ seginfo->tc_segment_info_data.sploop_ii,
+ &fix_exp, &fix_pcrel, &fx_r_type,
+ &fix_adda, &fix_needed, &encoded_ok,
+ (try_rank == min_rank ? TRUE : FALSE),
+ str, opc_len);
+ if (encoded_ok)
+ {
+ opct = &tic6x_opcode_table[opcm[opc_rank[try_rank]]];
+ break;
+ }
+ }
+
+ free (opcm);
+
+ if (!encoded_ok)
+ return;
+
+ if (this_line_parallel)
+ {
+ if (seginfo->tc_segment_info_data.num_execute_packet_insns == 0)
+ {
+ as_bad (_("parallel instruction not following another instruction"));
+ return;
+ }
+
+ if (seginfo->tc_segment_info_data.num_execute_packet_insns >= 8)
+ {
+ as_bad (_("too many instructions in execute packet"));
+ return;
+ }
+
+ if (this_insn_label)
+ as_bad (_("label not at start of execute packet"));
+
+ if (opct->flags & TIC6X_FLAG_FIRST)
+ as_bad (_("'%.*s' instruction not at start of execute packet"),
+ opc_len, str);
+
+ *seginfo->tc_segment_info_data.last_insn_lsb |= 0x1;
+ }
+ else
+ {
+ seginfo->tc_segment_info_data.num_execute_packet_insns = 0;
+ seginfo->tc_segment_info_data.spmask_addr = NULL;
+ }
+
+ if (opct->flags & TIC6X_FLAG_SPLOOP)
+ {
+ if (seginfo->tc_segment_info_data.sploop_ii)
+ as_bad (_("nested software pipelined loop"));
+ if (num_operands_read != 1
+ || operands[0].form != TIC6X_OP_EXP
+ || operands[0].value.exp.X_op != O_constant)
+ abort ();
+ seginfo->tc_segment_info_data.sploop_ii
+ = operands[0].value.exp.X_add_number;
+ }
+ else if (opct->flags & TIC6X_FLAG_SPKERNEL)
+ {
+ if (!seginfo->tc_segment_info_data.sploop_ii)
+ as_bad (_("'%.*s' instruction not in a software pipelined loop"),
+ opc_len, str);
+ seginfo->tc_segment_info_data.sploop_ii = 0;
+ }
+
+ if (this_line_spmask)
+ {
+ if (seginfo->tc_segment_info_data.spmask_addr == NULL)
+ as_bad (_("'||^' without previous SPMASK"));
+ else if (func_unit_base == tic6x_func_unit_nfu)
+ as_bad (_("cannot mask instruction using no functional unit"));
+ else
+ {
+ unsigned int spmask_opcode;
+ unsigned int mask_bit;
+
+ spmask_opcode
+ = md_chars_to_number (seginfo->tc_segment_info_data.spmask_addr,
+ 4);
+ mask_bit = tic6x_encode_spmask (func_unit_base, func_unit_side);
+ mask_bit <<= 18;
+ if (spmask_opcode & mask_bit)
+ as_bad (_("functional unit already masked"));
+ spmask_opcode |= mask_bit;
+ md_number_to_chars (seginfo->tc_segment_info_data.spmask_addr,
+ spmask_opcode, 4);
+ }
+ }
+
+ record_alignment (now_seg, 5);
+ output = frag_more (4);
+ md_number_to_chars (output, opcode_value, 4);
+ if (fix_needed)
+ tic6x_fix_new_exp (frag_now, output - frag_now->fr_literal, 4, fix_exp,
+ fix_pcrel, fx_r_type, fix_adda);
+ seginfo->tc_segment_info_data.num_execute_packet_insns++;
+ seginfo->tc_segment_info_data.last_insn_lsb
+ = (target_big_endian ? output + 3 : output);
+ if (opct->flags & TIC6X_FLAG_SPMASK)
+ seginfo->tc_segment_info_data.spmask_addr = output;
+ dwarf2_emit_insn (4);
+}
+
+/* Modify NEWVAL (32-bit) by inserting VALUE, shifted right by SHIFT
+ and the least significant BITS bits taken, at position POS. */
+#define MODIFY_VALUE(NEWVAL, VALUE, SHIFT, POS, BITS) \
+ do { \
+ (NEWVAL) &= 0xffffffffU & ~(((1U << (BITS)) - 1) << (POS)); \
+ (NEWVAL) |= (((VALUE) >> (SHIFT)) & ((1U << (BITS)) - 1)) << (POS); \
+ } while (0)
+
+/* Apply a fixup to the object file. */
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+ offsetT value = *valP;
+ char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
+
+ value = SEXT (value);
+ *valP = value;
+
+ fixP->fx_offset = SEXT (fixP->fx_offset);
+
+ if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
+ fixP->fx_done = 1;
+
+ /* We do our own overflow checks. */
+ fixP->fx_no_overflow = 1;
+
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_NONE:
+ /* Force output to the object file. */
+ fixP->fx_done = 0;
+ break;
+
+ case BFD_RELOC_32:
+ if (fixP->fx_done || !seg->use_rela_p)
+ md_number_to_chars (buf, value, 4);
+ break;
+
+ case BFD_RELOC_16:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ if (value < -0x8000 || value > 0xffff)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("value too large for 2-byte field"));
+ md_number_to_chars (buf, value, 2);
+ }
+ break;
+
+ case BFD_RELOC_8:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ if (value < -0x80 || value > 0xff)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("value too large for 1-byte field"));
+ md_number_to_chars (buf, value, 1);
+ }
+ break;
+
+ case BFD_RELOC_C6000_ABS_S16:
+ case BFD_RELOC_C6000_ABS_L16:
+ case BFD_RELOC_C6000_SBR_S16:
+ case BFD_RELOC_C6000_SBR_L16_B:
+ case BFD_RELOC_C6000_SBR_L16_H:
+ case BFD_RELOC_C6000_SBR_L16_W:
+ case BFD_RELOC_C6000_SBR_GOT_L16_W:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ MODIFY_VALUE (newval, value, 0, 7, 16);
+ if ((value < -0x8000 || value > 0x7fff)
+ && (fixP->fx_r_type == BFD_RELOC_C6000_ABS_S16
+ || fixP->fx_r_type == BFD_RELOC_C6000_SBR_S16))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate offset out of range"));
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ if (fixP->fx_done
+ && fixP->fx_r_type != BFD_RELOC_C6000_ABS_S16
+ && fixP->fx_r_type != BFD_RELOC_C6000_ABS_L16)
+ abort ();
+ break;
+
+ case BFD_RELOC_C6000_ABS_H16:
+ case BFD_RELOC_C6000_SBR_H16_B:
+ case BFD_RELOC_C6000_SBR_H16_H:
+ case BFD_RELOC_C6000_SBR_H16_W:
+ case BFD_RELOC_C6000_SBR_GOT_H16_W:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ MODIFY_VALUE (newval, value, 16, 7, 16);
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ if (fixP->fx_done && fixP->fx_r_type != BFD_RELOC_C6000_ABS_H16)
+ abort ();
+ break;
+
+ case BFD_RELOC_C6000_SBR_U15_B:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ MODIFY_VALUE (newval, value, 0, 8, 15);
+ if (value < 0 || value > 0x7fff)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate offset out of range"));
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+
+ case BFD_RELOC_C6000_SBR_U15_H:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ /* Constant ADDA operands, processed as constant when the
+ instruction is parsed, are encoded as-is rather than
+ shifted. If the operand of an ADDA instruction is now
+ constant (for example, the difference between two labels
+ found after the instruction), ensure it is encoded the
+ same way it would have been if the constant value had
+ been known when the instruction was parsed. */
+ if (fixP->tc_fix_data.fix_adda && fixP->fx_done)
+ value <<= 1;
+
+ MODIFY_VALUE (newval, value, 1, 8, 15);
+ if (value & 1)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate offset not 2-byte-aligned"));
+ if (value < 0 || value > 0xfffe)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate offset out of range"));
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+
+ case BFD_RELOC_C6000_SBR_U15_W:
+ case BFD_RELOC_C6000_SBR_GOT_U15_W:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ /* Constant ADDA operands, processed as constant when the
+ instruction is parsed, are encoded as-is rather than
+ shifted. If the operand of an ADDA instruction is now
+ constant (for example, the difference between two labels
+ found after the instruction), ensure it is encoded the
+ same way it would have been if the constant value had
+ been known when the instruction was parsed. */
+ if (fixP->tc_fix_data.fix_adda && fixP->fx_done)
+ value <<= 2;
+
+ MODIFY_VALUE (newval, value, 2, 8, 15);
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate offset not 4-byte-aligned"));
+ if (value < 0 || value > 0x1fffc)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("immediate offset out of range"));
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ if (fixP->fx_done && fixP->fx_r_type != BFD_RELOC_C6000_SBR_U15_W)
+ abort ();
+ break;
+
+ case BFD_RELOC_C6000_DSBT_INDEX:
+ if (value != 0)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("addend used with $DSBT_INDEX"));
+ if (fixP->fx_done)
+ abort ();
+ break;
+
+ case BFD_RELOC_C6000_PCR_S21:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ MODIFY_VALUE (newval, value, 2, 7, 21);
+
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative offset not 4-byte-aligned"));
+ if (value < -0x400000 || value > 0x3ffffc)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative offset out of range"));
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+
+ case BFD_RELOC_C6000_PCR_S12:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ MODIFY_VALUE (newval, value, 2, 16, 12);
+
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative offset not 4-byte-aligned"));
+ if (value < -0x2000 || value > 0x1ffc)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative offset out of range"));
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+
+ case BFD_RELOC_C6000_PCR_S10:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ MODIFY_VALUE (newval, value, 2, 13, 10);
+
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative offset not 4-byte-aligned"));
+ if (value < -0x800 || value > 0x7fc)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative offset out of range"));
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+
+ case BFD_RELOC_C6000_PCR_S7:
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval = md_chars_to_number (buf, 4);
+
+ MODIFY_VALUE (newval, value, 2, 16, 7);
+
+ if (value & 3)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative offset not 4-byte-aligned"));
+ if (value < -0x100 || value > 0xfc)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative offset out of range"));
+
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+
+ default:
+ abort ();
+ }
+}
+
+/* Convert a floating-point number to target (IEEE) format. */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+ return ieee_md_atof (type, litP, sizeP, target_big_endian);
+}
+
+/* No machine-dependent frags yet. */
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
+ fragS *fragp ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+/* No machine-dependent frags yet. */
+
+int
+md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
+ segT seg ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+/* Put a number into target byte order. */
+
+void
+md_number_to_chars (char *buf, valueT val, int n)
+{
+ if (target_big_endian)
+ number_to_chars_bigendian (buf, val, n);
+ else
+ number_to_chars_littleendian (buf, val, n);
+}
+
+/* Machine-dependent operand parsing not currently needed. */
+
+void
+md_operand (expressionS *op ATTRIBUTE_UNUSED)
+{
+}
+
+/* PC-relative operands are relative to the start of the fetch
+ packet. */
+
+long
+md_pcrel_from (fixS *fixp)
+{
+ return (fixp->fx_where + fixp->fx_frag->fr_address) & ~(long) 0x1f;
+}
+
+/* Round up a section size to the appropriate boundary. */
+
+valueT
+md_section_align (segT segment ATTRIBUTE_UNUSED,
+ valueT size)
+{
+ /* Round up section sizes to ensure that text sections consist of
+ whole fetch packets. */
+ int align = bfd_get_section_alignment (stdoutput, segment);
+ return ((size + (1 << align) - 1) & ((valueT) -1 << align));
+}
+
+/* No special undefined symbol handling needed for now. */
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+ return NULL;
+}
+
+/* Translate internal representation of relocation info to BFD target
+ format. */
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
+{
+ arelent *reloc;
+ bfd_reloc_code_real_type r_type;
+
+ reloc = xmalloc (sizeof (arelent));
+ reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+ reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+ reloc->addend = fixp->fx_offset;
+ r_type = fixp->fx_r_type;
+ reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type);
+
+ if (reloc->howto == NULL)
+ {
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("Cannot represent relocation type %s"),
+ bfd_get_reloc_code_name (r_type));
+ return NULL;
+ }
+
+ return reloc;
+}
--- /dev/null
+/* Definitions for TI C6X assembler.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#define TC_TIC6X 1
+#define TARGET_BYTES_BIG_ENDIAN 0
+#define WORKING_DOT_WORD
+#define DOUBLEBAR_PARALLEL
+#define DWARF2_LINE_MIN_INSN_LENGTH 2
+#define MD_APPLY_SYM_VALUE(FIX) 0
+#define TC_PREDICATE_START_CHAR '['
+#define TC_PREDICATE_END_CHAR ']'
+/* For TI C6X, we keep spaces in what the preprocessor considers
+ operands as they may separate functional unit specifiers from
+ operands. */
+#define TC_KEEP_OPERAND_SPACES 1
+
+#define TARGET_ARCH bfd_arch_tic6x
+#define TARGET_FORMAT (target_big_endian \
+ ? "elf32-tic6x-be" \
+ : "elf32-tic6x-le")
+
+typedef struct
+{
+ /* Number of instructions in the current execute packet. */
+ unsigned int num_execute_packet_insns;
+
+ /* Whether a label has been seen since the last instruction or data
+ (in which case a following instruction may not have parallel
+ bars, but must start a new execute packet). */
+ bfd_boolean seen_label;
+
+ /* Whether compact instructions are forbidden here. */
+ bfd_boolean nocmp;
+
+ /* If there is a current execute packet, a pointer to the
+ least-significant byte of the last instruction in it (for setting
+ the p-bit). */
+ char *last_insn_lsb;
+
+ /* If there has been an SPMASK instruction in the current execute
+ packet, a pointer to the first byte in it (for processing
+ ||^); otherwise NULL. */
+ char *spmask_addr;
+
+ /* If an SPLOOP-family instruction has been seen, and a following
+ SPKERNEL-family instruction has not yet been seen, the ii value
+ from the SPLOOP instruction (in the range 1 to 14); otherwise
+ 0. */
+ int sploop_ii;
+} tic6x_segment_info_type;
+#define TC_SEGMENT_INFO_TYPE tic6x_segment_info_type
+
+typedef struct
+{
+ /* Whether this fix was for an ADDA instruction. If so, a constant
+ resulting from resolving the fix should be implicitly shifted
+ left (it represents a value to be encoded literally in the
+ instruction, whereas a non-constant represents a DP-relative
+ value counting in the appropriate units). */
+ bfd_boolean fix_adda;
+} tic6x_fix_info;
+#define TC_FIX_TYPE tic6x_fix_info
+#define TC_INIT_FIX_DATA(fixP) tic6x_init_fix_data (fixP)
+struct fix;
+extern void tic6x_init_fix_data (struct fix *fixP);
+
+#define md_after_parse_args() tic6x_after_parse_args ()
+extern void tic6x_after_parse_args (void);
+
+#define md_cleanup() tic6x_cleanup ()
+extern void tic6x_cleanup (void);
+
+#define md_cons_align(n) tic6x_cons_align (n)
+extern void tic6x_cons_align (int n);
+
+#define md_parse_name(name, exprP, mode, nextcharP) \
+ tic6x_parse_name (name, exprP, mode, nextcharP)
+extern int tic6x_parse_name (const char *name, expressionS *exprP,
+ enum expr_mode mode, char *nextchar);
+
+#define md_start_line_hook() tic6x_start_line_hook ()
+extern void tic6x_start_line_hook (void);
+
+#define TC_CONS_FIX_NEW(frag, where, size, exp) \
+ tic6x_cons_fix_new (frag, where, size, exp)
+extern void tic6x_cons_fix_new (fragS *frag, int where, int size,
+ expressionS *exp);
+
+#define tc_frob_label(sym) tic6x_frob_label (sym)
+extern void tic6x_frob_label (symbolS *sym);
+
+#define tc_unrecognized_line(c) tic6x_unrecognized_line (c)
+extern int tic6x_unrecognized_line (int c);
tic30-*-*coff*) fmt=coff bfd_gas=yes ;;
tic4x-*-* | c4x-*-*) fmt=coff bfd_gas=yes ;;
tic54x-*-* | c54x*-*-*) fmt=coff bfd_gas=yes need_libm=yes;;
+ tic6x-*-*) fmt=elf ;;
v850-*-*) fmt=elf ;;
v850e-*-*) fmt=elf ;;
c-sh64.texi \
c-sparc.texi \
c-tic54x.texi \
+ c-tic6x.texi \
c-vax.texi \
c-v850.texi \
c-xtensa.texi \
c-sh64.texi \
c-sparc.texi \
c-tic54x.texi \
+ c-tic6x.texi \
c-vax.texi \
c-v850.texi \
c-xtensa.texi \
@c Copyright 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002,
-@c 2003, 2005, 2006, 2007, 2008, 2009
+@c 2003, 2005, 2006, 2007, 2008, 2009, 2010
@c Free Software Foundation, Inc.
@c This file is part of the documentation for the GAS manual
@set SH
@set SPARC
@set TIC54X
+@set TIC6X
@set V850
@set VAX
@set XTENSA
\input texinfo @c -*-Texinfo-*-
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
@c Free Software Foundation, Inc.
@c UPDATE!! On future updates--
@c (1) check for new machine-dep cmdline options in
@c man begin COPYRIGHT
Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
-2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
@vskip 0pt plus 1filll
Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
-2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
[@b{-merrors-to-file} @var{<filename>}|@b{-me} @var{<filename>}]
@end ifset
+@ifset TIC6X
+
+@emph{Target TIC6X options:}
+ [@b{-march=@var{arch}}] [@b{-matomic}|@b{-mno-atomic}]
+ [@b{-mbig-endian}|@b{-mlittle-endian}]
+@end ifset
+
@ifset Z80
@emph{Target Z80 options:}
@end table
@end ifset
+@ifset TIC6X
+The following options are available when @value{AS} is configured for a
+TMS320C6000 processor.
+
+@table @gcctabopt
+@item -march=@var{arch}
+Enable (only) instructions from architecture @var{arch}. By default,
+all instructions are permitted.
+
+The following values of @var{arch} are accepted: @code{c62x},
+@code{c64x}, @code{c64x+}, @code{c67x}, @code{c67x+}, @code{c674x}.
+
+@item -matomic
+@itemx -mno-atomic
+Enable or disable the optional C64x+ atomic operation instructions.
+By default, they are enabled if no @option{-march} option is given, or
+if an architecture is specified with @option{-march} that implies
+these instructions are present (currently, there are no such
+architectures); they are disabled if an architecture is specified with
+@option{-march} on which the instructions are optional or not
+present. This option overrides such a default from the architecture,
+independent of the order in which the @option{-march} or
+@option{-matomic} or @option{-mno-atomic} options are passed.
+
+@item -mbig-endian
+@itemx -mlittle-endian
+Generate code for the specified endianness. The default is
+little-endian.
+@end table
+
+@end ifset
+
@ifset XTENSA
The following options are available when @value{AS} is configured for
an Xtensa processor.
@ifset RX
@samp{#} on the RX;
@end ifset
+@ifset TIC6X
+@samp{;} on the TMS320C6X;
+@end ifset
@ifset VAX
@samp{#} on the Vax;
@end ifset
@ifset TIC54X
* TIC54X-Dependent:: TI TMS320C54x Dependent Features
@end ifset
+@ifset TIC6X
+* TIC6X-Dependent :: TI TMS320C6x Dependent Features
+@end ifset
@ifset V850
* V850-Dependent:: V850 Dependent Features
@end ifset
@include c-tic54x.texi
@end ifset
+@ifset TIC6X
+@include c-tic6x.texi
+@end ifset
+
@ifset Z80
@include c-z80.texi
@end ifset
--- /dev/null
+@c Copyright 2010 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node TIC6X-Dependent
+@chapter TIC6X Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter TIC6X Dependent Features
+@end ifclear
+
+@cindex TIC6X support
+@cindex TMS320C6X support
+@menu
+* TIC6X Options:: Options
+* TIC6X Syntax:: Syntax
+* TIC6X Directives:: Directives
+@end menu
+
+@node TIC6X Options
+@section TIC6X Options
+@cindex TIC6X options
+@cindex options for TIC6X
+
+@table @code
+
+@cindex @code{-march=} command line option, TIC6X
+@item -march=@var{arch}
+Enable (only) instructions from architecture @var{arch}. By default,
+all instructions are permitted.
+
+The following values of @var{arch} are accepted: @code{c62x},
+@code{c64x}, @code{c64x+}, @code{c67x}, @code{c67x+}, @code{c674x}.
+
+@cindex @code{-matomic} command line option, TIC6X
+@cindex @code{-mno-atomic} command line option, TIC6X
+@item -matomic
+@itemx -mno-atomic
+Enable or disable the optional C64x+ atomic operation instructions.
+By default, they are enabled if no @option{-march} option is given, or
+if an architecture is specified with @option{-march} that implies
+these instructions are present (currently, there are no such
+architectures); they are disabled if an architecture is specified with
+@option{-march} on which the instructions are optional or not
+present. This option overrides such a default from the architecture,
+independent of the order in which the @option{-march} or
+@option{-matomic} or @option{-mno-atomic} options are passed.
+
+@cindex TIC6X big-endian output
+@cindex TIC6X little-endian output
+@cindex big-endian output, TIC6X
+@cindex little-endian output, TIC6X
+@item -mbig-endian
+@itemx -mlittle-endian
+Generate code for the specified endianness. The default is
+little-endian.
+
+@end table
+
+@node TIC6X Syntax
+@section TIC6X Syntax
+
+@cindex line comment character, TIC6X
+@cindex TIC6X line comment character
+The presence of a @samp{;} on a line indicates the start of a comment
+that extends to the end of the current line. If a @samp{#} or
+@samp{*} appears as the first character of a line, the whole line is
+treated as a comment.
+
+@cindex line separator, TIC6X
+@cindex statement separator, TIC6X
+@cindex TIC6X line separator
+The @samp{@@} character can be used instead of a newline to separate
+statements.
+
+Instruction, register and functional unit names are case-insensitive.
+@command{@value{AS}} requires fully-specified functional unit names,
+such as @samp{.S1}, @samp{.L1X} or @samp{.D1T2}, on all instructions
+using a functional unit.
+
+For some instructions, there may be syntactic ambiguity between
+register or functional unit names and the names of labels or other
+symbols. To avoid this, enclose the ambiguous symbol name in
+parentheses; register and functional unit names may not be enclosed in
+parentheses.
+
+@node TIC6X Directives
+@section TIC6X Directives
+
+@cindex machine directives, TIC6X
+@cindex TIC6X machine directives
+
+Directives controlling the set of instructions accepted by the
+assembler have effect for instructions between the directive and any
+subsequent directive overriding it.
+
+@table @code
+
+@cindex @code{.arch} directive, TIC6X
+@item .arch @var{arch}
+This has the same effect as @option{-march=@var{arch}}.
+
+@cindex @code{.atomic} directive, TIC6X
+@cindex @code{.noatomic} directive, TIC6X
+@item .atomic
+@itemx .noatomic
+These have the same effects as @option{-matomic} and
+@option{-mno-atomic}.
+
+@cindex @code{.nocmp} directive, TIC6X
+@item .nocmp
+Disallow use of C64x+ compact instructions in the current text
+section.
+
+@end table
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * gas/tic6x: New directory and testcases.
+
2010-03-23 Joseph Myers <joseph@codesourcery.com>
* gas/macros/dot.s: Remove space in .byte operands.
--- /dev/null
+#name: C6X invalid -march
+#as: -march=invalid
+#source: dummy.s
+#error-output: arch-invalid-1.l
--- /dev/null
+Assembler messages:
+Error: unknown architecture 'invalid'
--- /dev/null
+#name: C6X invalid .arch
+#error-output: arch-invalid-2.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:1: Error: unknown architecture 'nonesuch'
--- /dev/null
+.arch nonesuch
--- /dev/null
+#objdump: -r
+#name: C6X data relocations
+
+.*: *file format elf32-tic6x-le
+
+RELOCATION RECORDS FOR \[\.data\]:
+OFFSET *TYPE *VALUE *
+0+00 R_C6000_ABS32 +ext1
+0+04 R_C6000_ABS32 +ext1\+0x0+04
+0+08 R_C6000_ABS16 +ext2
+0+0a R_C6000_ABS16 +ext2\+0xf+fe
+0+0c R_C6000_ABS8 +ext3
+0+0d R_C6000_ABS8 +ext3\+0x0+01
--- /dev/null
+.data
+.globl a
+.globl ext1
+.globl ext2
+.globl ext3
+a:
+ .word ext1
+ .word ext1 + 4
+ .short ext2
+ .short ext2 - 2
+ .byte ext3
+ .byte ext3 + 1
--- /dev/null
+#name: C6X junk after directives
+#error-output: dir-junk.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:2: Error: junk at end of line, first unrecognized character is `c'
+[^:]*:3: Error: junk at end of line, first unrecognized character is `f'
+[^:]*:6: Error: junk at end of line, first unrecognized character is `b'
+[^:]*:7: Error: junk at end of line, first unrecognized character is `x'
--- /dev/null
+.arch c64x
+.arch c64x c64x
+.atomic foo
+.atomic ; comment OK
+.noatomic
+.noatomic bar
+.nocmp x
--- /dev/null
+# Dummy input file for tests of command-line options.
+.text
+.globl f
+f:
+ nop 2
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X endian options 1
+#as: -mbig-endian
+#source: dummy.s
+
+.*: *file format elf32-tic6x-be
+
+
+Disassembly of section \.text:
+0+00 <[^>]*> 00002000[ \t]+nop 2
+[ \t]*\.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X endian options 2
+#as: -mlittle-endian -mbig-endian
+#source: dummy.s
+
+.*: *file format elf32-tic6x-be
+
+
+Disassembly of section \.text:
+0+00 <[^>]*> 00002000[ \t]+nop 2
+[ \t]*\.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X endian options 3
+#as: -mbig-endian -mlittle-endian
+#source: dummy.s
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+0+00 <[^>]*> 00002000[ \t]+nop 2
+[ \t]*\.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X atomic instructions
+#as: -march=c674x -matomic -mlittle-endian
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+[0-9a-f]+[048c] <[^>]*> c0800742[ \t]+\[a0\] cmtl \.D2T2 \*b0,b1
+[0-9a-f]+[048c] <[^>]*> 51880642[ \t]+\[!b1\] ll \.D2T2 \*b2,b3
+[0-9a-f]+[048c] <[^>]*> af7406c2[ \t]+\[a2\] sl \.D2T2 b30,\*b29
+[ \t]*\.\.\.
--- /dev/null
+# Test atomic instructions.
+.text
+.nocmp
+.globl f
+f:
+ [a0] cmtl .D2T2 *b0,b1
+ [!b1] ll .D2T2 *b2,b3
+ [a2] sl .D2T2 b30,*b29
--- /dev/null
+#name: C6X bad instructions 1
+#error-output: insns-bad-1.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: unknown opcode 'nonesuch'
+[^:]*:6: Error: operand 1 of 'nop' not constant
+[^:]*:7: Error: too many operands to 'nop'
+[^:]*:8: Error: too many operands to 'nop'
+[^:]*:9: Error: too many operands to 'nop'
+[^:]*:10: Error: junk after operand 1 of 'nop'
+[^:]*:11: Error: operand 1 of 'nop' out of range
+[^:]*:12: Error: operand 1 of 'nop' out of range
+[^:]*:13: Error: operand 1 of 'nop' out of range
+[^:]*:14: Error: operand 1 of 'nop' out of range
+[^:]*:15: Error: operand 1 of 'nop' out of range
+[^:]*:16: Error: missing operand after comma
+[^:]*:17: Error: bad number of operands to 'abs'
+[^:]*:18: Error: 'abs' instruction not supported on this functional unit
+[^:]*:19: Error: bad register or register pair for operand 1 of 'abs'
+[^:]*:19: Error: bad register or register pair for operand 2 of 'abs'
+[^:]*:20: Error: bad register for operand 1 of 'abs'
+[^:]*:20: Error: bad register for operand 2 of 'abs'
+[^:]*:21: Error: bad register or register pair for operand 2 of 'abs'
+[^:]*:22: Error: bad register or register pair for operand 1 of 'abs'
+[^:]*:23: Error: operand 1 of 'abs' on wrong side
+[^:]*:24: Error: operand 2 of 'abs' on wrong side
+[^:]*:25: Error: operand 1 of 'abs' on wrong side
+[^:]*:26: Error: operand 2 of 'abs' on wrong side
+[^:]*:27: Error: operand 1 of 'abs' on wrong side
+[^:]*:28: Error: operand 2 of 'abs' on wrong side
+[^:]*:29: Error: operand 2 of 'abs' on wrong side
+[^:]*:30: Error: operand 1 of 'abs' on wrong side
+[^:]*:31: Error: register pair for operand 1 of 'abs' not a valid even/odd pair
+[^:]*:32: Error: register pair for operand 2 of 'abs' not a valid even/odd pair
+[^:]*:33: Error: register pair for operand 1 of 'abs' not a valid even/odd pair
+[^:]*:33: Error: operand 1 of 'abs' on wrong side
+[^:]*:34: Error: operand 2 of 'abs' on wrong side
+[^:]*:35: Error: bad register for operand 1 of 'abs'
+[^:]*:35: Error: bad register for operand 2 of 'abs'
+[^:]*:36: Error: bad operand combination for 'abs'
+[^:]*:37: Error: bad number of operands to 'abs2'
+[^:]*:38: Error: 'abs2' instruction not supported on this functional unit
+[^:]*:39: Error: bad register for operand 1 of 'abs2'
+[^:]*:39: Error: bad register for operand 2 of 'abs2'
+[^:]*:40: Error: operand 1 of 'abs2' on wrong side
+[^:]*:41: Error: 'absdp' instruction not supported on this functional unit
+[^:]*:42: Error: bad number of operands to 'absdp'
+[^:]*:43: Error: bad register pair for operand 1 of 'absdp'
+[^:]*:43: Error: bad register pair for operand 2 of 'absdp'
+[^:]*:44: Error: 'absdp' instruction not supported on this functional unit
+[^:]*:45: Error: 'abssp' instruction not supported on this functional unit
+[^:]*:46: Error: bad register for operand 1 of 'abssp'
+[^:]*:47: Error: operand 1 of 'abssp' on wrong side
+[^:]*:48: Error: operand 1 of 'abssp' on wrong side
+[^:]*:49: Error: 'add' instruction not supported on this functional unit
+[^:]*:50: Error: operand 2 of 'add' on wrong side
+[^:]*:51: Error: operand 2 of 'add' on wrong side
+[^:]*:52: Error: junk after operand 1 of 'add'
+[^:]*:53: Error: operand 1 of 'add' out of range
+[^:]*:54: Error: operand 1 of 'add' out of range
+[^:]*:55: Error: bad operand combination for 'add'
+[^:]*:56: Error: operand 1 of 'add' out of range
+[^:]*:57: Error: bad number of operands to 'add'
+[^:]*:58: Error: bad register for operand 3 of 'add'
+[^:]*:59: Error: bad number of operands to 'add'
+[^:]*:60: Error: operand 2 of 'add' on wrong side
+[^:]*:61: Error: operand 1 of 'add' out of range
+[^:]*:62: Error: operand 1 of 'add' out of range
+[^:]*:63: Error: 'add' instruction not supported on this functional unit
+[^:]*:64: Error: bad number of operands to 'add'
+[^:]*:65: Error: operand 2 of 'add' out of range
+[^:]*:66: Error: operand 2 of 'add' out of range
+[^:]*:67: Error: bad operand combination for 'add'
+[^:]*:68: Error: operand 2 of 'add' out of range
+[^:]*:69: Error: operand 2 of 'add' out of range
+[^:]*:70: Error: 'addab' instruction not supported on this functional unit
+[^:]*:71: Error: operand 1 of 'addab' on wrong side
+[^:]*:72: Error: bad number of operands to 'addab'
+[^:]*:73: Error: operand 1 of 'addab' on wrong side
+[^:]*:74: Error: operand 2 of 'addab' out of range
+[^:]*:75: Error: operand 2 of 'addab' out of range
+[^:]*:76: Error: operand 2 of 'addab' out of range
+[^:]*:77: Error: operand 2 of 'addab' out of range
+[^:]*:78: Error: operand 2 of 'addab' out of range
+[^:]*:79: Error: 'addad' instruction not supported on this functional unit
+[^:]*:80: Error: 'addad' instruction not supported on this functional unit
+[^:]*:81: Error: too many operands to 'addad'
+[^:]*:82: Error: operand 2 of 'addad' out of range
+[^:]*:83: Error: operand 2 of 'addad' out of range
+[^:]*:84: Error: operand 2 of 'addad' on wrong side
+[^:]*:85: Error: operand 2 of 'addad' not constant
+[^:]*:86: Error: 'addah' instruction not supported on this functional unit
+[^:]*:87: Error: operand 1 of 'addah' on wrong side
+[^:]*:88: Error: bad number of operands to 'addah'
+[^:]*:89: Error: operand 1 of 'addah' on wrong side
+[^:]*:90: Error: operand 2 of 'addah' out of range
+[^:]*:91: Error: operand 2 of 'addah' out of range
+[^:]*:92: Error: operand 2 of 'addah' out of range
+[^:]*:93: Error: operand 2 of 'addah' out of range
+[^:]*:94: Error: operand 2 of 'addah' out of range
+[^:]*:95: Error: 'addaw' instruction not supported on this functional unit
+[^:]*:96: Error: operand 1 of 'addaw' on wrong side
+[^:]*:97: Error: bad number of operands to 'addaw'
+[^:]*:98: Error: operand 1 of 'addaw' on wrong side
+[^:]*:99: Error: operand 2 of 'addaw' out of range
+[^:]*:100: Error: operand 2 of 'addaw' out of range
+[^:]*:101: Error: operand 2 of 'addaw' out of range
+[^:]*:102: Error: operand 2 of 'addaw' out of range
+[^:]*:103: Error: operand 2 of 'addaw' out of range
+[^:]*:104: Error: 'adddp' instruction not supported on this functional unit
+[^:]*:105: Error: bad number of operands to 'adddp'
+[^:]*:106: Error: bad register pair for operand 1 of 'adddp'
+[^:]*:106: Error: bad register pair for operand 2 of 'adddp'
+[^:]*:106: Error: bad register pair for operand 3 of 'adddp'
+[^:]*:107: Error: operand 2 of 'adddp' on wrong side
+[^:]*:108: Error: operand 2 of 'adddp' on wrong side
+[^:]*:109: Error: 'addk' instruction not supported on this functional unit
+[^:]*:110: Error: operand 1 of 'addk' out of range
+[^:]*:111: Error: operand 1 of 'addk' out of range
+[^:]*:112: Error: bad number of operands to 'addk'
+[^:]*:113: Error: 'addk' instruction not supported on this functional unit
+[^:]*:114: Error: 'mvk' instruction not supported on this functional unit
+[^:]*:115: Error: operand 1 of 'mvk' out of range
+[^:]*:116: Error: operand 1 of 'mvk' out of range
+[^:]*:117: Error: too many operands to 'mvk'
+[^:]*:118: Error: 'mvk' instruction not supported on this functional unit
+[^:]*:119: Error: 'mvkh' instruction not supported on this functional unit
+[^:]*:120: Error: too many operands to 'mvkh'
+[^:]*:121: Error: 'mvkh' instruction not supported on this functional unit
+[^:]*:122: Error: 'mvklh' instruction not supported on this functional unit
+[^:]*:123: Error: too many operands to 'mvklh'
+[^:]*:124: Error: 'mvklh' instruction not supported on this functional unit
+[^:]*:125: Error: 'mvkl' instruction not supported on this functional unit
+[^:]*:126: Error: too many operands to 'mvkl'
+[^:]*:127: Error: 'mvkl' instruction not supported on this functional unit
+[^:]*:128: Error: 'addkpc' instruction not supported on this functional unit
+[^:]*:129: Error: 'addkpc' instruction not supported on this functional unit
+[^:]*:130: Error: invalid PC-relative operand
+[^:]*:131: Error: bad number of operands to 'addkpc'
+[^:]*:132: Error: operand 3 of 'addkpc' out of range
+[^:]*:133: Error: operand 3 of 'addkpc' out of range
+[^:]*:134: Error: 'b' instruction not supported on this functional unit
+[^:]*:135: Error: 'b' instruction not supported on this functional unit
+[^:]*:136: Error: too many operands to 'b'
+[^:]*:137: Error: invalid PC-relative operand
+[^:]*:138: Error: 'call' instruction not supported on this functional unit
+[^:]*:139: Error: 'call' instruction not supported on this functional unit
+[^:]*:140: Error: too many operands to 'call'
+[^:]*:141: Error: invalid PC-relative operand
+[^:]*:142: Error: 'bdec' instruction not supported on this functional unit
+[^:]*:143: Error: 'bdec' instruction not supported on this functional unit
+[^:]*:144: Error: operand 2 of 'bdec' on wrong side
+[^:]*:145: Error: invalid PC-relative operand
+[^:]*:146: Error: too many operands to 'bdec'
+[^:]*:147: Error: 'bpos' instruction not supported on this functional unit
+[^:]*:148: Error: 'bpos' instruction not supported on this functional unit
+[^:]*:149: Error: operand 2 of 'bpos' on wrong side
+[^:]*:150: Error: invalid PC-relative operand
+[^:]*:151: Error: too many operands to 'bpos'
+[^:]*:152: Error: 'bnop' instruction not supported on this functional unit
+[^:]*:153: Error: 'bnop' instruction not supported on this functional unit
+[^:]*:154: Error: operand 2 of 'bnop' out of range
+[^:]*:155: Error: invalid PC-relative operand
+[^:]*:156: Error: operand 2 of 'bnop' out of range
+[^:]*:157: Error: 'callnop' instruction not supported on this functional unit
+[^:]*:158: Error: 'callnop' instruction not supported on this functional unit
+[^:]*:159: Error: operand 2 of 'callnop' out of range
+[^:]*:160: Error: invalid PC-relative operand
+[^:]*:161: Error: operand 2 of 'callnop' out of range
+[^:]*:162: Error: 'callp' instruction not supported on this functional unit
+[^:]*:163: Error: 'callp' instruction not supported on this functional unit
+[^:]*:164: Error: operand 2 of 'callp' not a valid return address register
+[^:]*:165: Error: invalid PC-relative operand
+[^:]*:166: Error: operand 2 of 'callp' on wrong side
+[^:]*:167: Error: operand 2 of 'callp' on wrong side
+[^:]*:168: Error: 'addsp' instruction not supported on this functional unit
+[^:]*:169: Error: bad number of operands to 'addsp'
+[^:]*:170: Error: bad register for operand 2 of 'addsp'
+[^:]*:171: Error: operand 1 of 'addsp' on wrong side
+[^:]*:172: Error: operand 2 of 'addsp' on wrong side
+[^:]*:173: Error: 'addsub' instruction not supported on this functional unit
+[^:]*:174: Error: bad number of operands to 'addsub'
+[^:]*:175: Error: bad register pair for operand 3 of 'addsub'
+[^:]*:176: Error: operand 1 of 'addsub' on wrong side
+[^:]*:177: Error: 'addsub2' instruction not supported on this functional unit
+[^:]*:178: Error: bad number of operands to 'addsub2'
+[^:]*:179: Error: bad register pair for operand 3 of 'addsub2'
+[^:]*:180: Error: operand 1 of 'addsub2' on wrong side
+[^:]*:181: Error: 'addu' instruction not supported on this functional unit
+[^:]*:182: Error: bad number of operands to 'addu'
+[^:]*:183: Error: operand 1 of 'addu' on wrong side
+[^:]*:184: Error: bad register pair for operand 3 of 'addu'
+[^:]*:185: Error: 'add2' instruction not supported on this functional unit
+[^:]*:186: Error: too many operands to 'add2'
+[^:]*:187: Error: operand 1 of 'add2' on wrong side
+[^:]*:188: Error: operand 2 of 'add2' on wrong side
+[^:]*:189: Error: 'add4' instruction not supported on this functional unit
+[^:]*:190: Error: too many operands to 'add4'
+[^:]*:191: Error: operand 1 of 'add4' on wrong side
+[^:]*:192: Error: operand 2 of 'add4' on wrong side
+[^:]*:193: Error: 'and' instruction not supported on this functional unit
+[^:]*:194: Error: operand 1 of 'and' out of range
+[^:]*:195: Error: operand 1 of 'and' out of range
+[^:]*:196: Error: operand 1 of 'and' out of range
+[^:]*:197: Error: operand 1 of 'and' out of range
+[^:]*:198: Error: operand 1 of 'and' out of range
+[^:]*:199: Error: operand 1 of 'and' out of range
+[^:]*:200: Error: operand 1 of 'and' on wrong side
+[^:]*:201: Error: 'andn' instruction not supported on this functional unit
+[^:]*:202: Error: bad number of operands to 'andn'
+[^:]*:203: Error: operand 1 of 'andn' on wrong side
+[^:]*:204: Error: bad register for operand 1 of 'andn'
+[^:]*:205: Error: 'avg2' instruction not supported on this functional unit
+[^:]*:206: Error: bad number of operands to 'avg2'
+[^:]*:207: Error: operand 1 of 'avg2' on wrong side
+[^:]*:208: Error: operand 1 of 'avg2' on wrong side
+[^:]*:209: Error: 'avgu4' instruction not supported on this functional unit
+[^:]*:210: Error: bad number of operands to 'avgu4'
+[^:]*:211: Error: operand 1 of 'avgu4' on wrong side
+[^:]*:212: Error: operand 1 of 'avgu4' on wrong side
+[^:]*:213: Error: 'b' instruction not supported on this functional unit
+[^:]*:214: Error: too many operands to 'b'
+[^:]*:215: Error: 'call' instruction not supported on this functional unit
+[^:]*:216: Error: too many operands to 'call'
+[^:]*:217: Error: 'callret' instruction not supported on this functional unit
+[^:]*:218: Error: too many operands to 'callret'
+[^:]*:219: Error: 'ret' instruction not supported on this functional unit
+[^:]*:220: Error: too many operands to 'ret'
+[^:]*:221: Error: bad register for operand 1 of 'b'
+[^:]*:222: Error: 'b' instruction not supported on this functional unit
+[^:]*:223: Error: bad register for operand 1 of 'b'
+[^:]*:224: Error: 'b' instruction not supported on this functional unit
+[^:]*:225: Error: too many operands to 'bitc4'
+[^:]*:226: Error: 'bitc4' instruction not supported on this functional unit
+[^:]*:227: Error: operand 2 of 'bitc4' on wrong side
+[^:]*:228: Error: operand 1 of 'bitc4' on wrong side
+[^:]*:229: Error: bad number of operands to 'bitr'
+[^:]*:230: Error: 'bitr' instruction not supported on this functional unit
+[^:]*:231: Error: operand 2 of 'bitr' on wrong side
+[^:]*:232: Error: operand 1 of 'bitr' on wrong side
+[^:]*:233: Error: 'bnop' instruction not supported on this functional unit
+[^:]*:234: Error: 'bnop' instruction not supported on this functional unit
+[^:]*:235: Error: operand 2 of 'bnop' out of range
+[^:]*:236: Error: operand 2 of 'bnop' out of range
+[^:]*:237: Error: bad number of operands to 'bnop'
+[^:]*:238: Error: 'callnop' instruction not supported on this functional unit
+[^:]*:239: Error: 'callnop' instruction not supported on this functional unit
+[^:]*:240: Error: operand 2 of 'callnop' out of range
+[^:]*:241: Error: operand 2 of 'callnop' out of range
+[^:]*:242: Error: bad number of operands to 'callnop'
+[^:]*:243: Error: 'clr' instruction not supported on this functional unit
+[^:]*:244: Error: 'clr' instruction not supported on this functional unit
+[^:]*:245: Error: bad number of operands to 'clr'
+[^:]*:246: Error: bad register for operand 2 of 'clr'
+[^:]*:246: Error: bad register for operand 3 of 'clr'
+[^:]*:246: Error: too many operands to 'clr'
+[^:]*:247: Error: operand 2 of 'clr' on wrong side
+[^:]*:248: Error: 'cmpeq' instruction not supported on this functional unit
+[^:]*:249: Error: too many operands to 'cmpeq'
+[^:]*:250: Error: junk after operand 1 of 'cmpeq'
+[^:]*:251: Error: operand 1 of 'cmpeq' out of range
+[^:]*:252: Error: operand 1 of 'cmpeq' out of range
+[^:]*:253: Error: operand 1 of 'cmpeq' out of range
+[^:]*:254: Error: operand 1 of 'cmpeq' out of range
+[^:]*:255: Error: bad operand combination for 'cmpeq'
+[^:]*:256: Error: 'cmpeq2' instruction not supported on this functional unit
+[^:]*:257: Error: bad number of operands to 'cmpeq2'
+[^:]*:258: Error: operand 2 of 'cmpeq2' on wrong side
+[^:]*:259: Error: operand 2 of 'cmpeq2' on wrong side
+[^:]*:260: Error: 'cmpeq4' instruction not supported on this functional unit
+[^:]*:261: Error: bad number of operands to 'cmpeq4'
+[^:]*:262: Error: operand 1 of 'cmpeq4' on wrong side
+[^:]*:263: Error: operand 2 of 'cmpeq4' on wrong side
+[^:]*:264: Error: 'cmpeqdp' instruction not supported on this functional unit
+[^:]*:265: Error: bad number of operands to 'cmpeqdp'
+[^:]*:266: Error: bad register pair for operand 1 of 'cmpeqdp'
+[^:]*:266: Error: bad register pair for operand 2 of 'cmpeqdp'
+[^:]*:267: Error: operand 1 of 'cmpeqdp' on wrong side
+[^:]*:268: Error: operand 2 of 'cmpeqdp' on wrong side
+[^:]*:269: Error: bad number of operands to 'cmpeqsp'
+[^:]*:270: Error: 'cmpeqsp' instruction not supported on this functional unit
+[^:]*:271: Error: operand 2 of 'cmpeqsp' on wrong side
+[^:]*:272: Error: operand 1 of 'cmpeqsp' on wrong side
+[^:]*:273: Error: 'cmpgt' instruction not supported on this functional unit
+[^:]*:274: Error: too many operands to 'cmpgt'
+[^:]*:275: Error: bad operand combination for 'cmpgt'
+[^:]*:276: Error: operand 1 of 'cmpgt' out of range
+[^:]*:277: Error: operand 1 of 'cmpgt' out of range
+[^:]*:278: Error: operand 1 of 'cmpgt' out of range
+[^:]*:279: Error: operand 1 of 'cmpgt' out of range
+[^:]*:280: Error: bad operand combination for 'cmpgt'
+[^:]*:281: Error: 'cmpgt2' instruction not supported on this functional unit
+[^:]*:282: Error: bad number of operands to 'cmpgt2'
+[^:]*:283: Error: operand 1 of 'cmpgt2' on wrong side
+[^:]*:284: Error: operand 2 of 'cmpgt2' on wrong side
+[^:]*:285: Error: 'cmpgtdp' instruction not supported on this functional unit
+[^:]*:286: Error: bad number of operands to 'cmpgtdp'
+[^:]*:287: Error: operand 1 of 'cmpgtdp' on wrong side
+[^:]*:288: Error: operand 2 of 'cmpgtdp' on wrong side
+[^:]*:289: Error: 'cmpgtsp' instruction not supported on this functional unit
+[^:]*:290: Error: bad number of operands to 'cmpgtsp'
+[^:]*:291: Error: operand 1 of 'cmpgtsp' on wrong side
+[^:]*:292: Error: operand 2 of 'cmpgtsp' on wrong side
+[^:]*:293: Error: 'cmpgtu' instruction not supported on this functional unit
+[^:]*:294: Error: too many operands to 'cmpgtu'
+[^:]*:295: Error: junk after operand 1 of 'cmpgtu'
+[^:]*:296: Error: operand 1 of 'cmpgtu' out of range
+[^:]*:297: Error: operand 1 of 'cmpgtu' out of range
+[^:]*:298: Error: operand 1 of 'cmpgtu' out of range
+[^:]*:299: Error: operand 1 of 'cmpgtu' out of range
+[^:]*:300: Error: bad operand combination for 'cmpgtu'
+[^:]*:301: Error: 'cmpgtu4' instruction not supported on this functional unit
+[^:]*:302: Error: bad number of operands to 'cmpgtu4'
+[^:]*:303: Error: operand 3 of 'cmpgtu4' on wrong side
+[^:]*:304: Error: operand 2 of 'cmpgtu4' on wrong side
+[^:]*:305: Error: 'cmplt' instruction not supported on this functional unit
+[^:]*:306: Error: too many operands to 'cmplt'
+[^:]*:307: Error: bad operand combination for 'cmplt'
+[^:]*:308: Error: operand 1 of 'cmplt' out of range
+[^:]*:309: Error: operand 1 of 'cmplt' out of range
+[^:]*:310: Error: operand 1 of 'cmplt' out of range
+[^:]*:311: Error: operand 1 of 'cmplt' out of range
+[^:]*:312: Error: bad operand combination for 'cmplt'
+[^:]*:313: Error: 'cmplt2' instruction not supported on this functional unit
+[^:]*:314: Error: bad number of operands to 'cmplt2'
+[^:]*:315: Error: operand 2 of 'cmplt2' on wrong side
+[^:]*:316: Error: operand 1 of 'cmplt2' on wrong side
+[^:]*:317: Error: 'cmpltdp' instruction not supported on this functional unit
+[^:]*:318: Error: bad number of operands to 'cmpltdp'
+[^:]*:319: Error: operand 1 of 'cmpltdp' on wrong side
+[^:]*:320: Error: operand 2 of 'cmpltdp' on wrong side
+[^:]*:321: Error: 'cmpltsp' instruction not supported on this functional unit
+[^:]*:322: Error: bad number of operands to 'cmpltsp'
+[^:]*:323: Error: operand 1 of 'cmpltsp' on wrong side
+[^:]*:324: Error: operand 2 of 'cmpltsp' on wrong side
+[^:]*:325: Error: 'cmpltu' instruction not supported on this functional unit
+[^:]*:326: Error: too many operands to 'cmpltu'
+[^:]*:327: Error: junk after operand 1 of 'cmpltu'
+[^:]*:328: Error: operand 1 of 'cmpltu' out of range
+[^:]*:329: Error: operand 1 of 'cmpltu' out of range
+[^:]*:330: Error: operand 1 of 'cmpltu' out of range
+[^:]*:331: Error: operand 1 of 'cmpltu' out of range
+[^:]*:332: Error: bad operand combination for 'cmpltu'
+[^:]*:333: Error: 'cmpltu4' instruction not supported on this functional unit
+[^:]*:334: Error: bad number of operands to 'cmpltu4'
+[^:]*:335: Error: operand 3 of 'cmpltu4' on wrong side
+[^:]*:336: Error: operand 1 of 'cmpltu4' on wrong side
+[^:]*:337: Error: 'cmpy' instruction not supported on this functional unit
+[^:]*:338: Error: bad number of operands to 'cmpy'
+[^:]*:339: Error: operand 1 of 'cmpy' on wrong side
+[^:]*:340: Error: operand 2 of 'cmpy' on wrong side
+[^:]*:341: Error: 'cmpyr' instruction not supported on this functional unit
+[^:]*:342: Error: bad number of operands to 'cmpyr'
+[^:]*:343: Error: operand 1 of 'cmpyr' on wrong side
+[^:]*:344: Error: operand 2 of 'cmpyr' on wrong side
+[^:]*:345: Error: 'cmpyr1' instruction not supported on this functional unit
+[^:]*:346: Error: bad number of operands to 'cmpyr1'
+[^:]*:347: Error: operand 1 of 'cmpyr1' on wrong side
+[^:]*:348: Error: operand 2 of 'cmpyr1' on wrong side
+[^:]*:349: Error: 'ddotp4' instruction not supported on this functional unit
+[^:]*:350: Error: bad number of operands to 'ddotp4'
+[^:]*:351: Error: operand 2 of 'ddotp4' on wrong side
+[^:]*:352: Error: operand 1 of 'ddotp4' on wrong side
+[^:]*:353: Error: 'ddotph2' instruction not supported on this functional unit
+[^:]*:354: Error: bad number of operands to 'ddotph2'
+[^:]*:355: Error: operand 2 of 'ddotph2' on wrong side
+[^:]*:356: Error: operand 1 of 'ddotph2' on wrong side
+[^:]*:357: Error: 'ddotph2r' instruction not supported on this functional unit
+[^:]*:358: Error: bad number of operands to 'ddotph2r'
+[^:]*:359: Error: operand 2 of 'ddotph2r' on wrong side
+[^:]*:360: Error: operand 1 of 'ddotph2r' on wrong side
+[^:]*:361: Error: 'ddotpl2' instruction not supported on this functional unit
+[^:]*:362: Error: bad number of operands to 'ddotpl2'
+[^:]*:363: Error: operand 2 of 'ddotpl2' on wrong side
+[^:]*:364: Error: operand 1 of 'ddotpl2' on wrong side
+[^:]*:365: Error: 'ddotpl2r' instruction not supported on this functional unit
+[^:]*:366: Error: bad number of operands to 'ddotpl2r'
+[^:]*:367: Error: operand 2 of 'ddotpl2r' on wrong side
+[^:]*:368: Error: operand 1 of 'ddotpl2r' on wrong side
+[^:]*:369: Error: 'deal' instruction not supported on this functional unit
+[^:]*:370: Error: too many operands to 'deal'
+[^:]*:371: Error: operand 2 of 'deal' on wrong side
+[^:]*:372: Error: operand 1 of 'deal' on wrong side
+[^:]*:373: Error: 'dint' instruction not supported on this functional unit
+[^:]*:374: Error: too many operands to 'dint'
+[^:]*:375: Error: 'dmv' instruction not supported on this functional unit
+[^:]*:376: Error: bad number of operands to 'dmv'
+[^:]*:377: Error: operand 1 of 'dmv' on wrong side
+[^:]*:378: Error: operand 2 of 'dmv' on wrong side
+[^:]*:379: Error: 'dotp2' instruction not supported on this functional unit
+[^:]*:380: Error: bad number of operands to 'dotp2'
+[^:]*:381: Error: operand 1 of 'dotp2' on wrong side
+[^:]*:382: Error: operand 2 of 'dotp2' on wrong side
+[^:]*:383: Error: operand 1 of 'dotp2' on wrong side
+[^:]*:384: Error: operand 2 of 'dotp2' on wrong side
+[^:]*:385: Error: 'dotpn2' instruction not supported on this functional unit
+[^:]*:386: Error: bad number of operands to 'dotpn2'
+[^:]*:387: Error: operand 1 of 'dotpn2' on wrong side
+[^:]*:388: Error: operand 2 of 'dotpn2' on wrong side
+[^:]*:389: Error: 'dotpnrsu2' instruction not supported on this functional unit
+[^:]*:390: Error: bad number of operands to 'dotpnrsu2'
+[^:]*:391: Error: operand 1 of 'dotpnrsu2' on wrong side
+[^:]*:392: Error: operand 2 of 'dotpnrsu2' on wrong side
+[^:]*:393: Error: 'dotpnrus2' instruction not supported on this functional unit
+[^:]*:394: Error: bad number of operands to 'dotpnrus2'
+[^:]*:395: Error: operand 2 of 'dotpnrus2' on wrong side
+[^:]*:396: Error: operand 1 of 'dotpnrus2' on wrong side
+[^:]*:397: Error: 'dotprsu2' instruction not supported on this functional unit
+[^:]*:398: Error: bad number of operands to 'dotprsu2'
+[^:]*:399: Error: operand 1 of 'dotprsu2' on wrong side
+[^:]*:400: Error: operand 2 of 'dotprsu2' on wrong side
+[^:]*:401: Error: 'dotprus2' instruction not supported on this functional unit
+[^:]*:402: Error: bad number of operands to 'dotprus2'
+[^:]*:403: Error: operand 2 of 'dotprus2' on wrong side
+[^:]*:404: Error: operand 1 of 'dotprus2' on wrong side
+[^:]*:405: Error: 'dotpsu4' instruction not supported on this functional unit
+[^:]*:406: Error: bad number of operands to 'dotpsu4'
+[^:]*:407: Error: operand 1 of 'dotpsu4' on wrong side
+[^:]*:408: Error: operand 2 of 'dotpsu4' on wrong side
+[^:]*:409: Error: 'dotpus4' instruction not supported on this functional unit
+[^:]*:410: Error: bad number of operands to 'dotpus4'
+[^:]*:411: Error: operand 2 of 'dotpus4' on wrong side
+[^:]*:412: Error: operand 1 of 'dotpus4' on wrong side
+[^:]*:413: Error: 'dotpu4' instruction not supported on this functional unit
+[^:]*:414: Error: bad number of operands to 'dotpu4'
+[^:]*:415: Error: operand 1 of 'dotpu4' on wrong side
+[^:]*:416: Error: operand 2 of 'dotpu4' on wrong side
+[^:]*:417: Error: 'dpack2' instruction not supported on this functional unit
+[^:]*:418: Error: bad number of operands to 'dpack2'
+[^:]*:419: Error: operand 3 of 'dpack2' on wrong side
+[^:]*:420: Error: operand 2 of 'dpack2' on wrong side
+[^:]*:421: Error: 'dpackx2' instruction not supported on this functional unit
+[^:]*:422: Error: bad number of operands to 'dpackx2'
+[^:]*:423: Error: operand 3 of 'dpackx2' on wrong side
+[^:]*:424: Error: operand 2 of 'dpackx2' on wrong side
+[^:]*:425: Error: 'dpint' instruction not supported on this functional unit
+[^:]*:426: Error: 'dpint' instruction not supported on this functional unit
+[^:]*:427: Error: operand 1 of 'dpint' on wrong side
+[^:]*:428: Error: 'dpsp' instruction not supported on this functional unit
+[^:]*:429: Error: 'dpsp' instruction not supported on this functional unit
+[^:]*:430: Error: operand 1 of 'dpsp' on wrong side
+[^:]*:431: Error: 'dptrunc' instruction not supported on this functional unit
+[^:]*:432: Error: 'dptrunc' instruction not supported on this functional unit
+[^:]*:433: Error: operand 1 of 'dptrunc' on wrong side
+[^:]*:434: Error: 'ext' instruction not supported on this functional unit
+[^:]*:435: Error: 'ext' instruction not supported on this functional unit
+[^:]*:436: Error: bad number of operands to 'ext'
+[^:]*:437: Error: bad register for operand 2 of 'ext'
+[^:]*:437: Error: bad register for operand 3 of 'ext'
+[^:]*:437: Error: too many operands to 'ext'
+[^:]*:438: Error: operand 2 of 'ext' on wrong side
+[^:]*:439: Error: operand 2 of 'clr' out of range
+[^:]*:440: Error: operand 2 of 'clr' out of range
+[^:]*:441: Error: operand 3 of 'clr' out of range
+[^:]*:442: Error: operand 3 of 'clr' out of range
+[^:]*:443: Error: operand 2 of 'ext' out of range
+[^:]*:444: Error: operand 2 of 'ext' out of range
+[^:]*:445: Error: operand 3 of 'ext' out of range
+[^:]*:446: Error: operand 3 of 'ext' out of range
+[^:]*:447: Error: 'extu' instruction not supported on this functional unit
+[^:]*:448: Error: 'extu' instruction not supported on this functional unit
+[^:]*:449: Error: bad number of operands to 'extu'
+[^:]*:450: Error: bad register for operand 2 of 'extu'
+[^:]*:450: Error: bad register for operand 3 of 'extu'
+[^:]*:450: Error: too many operands to 'extu'
+[^:]*:451: Error: operand 2 of 'extu' on wrong side
+[^:]*:452: Error: operand 2 of 'extu' out of range
+[^:]*:453: Error: operand 2 of 'extu' out of range
+[^:]*:454: Error: operand 3 of 'extu' out of range
+[^:]*:455: Error: operand 3 of 'extu' out of range
+[^:]*:456: Error: 'gmpy' instruction not supported on this functional unit
+[^:]*:457: Error: bad number of operands to 'gmpy'
+[^:]*:458: Error: 'gmpy' instruction not supported on this functional unit
+[^:]*:459: Error: operand 1 of 'gmpy' on wrong side
+[^:]*:460: Error: 'gmpy4' instruction not supported on this functional unit
+[^:]*:461: Error: too many operands to 'gmpy4'
+[^:]*:462: Error: operand 1 of 'gmpy4' on wrong side
+[^:]*:463: Error: operand 2 of 'gmpy4' on wrong side
+[^:]*:464: Error: 'idle' instruction not supported on this functional unit
+[^:]*:465: Error: too many operands to 'idle'
+[^:]*:466: Error: 'intdp' instruction not supported on this functional unit
+[^:]*:467: Error: bad number of operands to 'intdp'
+[^:]*:468: Error: operand 2 of 'intdp' on wrong side
+[^:]*:469: Error: operand 2 of 'intdp' on wrong side
+[^:]*:470: Error: 'intdpu' instruction not supported on this functional unit
+[^:]*:471: Error: bad number of operands to 'intdpu'
+[^:]*:472: Error: operand 2 of 'intdpu' on wrong side
+[^:]*:473: Error: operand 2 of 'intdpu' on wrong side
+[^:]*:474: Error: 'intsp' instruction not supported on this functional unit
+[^:]*:475: Error: bad number of operands to 'intsp'
+[^:]*:476: Error: operand 2 of 'intsp' on wrong side
+[^:]*:477: Error: operand 2 of 'intsp' on wrong side
+[^:]*:478: Error: 'intspu' instruction not supported on this functional unit
+[^:]*:479: Error: bad number of operands to 'intspu'
+[^:]*:480: Error: operand 2 of 'intspu' on wrong side
+[^:]*:481: Error: operand 2 of 'intspu' on wrong side
+[^:]*:482: Error: 'cmtl' instruction not supported on this functional unit
+[^:]*:483: Error: 'cmtl' instruction not supported on this functional unit
+[^:]*:484: Error: 'cmtl' instruction not supported on this functional unit
+[^:]*:485: Error: operand 1 of 'cmtl' not a valid memory reference
+[^:]*:486: Error: operand 1 of 'cmtl' not a valid memory reference
+[^:]*:487: Error: operand 1 of 'cmtl' not a valid memory reference
+[^:]*:488: Error: operand 1 of 'cmtl' not a valid memory reference
+[^:]*:489: Error: operand 1 of 'cmtl' not a valid memory reference
+[^:]*:490: Error: operand 1 of 'cmtl' not a valid memory reference
+[^:]*:491: Error: operand 1 of 'cmtl' not a valid memory reference
+[^:]*:492: Error: operand 1 of 'cmtl' not a valid memory reference
+[^:]*:493: Error: operand 2 of 'cmtl' on wrong side
+[^:]*:494: Error: 'll' instruction not supported on this functional unit
+[^:]*:495: Error: 'll' instruction not supported on this functional unit
+[^:]*:496: Error: 'll' instruction not supported on this functional unit
+[^:]*:497: Error: operand 1 of 'll' not a valid memory reference
+[^:]*:498: Error: operand 1 of 'll' not a valid memory reference
+[^:]*:499: Error: operand 1 of 'll' not a valid memory reference
+[^:]*:500: Error: operand 1 of 'll' not a valid memory reference
+[^:]*:501: Error: operand 1 of 'll' not a valid memory reference
+[^:]*:502: Error: operand 1 of 'll' not a valid memory reference
+[^:]*:503: Error: operand 1 of 'll' not a valid memory reference
+[^:]*:504: Error: operand 1 of 'll' not a valid memory reference
+[^:]*:505: Error: operand 2 of 'll' on wrong side
+[^:]*:506: Error: 'sl' instruction not supported on this functional unit
+[^:]*:507: Error: 'sl' instruction not supported on this functional unit
+[^:]*:508: Error: 'sl' instruction not supported on this functional unit
+[^:]*:509: Error: operand 2 of 'sl' not a valid memory reference
+[^:]*:510: Error: operand 2 of 'sl' not a valid memory reference
+[^:]*:511: Error: operand 2 of 'sl' not a valid memory reference
+[^:]*:512: Error: operand 2 of 'sl' not a valid memory reference
+[^:]*:513: Error: operand 2 of 'sl' not a valid memory reference
+[^:]*:514: Error: operand 2 of 'sl' not a valid memory reference
+[^:]*:515: Error: operand 2 of 'sl' not a valid memory reference
+[^:]*:516: Error: operand 2 of 'sl' not a valid memory reference
+[^:]*:517: Error: operand 1 of 'sl' on wrong side
+[^:]*:518: Error: 'ldb' instruction not supported on this functional unit
+[^:]*:519: Error: operand 2 of 'ldb' on wrong side
+[^:]*:520: Error: operand 1 of 'ldb' not a valid memory reference
+[^:]*:521: Error: operand 1 of 'ldb' not a valid memory reference
+[^:]*:522: Error: operand 2 of 'ldb' on wrong side
+[^:]*:523: Error: bad number of operands to 'ldb'
+[^:]*:524: Error: operand 1 of 'ldb' not a valid memory reference
+[^:]*:525: Error: bad operand 1 of 'ldb'
+[^:]*:526: Error: bad operand 1 of 'ldb'
+[^:]*:527: Error: offset in operand 1 of 'ldb' out of range
+[^:]*:528: Error: offset in operand 1 of 'ldb' out of range
+[^:]*:529: Error: offset in operand 1 of 'ldb' out of range
+[^:]*:530: Error: offset in operand 1 of 'ldb' out of range
+[^:]*:531: Error: operand 1 of 'ldb' not a valid memory reference
+[^:]*:532: Error: operand 1 of 'ldb' not a valid memory reference
+[^:]*:533: Error: 'ldbu' instruction not supported on this functional unit
+[^:]*:534: Error: operand 2 of 'ldbu' on wrong side
+[^:]*:535: Error: operand 1 of 'ldbu' not a valid memory reference
+[^:]*:536: Error: operand 1 of 'ldbu' not a valid memory reference
+[^:]*:537: Error: operand 2 of 'ldbu' on wrong side
+[^:]*:538: Error: bad number of operands to 'ldbu'
+[^:]*:539: Error: operand 1 of 'ldbu' not a valid memory reference
+[^:]*:540: Error: bad operand 1 of 'ldbu'
+[^:]*:541: Error: bad operand 1 of 'ldbu'
+[^:]*:542: Error: offset in operand 1 of 'ldbu' out of range
+[^:]*:543: Error: offset in operand 1 of 'ldbu' out of range
+[^:]*:544: Error: offset in operand 1 of 'ldbu' out of range
+[^:]*:545: Error: offset in operand 1 of 'ldbu' out of range
+[^:]*:546: Error: operand 1 of 'ldbu' not a valid memory reference
+[^:]*:547: Error: operand 1 of 'ldbu' not a valid memory reference
+[^:]*:548: Error: 'lddw' instruction not supported on this functional unit
+[^:]*:549: Error: operand 2 of 'lddw' on wrong side
+[^:]*:550: Error: operand 1 of 'lddw' not a valid memory reference
+[^:]*:551: Error: operand 1 of 'lddw' not a valid memory reference
+[^:]*:552: Error: operand 2 of 'lddw' on wrong side
+[^:]*:553: Error: bad number of operands to 'lddw'
+[^:]*:554: Error: operand 1 of 'lddw' not a valid memory reference
+[^:]*:555: Error: bad operand 1 of 'lddw'
+[^:]*:556: Error: bad operand 1 of 'lddw'
+[^:]*:557: Error: offset in operand 1 of 'lddw' out of range
+[^:]*:558: Error: offset in operand 1 of 'lddw' out of range
+[^:]*:559: Error: offset in operand 1 of 'lddw' out of range
+[^:]*:560: Error: offset in operand 1 of 'lddw' out of range
+[^:]*:561: Error: operand 1 of 'lddw' not a valid memory reference
+[^:]*:562: Error: operand 1 of 'lddw' not a valid memory reference
+[^:]*:563: Error: offset in operand 1 of 'lddw' not divisible by 8
+[^:]*:564: Error: operand 1 of 'lddw' not a valid memory reference
+[^:]*:565: Error: 'ldh' instruction not supported on this functional unit
+[^:]*:566: Error: operand 2 of 'ldh' on wrong side
+[^:]*:567: Error: operand 1 of 'ldh' not a valid memory reference
+[^:]*:568: Error: operand 1 of 'ldh' not a valid memory reference
+[^:]*:569: Error: operand 2 of 'ldh' on wrong side
+[^:]*:570: Error: bad number of operands to 'ldh'
+[^:]*:571: Error: operand 1 of 'ldh' not a valid memory reference
+[^:]*:572: Error: bad operand 1 of 'ldh'
+[^:]*:573: Error: bad operand 1 of 'ldh'
+[^:]*:574: Error: offset in operand 1 of 'ldh' out of range
+[^:]*:575: Error: offset in operand 1 of 'ldh' out of range
+[^:]*:576: Error: offset in operand 1 of 'ldh' out of range
+[^:]*:577: Error: offset in operand 1 of 'ldh' out of range
+[^:]*:578: Error: operand 1 of 'ldh' not a valid memory reference
+[^:]*:579: Error: operand 1 of 'ldh' not a valid memory reference
+[^:]*:580: Error: offset in operand 1 of 'ldh' not divisible by 2
+[^:]*:581: Error: 'ldhu' instruction not supported on this functional unit
+[^:]*:582: Error: operand 2 of 'ldhu' on wrong side
+[^:]*:583: Error: operand 1 of 'ldhu' not a valid memory reference
+[^:]*:584: Error: operand 1 of 'ldhu' not a valid memory reference
+[^:]*:585: Error: operand 2 of 'ldhu' on wrong side
+[^:]*:586: Error: bad number of operands to 'ldhu'
+[^:]*:587: Error: operand 1 of 'ldhu' not a valid memory reference
+[^:]*:588: Error: bad operand 1 of 'ldhu'
+[^:]*:589: Error: bad operand 1 of 'ldhu'
+[^:]*:590: Error: offset in operand 1 of 'ldhu' out of range
+[^:]*:591: Error: offset in operand 1 of 'ldhu' out of range
+[^:]*:592: Error: offset in operand 1 of 'ldhu' out of range
+[^:]*:593: Error: offset in operand 1 of 'ldhu' out of range
+[^:]*:594: Error: operand 1 of 'ldhu' not a valid memory reference
+[^:]*:595: Error: operand 1 of 'ldhu' not a valid memory reference
+[^:]*:596: Error: offset in operand 1 of 'ldhu' not divisible by 2
+[^:]*:597: Error: 'ldndw' instruction not supported on this functional unit
+[^:]*:598: Error: operand 2 of 'ldndw' on wrong side
+[^:]*:599: Error: operand 1 of 'ldndw' not a valid memory reference
+[^:]*:600: Error: operand 1 of 'ldndw' not a valid memory reference
+[^:]*:601: Error: operand 2 of 'ldndw' on wrong side
+[^:]*:602: Error: bad number of operands to 'ldndw'
+[^:]*:603: Error: operand 1 of 'ldndw' not a valid memory reference
+[^:]*:604: Error: bad operand 1 of 'ldndw'
+[^:]*:605: Error: bad operand 1 of 'ldndw'
+[^:]*:606: Error: offset in operand 1 of 'ldndw' out of range
+[^:]*:607: Error: offset in operand 1 of 'ldndw' out of range
+[^:]*:608: Error: offset in operand 1 of 'ldndw' out of range
+[^:]*:609: Error: offset in operand 1 of 'ldndw' out of range
+[^:]*:610: Error: operand 1 of 'ldndw' not a valid memory reference
+[^:]*:611: Error: 'ldnw' instruction not supported on this functional unit
+[^:]*:612: Error: operand 2 of 'ldnw' on wrong side
+[^:]*:613: Error: operand 1 of 'ldnw' not a valid memory reference
+[^:]*:614: Error: operand 1 of 'ldnw' not a valid memory reference
+[^:]*:615: Error: operand 2 of 'ldnw' on wrong side
+[^:]*:616: Error: bad number of operands to 'ldnw'
+[^:]*:617: Error: operand 1 of 'ldnw' not a valid memory reference
+[^:]*:618: Error: bad operand 1 of 'ldnw'
+[^:]*:619: Error: bad operand 1 of 'ldnw'
+[^:]*:620: Error: offset in operand 1 of 'ldnw' out of range
+[^:]*:621: Error: offset in operand 1 of 'ldnw' out of range
+[^:]*:622: Error: offset in operand 1 of 'ldnw' out of range
+[^:]*:623: Error: offset in operand 1 of 'ldnw' out of range
+[^:]*:624: Error: operand 1 of 'ldnw' not a valid memory reference
+[^:]*:625: Error: operand 1 of 'ldnw' not a valid memory reference
+[^:]*:626: Error: offset in operand 1 of 'ldnw' not divisible by 4
+[^:]*:627: Error: 'ldw' instruction not supported on this functional unit
+[^:]*:628: Error: operand 2 of 'ldw' on wrong side
+[^:]*:629: Error: operand 1 of 'ldw' not a valid memory reference
+[^:]*:630: Error: operand 1 of 'ldw' not a valid memory reference
+[^:]*:631: Error: operand 2 of 'ldw' on wrong side
+[^:]*:632: Error: bad number of operands to 'ldw'
+[^:]*:633: Error: operand 1 of 'ldw' not a valid memory reference
+[^:]*:634: Error: bad operand 1 of 'ldw'
+[^:]*:635: Error: bad operand 1 of 'ldw'
+[^:]*:636: Error: offset in operand 1 of 'ldw' out of range
+[^:]*:637: Error: offset in operand 1 of 'ldw' out of range
+[^:]*:638: Error: offset in operand 1 of 'ldw' out of range
+[^:]*:639: Error: offset in operand 1 of 'ldw' out of range
+[^:]*:640: Error: operand 1 of 'ldw' not a valid memory reference
+[^:]*:641: Error: operand 1 of 'ldw' not a valid memory reference
+[^:]*:642: Error: offset in operand 1 of 'ldw' not divisible by 4
+[^:]*:643: Error: operand 1 of 'ldb' out of range
+[^:]*:644: Error: operand 1 of 'ldb' out of range
+[^:]*:645: Error: operand 1 of 'ldbu' out of range
+[^:]*:646: Error: operand 1 of 'ldbu' out of range
+[^:]*:647: Error: operand 1 of 'ldh' out of range
+[^:]*:648: Error: operand 1 of 'ldh' out of range
+[^:]*:649: Error: operand 1 of 'ldhu' out of range
+[^:]*:650: Error: operand 1 of 'ldhu' out of range
+[^:]*:651: Error: operand 1 of 'ldw' out of range
+[^:]*:652: Error: operand 1 of 'ldw' out of range
+[^:]*:653: Error: 'lmbd' instruction not supported on this functional unit
+[^:]*:654: Error: bad number of operands to 'lmbd'
+[^:]*:655: Error: operand 1 of 'lmbd' on wrong side
+[^:]*:656: Error: operand 2 of 'lmbd' on wrong side
+[^:]*:657: Error: operand 1 of 'lmbd' out of range
+[^:]*:658: Error: operand 1 of 'lmbd' out of range
+[^:]*:659: Error: 'max2' instruction not supported on this functional unit
+[^:]*:660: Error: bad number of operands to 'max2'
+[^:]*:661: Error: operand 1 of 'max2' on wrong side
+[^:]*:662: Error: operand 2 of 'max2' on wrong side
+[^:]*:663: Error: operand 2 of 'max2' on wrong side
+[^:]*:664: Error: operand 1 of 'max2' on wrong side
+[^:]*:665: Error: 'maxu4' instruction not supported on this functional unit
+[^:]*:666: Error: bad number of operands to 'maxu4'
+[^:]*:667: Error: operand 1 of 'maxu4' on wrong side
+[^:]*:668: Error: operand 2 of 'maxu4' on wrong side
+[^:]*:669: Error: 'min2' instruction not supported on this functional unit
+[^:]*:670: Error: bad number of operands to 'min2'
+[^:]*:671: Error: operand 1 of 'min2' on wrong side
+[^:]*:672: Error: operand 2 of 'min2' on wrong side
+[^:]*:673: Error: operand 2 of 'min2' on wrong side
+[^:]*:674: Error: operand 1 of 'min2' on wrong side
+[^:]*:675: Error: 'minu4' instruction not supported on this functional unit
+[^:]*:676: Error: bad number of operands to 'minu4'
+[^:]*:677: Error: operand 1 of 'minu4' on wrong side
+[^:]*:678: Error: operand 2 of 'minu4' on wrong side
+[^:]*:679: Error: 'mpy' instruction not supported on this functional unit
+[^:]*:680: Error: bad number of operands to 'mpy'
+[^:]*:681: Error: operand 1 of 'mpy' on wrong side
+[^:]*:682: Error: operand 2 of 'mpy' on wrong side
+[^:]*:683: Error: operand 1 of 'mpy' out of range
+[^:]*:684: Error: operand 1 of 'mpy' out of range
+[^:]*:685: Error: operand 2 of 'mpy' on wrong side
+[^:]*:686: Error: 'mpydp' instruction not supported on this functional unit
+[^:]*:687: Error: bad number of operands to 'mpydp'
+[^:]*:688: Error: operand 1 of 'mpydp' on wrong side
+[^:]*:689: Error: 'mpydp' instruction not supported on this functional unit
+[^:]*:690: Error: 'mpyh' instruction not supported on this functional unit
+[^:]*:691: Error: bad number of operands to 'mpyh'
+[^:]*:692: Error: operand 1 of 'mpyh' on wrong side
+[^:]*:693: Error: operand 2 of 'mpyh' on wrong side
+[^:]*:694: Error: 'mpyhi' instruction not supported on this functional unit
+[^:]*:695: Error: bad number of operands to 'mpyhi'
+[^:]*:696: Error: operand 1 of 'mpyhi' on wrong side
+[^:]*:697: Error: operand 2 of 'mpyhi' on wrong side
+[^:]*:698: Error: 'mpyhir' instruction not supported on this functional unit
+[^:]*:699: Error: bad number of operands to 'mpyhir'
+[^:]*:700: Error: operand 1 of 'mpyhir' on wrong side
+[^:]*:701: Error: operand 2 of 'mpyhir' on wrong side
+[^:]*:702: Error: 'mpyhl' instruction not supported on this functional unit
+[^:]*:703: Error: bad number of operands to 'mpyhl'
+[^:]*:704: Error: operand 1 of 'mpyhl' on wrong side
+[^:]*:705: Error: operand 2 of 'mpyhl' on wrong side
+[^:]*:706: Error: 'mpyhlu' instruction not supported on this functional unit
+[^:]*:707: Error: bad number of operands to 'mpyhlu'
+[^:]*:708: Error: operand 1 of 'mpyhlu' on wrong side
+[^:]*:709: Error: operand 2 of 'mpyhlu' on wrong side
+[^:]*:710: Error: 'mpyhslu' instruction not supported on this functional unit
+[^:]*:711: Error: bad number of operands to 'mpyhslu'
+[^:]*:712: Error: operand 1 of 'mpyhslu' on wrong side
+[^:]*:713: Error: operand 2 of 'mpyhslu' on wrong side
+[^:]*:714: Error: 'mpyhsu' instruction not supported on this functional unit
+[^:]*:715: Error: bad number of operands to 'mpyhsu'
+[^:]*:716: Error: operand 1 of 'mpyhsu' on wrong side
+[^:]*:717: Error: operand 2 of 'mpyhsu' on wrong side
+[^:]*:718: Error: 'mpyhu' instruction not supported on this functional unit
+[^:]*:719: Error: bad number of operands to 'mpyhu'
+[^:]*:720: Error: operand 1 of 'mpyhu' on wrong side
+[^:]*:721: Error: operand 2 of 'mpyhu' on wrong side
+[^:]*:722: Error: 'mpyhuls' instruction not supported on this functional unit
+[^:]*:723: Error: bad number of operands to 'mpyhuls'
+[^:]*:724: Error: operand 1 of 'mpyhuls' on wrong side
+[^:]*:725: Error: operand 2 of 'mpyhuls' on wrong side
+[^:]*:726: Error: 'mpyhus' instruction not supported on this functional unit
+[^:]*:727: Error: bad number of operands to 'mpyhus'
+[^:]*:728: Error: operand 1 of 'mpyhus' on wrong side
+[^:]*:729: Error: operand 2 of 'mpyhus' on wrong side
+[^:]*:730: Error: 'mpyi' instruction not supported on this functional unit
+[^:]*:731: Error: bad number of operands to 'mpyi'
+[^:]*:732: Error: operand 1 of 'mpyi' on wrong side
+[^:]*:733: Error: operand 2 of 'mpyi' on wrong side
+[^:]*:734: Error: operand 1 of 'mpyi' out of range
+[^:]*:735: Error: operand 1 of 'mpyi' out of range
+[^:]*:736: Error: 'mpyid' instruction not supported on this functional unit
+[^:]*:737: Error: bad number of operands to 'mpyid'
+[^:]*:738: Error: operand 1 of 'mpyid' on wrong side
+[^:]*:739: Error: operand 2 of 'mpyid' on wrong side
+[^:]*:740: Error: operand 1 of 'mpyid' out of range
+[^:]*:741: Error: operand 1 of 'mpyid' out of range
+[^:]*:742: Error: 'mpyih' instruction not supported on this functional unit
+[^:]*:743: Error: bad number of operands to 'mpyih'
+[^:]*:744: Error: operand 1 of 'mpyih' on wrong side
+[^:]*:745: Error: operand 1 of 'mpyih' on wrong side
+[^:]*:746: Error: 'mpyihr' instruction not supported on this functional unit
+[^:]*:747: Error: bad number of operands to 'mpyihr'
+[^:]*:748: Error: operand 1 of 'mpyihr' on wrong side
+[^:]*:749: Error: operand 1 of 'mpyihr' on wrong side
+[^:]*:750: Error: 'mpyil' instruction not supported on this functional unit
+[^:]*:751: Error: bad number of operands to 'mpyil'
+[^:]*:752: Error: operand 1 of 'mpyil' on wrong side
+[^:]*:753: Error: operand 1 of 'mpyil' on wrong side
+[^:]*:754: Error: 'mpyilr' instruction not supported on this functional unit
+[^:]*:755: Error: bad number of operands to 'mpyilr'
+[^:]*:756: Error: operand 1 of 'mpyilr' on wrong side
+[^:]*:757: Error: operand 1 of 'mpyilr' on wrong side
+[^:]*:758: Error: 'mpylh' instruction not supported on this functional unit
+[^:]*:759: Error: bad number of operands to 'mpylh'
+[^:]*:760: Error: operand 1 of 'mpylh' on wrong side
+[^:]*:761: Error: operand 2 of 'mpylh' on wrong side
+[^:]*:762: Error: 'mpylhu' instruction not supported on this functional unit
+[^:]*:763: Error: bad number of operands to 'mpylhu'
+[^:]*:764: Error: operand 1 of 'mpylhu' on wrong side
+[^:]*:765: Error: operand 2 of 'mpylhu' on wrong side
+[^:]*:766: Error: 'mpyli' instruction not supported on this functional unit
+[^:]*:767: Error: bad number of operands to 'mpyli'
+[^:]*:768: Error: operand 1 of 'mpyli' on wrong side
+[^:]*:769: Error: operand 2 of 'mpyli' on wrong side
+[^:]*:770: Error: 'mpylir' instruction not supported on this functional unit
+[^:]*:771: Error: bad number of operands to 'mpylir'
+[^:]*:772: Error: operand 1 of 'mpylir' on wrong side
+[^:]*:773: Error: operand 2 of 'mpylir' on wrong side
+[^:]*:774: Error: 'mpylshu' instruction not supported on this functional unit
+[^:]*:775: Error: bad number of operands to 'mpylshu'
+[^:]*:776: Error: operand 1 of 'mpylshu' on wrong side
+[^:]*:777: Error: operand 2 of 'mpylshu' on wrong side
+[^:]*:778: Error: 'mpyluhs' instruction not supported on this functional unit
+[^:]*:779: Error: bad number of operands to 'mpyluhs'
+[^:]*:780: Error: operand 1 of 'mpyluhs' on wrong side
+[^:]*:781: Error: operand 2 of 'mpyluhs' on wrong side
+[^:]*:782: Error: 'mpysp' instruction not supported on this functional unit
+[^:]*:783: Error: bad number of operands to 'mpysp'
+[^:]*:784: Error: operand 1 of 'mpysp' on wrong side
+[^:]*:785: Error: operand 2 of 'mpysp' on wrong side
+[^:]*:786: Error: 'mpyspdp' instruction not supported on this functional unit
+[^:]*:787: Error: too many operands to 'mpyspdp'
+[^:]*:788: Error: operand 1 of 'mpyspdp' on wrong side
+[^:]*:789: Error: operand 2 of 'mpyspdp' on wrong side
+[^:]*:790: Error: 'mpysp2dp' instruction not supported on this functional unit
+[^:]*:791: Error: bad number of operands to 'mpysp2dp'
+[^:]*:792: Error: operand 1 of 'mpysp2dp' on wrong side
+[^:]*:793: Error: operand 2 of 'mpysp2dp' on wrong side
+[^:]*:794: Error: 'mpysu' instruction not supported on this functional unit
+[^:]*:795: Error: bad number of operands to 'mpysu'
+[^:]*:796: Error: operand 1 of 'mpysu' on wrong side
+[^:]*:797: Error: operand 2 of 'mpysu' on wrong side
+[^:]*:798: Error: operand 1 of 'mpysu' out of range
+[^:]*:799: Error: operand 1 of 'mpysu' out of range
+[^:]*:800: Error: 'mpysu4' instruction not supported on this functional unit
+[^:]*:801: Error: bad number of operands to 'mpysu4'
+[^:]*:802: Error: operand 1 of 'mpysu4' on wrong side
+[^:]*:803: Error: operand 2 of 'mpysu4' on wrong side
+[^:]*:804: Error: 'mpyu' instruction not supported on this functional unit
+[^:]*:805: Error: bad number of operands to 'mpyu'
+[^:]*:806: Error: operand 1 of 'mpyu' on wrong side
+[^:]*:807: Error: operand 2 of 'mpyu' on wrong side
+[^:]*:808: Error: 'mpyu4' instruction not supported on this functional unit
+[^:]*:809: Error: bad number of operands to 'mpyu4'
+[^:]*:810: Error: operand 1 of 'mpyu4' on wrong side
+[^:]*:811: Error: operand 2 of 'mpyu4' on wrong side
+[^:]*:812: Error: 'mpyus' instruction not supported on this functional unit
+[^:]*:813: Error: bad number of operands to 'mpyus'
+[^:]*:814: Error: operand 1 of 'mpyus' on wrong side
+[^:]*:815: Error: operand 2 of 'mpyus' on wrong side
+[^:]*:816: Error: 'mpyus4' instruction not supported on this functional unit
+[^:]*:817: Error: bad number of operands to 'mpyus4'
+[^:]*:818: Error: operand 1 of 'mpyus4' on wrong side
+[^:]*:819: Error: operand 1 of 'mpyus4' on wrong side
+[^:]*:820: Error: 'mpy2' instruction not supported on this functional unit
+[^:]*:821: Error: bad number of operands to 'mpy2'
+[^:]*:822: Error: operand 1 of 'mpy2' on wrong side
+[^:]*:823: Error: operand 2 of 'mpy2' on wrong side
+[^:]*:824: Error: 'mpy2ir' instruction not supported on this functional unit
+[^:]*:825: Error: bad number of operands to 'mpy2ir'
+[^:]*:826: Error: operand 1 of 'mpy2ir' on wrong side
+[^:]*:827: Error: operand 2 of 'mpy2ir' on wrong side
+[^:]*:828: Error: 'mpy32' instruction not supported on this functional unit
+[^:]*:829: Error: bad number of operands to 'mpy32'
+[^:]*:830: Error: operand 1 of 'mpy32' on wrong side
+[^:]*:831: Error: operand 2 of 'mpy32' on wrong side
+[^:]*:832: Error: operand 1 of 'mpy32' on wrong side
+[^:]*:833: Error: operand 2 of 'mpy32' on wrong side
+[^:]*:834: Error: 'mpy32su' instruction not supported on this functional unit
+[^:]*:835: Error: bad number of operands to 'mpy32su'
+[^:]*:836: Error: operand 2 of 'mpy32su' on wrong side
+[^:]*:837: Error: operand 1 of 'mpy32su' on wrong side
+[^:]*:838: Error: 'mpy32u' instruction not supported on this functional unit
+[^:]*:839: Error: bad number of operands to 'mpy32u'
+[^:]*:840: Error: operand 2 of 'mpy32u' on wrong side
+[^:]*:841: Error: operand 1 of 'mpy32u' on wrong side
+[^:]*:842: Error: 'mpy32us' instruction not supported on this functional unit
+[^:]*:843: Error: bad number of operands to 'mpy32us'
+[^:]*:844: Error: operand 2 of 'mpy32us' on wrong side
+[^:]*:845: Error: operand 1 of 'mpy32us' on wrong side
+[^:]*:846: Error: 'mvc' instruction not supported on this functional unit
+[^:]*:847: Error: bad register for operand 1 of 'mvc'
+[^:]*:847: Error: bad operand 2 of 'mvc'
+[^:]*:848: Error: bad register for operand 2 of 'mvc'
+[^:]*:849: Error: operand 2 of 'mvc' is read-only
+[^:]*:850: Error: operand 1 of 'mvc' is write-only
+[^:]*:851: Error: operand 2 of 'mvc' is read-only
+[^:]*:852: Error: operand 1 of 'mvc' is write-only
+[^:]*:853: Error: operand 2 of 'mvc' is read-only
+[^:]*:854: Error: operand 1 of 'mvc' is write-only
+[^:]*:855: Error: operand 2 of 'mvc' is read-only
+[^:]*:856: Error: operand 2 of 'mvc' is read-only
+[^:]*:857: Error: operand 2 of 'mvc' is read-only
+[^:]*:858: Error: 'mv' instruction not supported on this functional unit
+[^:]*:859: Error: too many operands to 'mv'
+[^:]*:860: Error: operand 2 of 'mv' on wrong side
+[^:]*:861: Error: operand 1 of 'mv' on wrong side
+[^:]*:862: Error: operand 2 of 'mv' on wrong side
+[^:]*:863: Error: operand 1 of 'mv' on wrong side
+[^:]*:864: Error: operand 2 of 'mv' on wrong side
+[^:]*:865: Error: operand 1 of 'mv' on wrong side
+[^:]*:866: Error: 'mvd' instruction not supported on this functional unit
+[^:]*:867: Error: too many operands to 'mvd'
+[^:]*:868: Error: operand 2 of 'mvd' on wrong side
+[^:]*:869: Error: operand 1 of 'mvd' on wrong side
+[^:]*:870: Error: operand 1 of 'mvk' out of range
+[^:]*:871: Error: operand 1 of 'mvk' out of range
+[^:]*:872: Error: 'mvk' instruction not supported on this functional unit
+[^:]*:873: Error: operand 1 of 'mvk' out of range
+[^:]*:874: Error: operand 1 of 'mvk' out of range
+[^:]*:875: Error: 'mvk' instruction not supported on this functional unit
+[^:]*:876: Error: 'norm' instruction not supported on this functional unit
+[^:]*:877: Error: too many operands to 'norm'
+[^:]*:878: Error: bad register for operand 1 of 'norm'
+[^:]*:879: Error: operand 2 of 'norm' on wrong side
+[^:]*:880: Error: operand 1 of 'norm' on wrong side
+[^:]*:881: Error: 'or' instruction not supported on this functional unit
+[^:]*:882: Error: bad number of operands to 'or'
+[^:]*:883: Error: operand 1 of 'or' out of range
+[^:]*:884: Error: operand 1 of 'or' out of range
+[^:]*:885: Error: operand 1 of 'or' out of range
+[^:]*:886: Error: operand 1 of 'or' out of range
+[^:]*:887: Error: operand 1 of 'or' out of range
+[^:]*:888: Error: operand 1 of 'or' out of range
+[^:]*:889: Error: operand 3 of 'or' on wrong side
+[^:]*:890: Error: operand 2 of 'or' on wrong side
+[^:]*:891: Error: operand 2 of 'or' on wrong side
+[^:]*:892: Error: operand 3 of 'or' on wrong side
+[^:]*:893: Error: 'pack2' instruction not supported on this functional unit
+[^:]*:894: Error: bad number of operands to 'pack2'
+[^:]*:895: Error: operand 3 of 'pack2' on wrong side
+[^:]*:896: Error: operand 2 of 'pack2' on wrong side
+[^:]*:897: Error: 'packh2' instruction not supported on this functional unit
+[^:]*:898: Error: bad number of operands to 'packh2'
+[^:]*:899: Error: operand 3 of 'packh2' on wrong side
+[^:]*:900: Error: operand 2 of 'packh2' on wrong side
+[^:]*:901: Error: 'packh4' instruction not supported on this functional unit
+[^:]*:902: Error: bad number of operands to 'packh4'
+[^:]*:903: Error: operand 3 of 'packh4' on wrong side
+[^:]*:904: Error: operand 2 of 'packh4' on wrong side
+[^:]*:905: Error: 'packhl2' instruction not supported on this functional unit
+[^:]*:906: Error: bad number of operands to 'packhl2'
+[^:]*:907: Error: operand 3 of 'packhl2' on wrong side
+[^:]*:908: Error: operand 2 of 'packhl2' on wrong side
+[^:]*:909: Error: 'packlh2' instruction not supported on this functional unit
+[^:]*:910: Error: bad number of operands to 'packlh2'
+[^:]*:911: Error: operand 3 of 'packlh2' on wrong side
+[^:]*:912: Error: operand 2 of 'packlh2' on wrong side
+[^:]*:913: Error: 'packl4' instruction not supported on this functional unit
+[^:]*:914: Error: bad number of operands to 'packl4'
+[^:]*:915: Error: operand 3 of 'packl4' on wrong side
+[^:]*:916: Error: operand 2 of 'packl4' on wrong side
+[^:]*:917: Error: 'rcpdp' instruction not supported on this functional unit
+[^:]*:918: Error: bad number of operands to 'rcpdp'
+[^:]*:919: Error: operand 1 of 'rcpdp' on wrong side
+[^:]*:920: Error: 'rcpdp' instruction not supported on this functional unit
+[^:]*:921: Error: 'rcpsp' instruction not supported on this functional unit
+[^:]*:922: Error: too many operands to 'rcpsp'
+[^:]*:923: Error: operand 2 of 'rcpsp' on wrong side
+[^:]*:924: Error: operand 1 of 'rcpsp' on wrong side
+[^:]*:925: Error: 'rint' instruction not supported on this functional unit
+[^:]*:926: Error: too many operands to 'rint'
+[^:]*:927: Error: 'rotl' instruction not supported on this functional unit
+[^:]*:928: Error: bad number of operands to 'rotl'
+[^:]*:929: Error: operand 2 of 'rotl' on wrong side
+[^:]*:930: Error: operand 1 of 'rotl' on wrong side
+[^:]*:931: Error: operand 2 of 'rotl' out of range
+[^:]*:932: Error: operand 2 of 'rotl' out of range
+[^:]*:933: Error: operand 1 of 'rotl' on wrong side
+[^:]*:934: Error: 'rpack2' instruction not supported on this functional unit
+[^:]*:935: Error: bad number of operands to 'rpack2'
+[^:]*:936: Error: operand 1 of 'rpack2' on wrong side
+[^:]*:937: Error: operand 2 of 'rpack2' on wrong side
+[^:]*:938: Error: 'rsqrdp' instruction not supported on this functional unit
+[^:]*:939: Error: bad number of operands to 'rsqrdp'
+[^:]*:940: Error: operand 1 of 'rsqrdp' on wrong side
+[^:]*:941: Error: 'rsqrdp' instruction not supported on this functional unit
+[^:]*:942: Error: 'rsqrsp' instruction not supported on this functional unit
+[^:]*:943: Error: too many operands to 'rsqrsp'
+[^:]*:944: Error: operand 2 of 'rsqrsp' on wrong side
+[^:]*:945: Error: operand 1 of 'rsqrsp' on wrong side
+[^:]*:946: Error: 'sadd' instruction not supported on this functional unit
+[^:]*:947: Error: bad number of operands to 'sadd'
+[^:]*:948: Error: bad register for operand 1 of 'sadd'
+[^:]*:949: Error: bad operand combination for 'sadd'
+[^:]*:950: Error: operand 1 of 'sadd' on wrong side
+[^:]*:951: Error: operand 2 of 'sadd' on wrong side
+[^:]*:952: Error: operand 1 of 'sadd' out of range
+[^:]*:953: Error: operand 1 of 'sadd' out of range
+[^:]*:954: Error: operand 1 of 'sadd' out of range
+[^:]*:955: Error: operand 1 of 'sadd' out of range
+[^:]*:956: Error: 'sadd2' instruction not supported on this functional unit
+[^:]*:957: Error: bad number of operands to 'sadd2'
+[^:]*:958: Error: operand 1 of 'sadd2' on wrong side
+[^:]*:959: Error: operand 2 of 'sadd2' on wrong side
+[^:]*:960: Error: 'saddsub' instruction not supported on this functional unit
+[^:]*:961: Error: bad number of operands to 'saddsub'
+[^:]*:962: Error: bad register pair for operand 3 of 'saddsub'
+[^:]*:963: Error: operand 1 of 'saddsub' on wrong side
+[^:]*:964: Error: operand 2 of 'saddsub' on wrong side
+[^:]*:965: Error: 'saddsub2' instruction not supported on this functional unit
+[^:]*:966: Error: bad number of operands to 'saddsub2'
+[^:]*:967: Error: bad register pair for operand 3 of 'saddsub2'
+[^:]*:968: Error: operand 1 of 'saddsub2' on wrong side
+[^:]*:969: Error: operand 2 of 'saddsub2' on wrong side
+[^:]*:970: Error: 'saddsu2' instruction not supported on this functional unit
+[^:]*:971: Error: bad number of operands to 'saddsu2'
+[^:]*:972: Error: operand 2 of 'saddsu2' on wrong side
+[^:]*:973: Error: operand 1 of 'saddsu2' on wrong side
+[^:]*:974: Error: 'saddus2' instruction not supported on this functional unit
+[^:]*:975: Error: bad number of operands to 'saddus2'
+[^:]*:976: Error: operand 1 of 'saddus2' on wrong side
+[^:]*:977: Error: operand 2 of 'saddus2' on wrong side
+[^:]*:978: Error: 'saddu4' instruction not supported on this functional unit
+[^:]*:979: Error: bad number of operands to 'saddu4'
+[^:]*:980: Error: operand 1 of 'saddu4' on wrong side
+[^:]*:981: Error: operand 2 of 'saddu4' on wrong side
+[^:]*:982: Error: 'sat' instruction not supported on this functional unit
+[^:]*:983: Error: 'sat' instruction not supported on this functional unit
+[^:]*:984: Error: bad number of operands to 'sat'
+[^:]*:985: Error: operand 1 of 'sat' on wrong side
+[^:]*:986: Error: 'set' instruction not supported on this functional unit
+[^:]*:987: Error: bad number of operands to 'set'
+[^:]*:988: Error: operand 2 of 'set' out of range
+[^:]*:989: Error: operand 2 of 'set' out of range
+[^:]*:990: Error: operand 3 of 'set' out of range
+[^:]*:991: Error: operand 3 of 'set' out of range
+[^:]*:992: Error: bad register for operand 2 of 'set'
+[^:]*:992: Error: bad register for operand 3 of 'set'
+[^:]*:992: Error: too many operands to 'set'
+[^:]*:993: Error: operand 1 of 'set' on wrong side
+[^:]*:994: Error: operand 2 of 'set' on wrong side
+[^:]*:995: Error: 'shfl' instruction not supported on this functional unit
+[^:]*:996: Error: too many operands to 'shfl'
+[^:]*:997: Error: operand 2 of 'shfl' on wrong side
+[^:]*:998: Error: operand 1 of 'shfl' on wrong side
+[^:]*:999: Error: 'shfl3' instruction not supported on this functional unit
+[^:]*:1000: Error: bad number of operands to 'shfl3'
+[^:]*:1001: Error: operand 1 of 'shfl3' on wrong side
+[^:]*:1002: Error: operand 2 of 'shfl3' on wrong side
+[^:]*:1003: Error: 'shl' instruction not supported on this functional unit
+[^:]*:1004: Error: bad number of operands to 'shl'
+[^:]*:1005: Error: bad register for operand 1 of 'shl'
+[^:]*:1006: Error: operand 2 of 'shl' on wrong side
+[^:]*:1007: Error: operand 1 of 'shl' on wrong side
+[^:]*:1008: Error: operand 2 of 'shl' out of range
+[^:]*:1009: Error: operand 2 of 'shl' out of range
+[^:]*:1010: Error: operand 2 of 'shl' out of range
+[^:]*:1011: Error: operand 2 of 'shl' out of range
+[^:]*:1012: Error: operand 2 of 'shl' out of range
+[^:]*:1013: Error: operand 2 of 'shl' out of range
+[^:]*:1014: Error: 'shlmb' instruction not supported on this functional unit
+[^:]*:1015: Error: bad number of operands to 'shlmb'
+[^:]*:1016: Error: operand 1 of 'shlmb' on wrong side
+[^:]*:1017: Error: operand 2 of 'shlmb' on wrong side
+[^:]*:1018: Error: operand 1 of 'shlmb' on wrong side
+[^:]*:1019: Error: operand 2 of 'shlmb' on wrong side
+[^:]*:1020: Error: 'shr' instruction not supported on this functional unit
+[^:]*:1021: Error: bad number of operands to 'shr'
+[^:]*:1022: Error: bad register for operand 1 of 'shr'
+[^:]*:1022: Error: bad register for operand 3 of 'shr'
+[^:]*:1023: Error: operand 2 of 'shr' on wrong side
+[^:]*:1024: Error: operand 2 of 'shr' out of range
+[^:]*:1025: Error: operand 2 of 'shr' out of range
+[^:]*:1026: Error: operand 2 of 'shr' out of range
+[^:]*:1027: Error: operand 2 of 'shr' out of range
+[^:]*:1028: Error: 'shr2' instruction not supported on this functional unit
+[^:]*:1029: Error: 'shr2' instruction not supported on this functional unit
+[^:]*:1030: Error: bad number of operands to 'shr2'
+[^:]*:1031: Error: operand 2 of 'shr2' on wrong side
+[^:]*:1032: Error: operand 1 of 'shr2' on wrong side
+[^:]*:1033: Error: operand 2 of 'shr2' out of range
+[^:]*:1034: Error: operand 2 of 'shr2' out of range
+[^:]*:1035: Error: 'shrmb' instruction not supported on this functional unit
+[^:]*:1036: Error: bad number of operands to 'shrmb'
+[^:]*:1037: Error: operand 1 of 'shrmb' on wrong side
+[^:]*:1038: Error: operand 2 of 'shrmb' on wrong side
+[^:]*:1039: Error: operand 1 of 'shrmb' on wrong side
+[^:]*:1040: Error: operand 2 of 'shrmb' on wrong side
+[^:]*:1041: Error: 'shru' instruction not supported on this functional unit
+[^:]*:1042: Error: bad number of operands to 'shru'
+[^:]*:1043: Error: bad register for operand 1 of 'shru'
+[^:]*:1043: Error: bad register for operand 3 of 'shru'
+[^:]*:1044: Error: operand 2 of 'shru' on wrong side
+[^:]*:1045: Error: operand 2 of 'shru' out of range
+[^:]*:1046: Error: operand 2 of 'shru' out of range
+[^:]*:1047: Error: operand 2 of 'shru' out of range
+[^:]*:1048: Error: operand 2 of 'shru' out of range
+[^:]*:1049: Error: 'shru2' instruction not supported on this functional unit
+[^:]*:1050: Error: 'shru2' instruction not supported on this functional unit
+[^:]*:1051: Error: bad number of operands to 'shru2'
+[^:]*:1052: Error: operand 2 of 'shru2' on wrong side
+[^:]*:1053: Error: operand 1 of 'shru2' on wrong side
+[^:]*:1054: Error: operand 2 of 'shru2' out of range
+[^:]*:1055: Error: operand 2 of 'shru2' out of range
+[^:]*:1056: Error: 'smpy' instruction not supported on this functional unit
+[^:]*:1057: Error: bad number of operands to 'smpy'
+[^:]*:1058: Error: operand 1 of 'smpy' on wrong side
+[^:]*:1059: Error: operand 2 of 'smpy' on wrong side
+[^:]*:1060: Error: 'smpyh' instruction not supported on this functional unit
+[^:]*:1061: Error: bad number of operands to 'smpyh'
+[^:]*:1062: Error: operand 1 of 'smpyh' on wrong side
+[^:]*:1063: Error: operand 2 of 'smpyh' on wrong side
+[^:]*:1064: Error: 'smpyhl' instruction not supported on this functional unit
+[^:]*:1065: Error: bad number of operands to 'smpyhl'
+[^:]*:1066: Error: operand 1 of 'smpyhl' on wrong side
+[^:]*:1067: Error: operand 2 of 'smpyhl' on wrong side
+[^:]*:1068: Error: 'smpylh' instruction not supported on this functional unit
+[^:]*:1069: Error: bad number of operands to 'smpylh'
+[^:]*:1070: Error: operand 1 of 'smpylh' on wrong side
+[^:]*:1071: Error: operand 2 of 'smpylh' on wrong side
+[^:]*:1072: Error: 'smpy2' instruction not supported on this functional unit
+[^:]*:1073: Error: bad number of operands to 'smpy2'
+[^:]*:1074: Error: operand 1 of 'smpy2' on wrong side
+[^:]*:1075: Error: operand 2 of 'smpy2' on wrong side
+[^:]*:1076: Error: 'smpy32' instruction not supported on this functional unit
+[^:]*:1077: Error: bad number of operands to 'smpy32'
+[^:]*:1078: Error: operand 1 of 'smpy32' on wrong side
+[^:]*:1079: Error: operand 2 of 'smpy32' on wrong side
+[^:]*:1080: Error: 'spack2' instruction not supported on this functional unit
+[^:]*:1081: Error: bad number of operands to 'spack2'
+[^:]*:1082: Error: operand 1 of 'spack2' on wrong side
+[^:]*:1083: Error: operand 2 of 'spack2' on wrong side
+[^:]*:1084: Error: 'spacku4' instruction not supported on this functional unit
+[^:]*:1085: Error: bad number of operands to 'spacku4'
+[^:]*:1086: Error: operand 1 of 'spacku4' on wrong side
+[^:]*:1087: Error: operand 2 of 'spacku4' on wrong side
+[^:]*:1088: Error: 'spdp' instruction not supported on this functional unit
+[^:]*:1089: Error: bad number of operands to 'spdp'
+[^:]*:1090: Error: operand 2 of 'spdp' on wrong side
+[^:]*:1091: Error: operand 1 of 'spdp' on wrong side
+[^:]*:1092: Error: 'spint' instruction not supported on this functional unit
+[^:]*:1093: Error: too many operands to 'spint'
+[^:]*:1094: Error: operand 2 of 'spint' on wrong side
+[^:]*:1095: Error: operand 1 of 'spint' on wrong side
+[^:]*:1096: Error: 'sptrunc' instruction not supported on this functional unit
+[^:]*:1097: Error: too many operands to 'sptrunc'
+[^:]*:1098: Error: operand 2 of 'sptrunc' on wrong side
+[^:]*:1099: Error: operand 1 of 'sptrunc' on wrong side
+[^:]*:1100: Error: 'sshl' instruction not supported on this functional unit
+[^:]*:1101: Error: bad number of operands to 'sshl'
+[^:]*:1102: Error: operand 2 of 'sshl' on wrong side
+[^:]*:1103: Error: operand 1 of 'sshl' on wrong side
+[^:]*:1104: Error: operand 2 of 'sshl' out of range
+[^:]*:1105: Error: operand 2 of 'sshl' out of range
+[^:]*:1106: Error: 'sshvl' instruction not supported on this functional unit
+[^:]*:1107: Error: bad number of operands to 'sshvl'
+[^:]*:1108: Error: operand 2 of 'sshvl' on wrong side
+[^:]*:1109: Error: operand 1 of 'sshvl' on wrong side
+[^:]*:1110: Error: 'sshvr' instruction not supported on this functional unit
+[^:]*:1111: Error: bad number of operands to 'sshvr'
+[^:]*:1112: Error: operand 2 of 'sshvr' on wrong side
+[^:]*:1113: Error: operand 1 of 'sshvr' on wrong side
+[^:]*:1114: Error: 'ssub' instruction not supported on this functional unit
+[^:]*:1115: Error: bad number of operands to 'ssub'
+[^:]*:1116: Error: operand 3 of 'ssub' on wrong side
+[^:]*:1117: Error: bad operand combination for 'ssub'
+[^:]*:1118: Error: operand 1 of 'ssub' out of range
+[^:]*:1119: Error: operand 1 of 'ssub' out of range
+[^:]*:1120: Error: bad register for operand 2 of 'ssub'
+[^:]*:1120: Error: bad register for operand 3 of 'ssub'
+[^:]*:1121: Error: operand 1 of 'ssub' out of range
+[^:]*:1122: Error: operand 1 of 'ssub' out of range
+[^:]*:1123: Error: 'ssub2' instruction not supported on this functional unit
+[^:]*:1124: Error: bad number of operands to 'ssub2'
+[^:]*:1125: Error: operand 2 of 'ssub2' on wrong side
+[^:]*:1126: Error: operand 2 of 'ssub2' on wrong side
+[^:]*:1127: Error: 'stb' instruction not supported on this functional unit
+[^:]*:1128: Error: operand 1 of 'stb' on wrong side
+[^:]*:1129: Error: operand 2 of 'stb' not a valid memory reference
+[^:]*:1130: Error: operand 2 of 'stb' not a valid memory reference
+[^:]*:1131: Error: operand 1 of 'stb' on wrong side
+[^:]*:1132: Error: bad register for operand 1 of 'stb'
+[^:]*:1133: Error: operand 2 of 'stb' not a valid memory reference
+[^:]*:1134: Error: bad operand 2 of 'stb'
+[^:]*:1135: Error: bad operand 2 of 'stb'
+[^:]*:1136: Error: offset in operand 2 of 'stb' out of range
+[^:]*:1137: Error: offset in operand 2 of 'stb' out of range
+[^:]*:1138: Error: offset in operand 2 of 'stb' out of range
+[^:]*:1139: Error: offset in operand 2 of 'stb' out of range
+[^:]*:1140: Error: operand 2 of 'stb' not a valid memory reference
+[^:]*:1141: Error: operand 2 of 'stb' not a valid memory reference
+[^:]*:1142: Error: operand 2 of 'stb' out of range
+[^:]*:1143: Error: operand 2 of 'stb' out of range
+[^:]*:1144: Error: 'stdw' instruction not supported on this functional unit
+[^:]*:1145: Error: operand 1 of 'stdw' on wrong side
+[^:]*:1146: Error: operand 2 of 'stdw' not a valid memory reference
+[^:]*:1147: Error: operand 2 of 'stdw' not a valid memory reference
+[^:]*:1148: Error: operand 1 of 'stdw' on wrong side
+[^:]*:1149: Error: bad register pair for operand 1 of 'stdw'
+[^:]*:1150: Error: operand 2 of 'stdw' not a valid memory reference
+[^:]*:1151: Error: bad operand 2 of 'stdw'
+[^:]*:1152: Error: bad operand 2 of 'stdw'
+[^:]*:1153: Error: offset in operand 2 of 'stdw' out of range
+[^:]*:1154: Error: offset in operand 2 of 'stdw' out of range
+[^:]*:1155: Error: offset in operand 2 of 'stdw' out of range
+[^:]*:1156: Error: offset in operand 2 of 'stdw' out of range
+[^:]*:1157: Error: operand 2 of 'stdw' not a valid memory reference
+[^:]*:1158: Error: operand 2 of 'stdw' not a valid memory reference
+[^:]*:1159: Error: offset in operand 2 of 'stdw' not divisible by 8
+[^:]*:1160: Error: operand 2 of 'stdw' not a valid memory reference
+[^:]*:1161: Error: 'sth' instruction not supported on this functional unit
+[^:]*:1162: Error: operand 1 of 'sth' on wrong side
+[^:]*:1163: Error: operand 2 of 'sth' not a valid memory reference
+[^:]*:1164: Error: operand 2 of 'sth' not a valid memory reference
+[^:]*:1165: Error: operand 1 of 'sth' on wrong side
+[^:]*:1166: Error: bad register for operand 1 of 'sth'
+[^:]*:1167: Error: operand 2 of 'sth' not a valid memory reference
+[^:]*:1168: Error: bad operand 2 of 'sth'
+[^:]*:1169: Error: bad operand 2 of 'sth'
+[^:]*:1170: Error: offset in operand 2 of 'sth' out of range
+[^:]*:1171: Error: offset in operand 2 of 'sth' out of range
+[^:]*:1172: Error: offset in operand 2 of 'sth' out of range
+[^:]*:1173: Error: offset in operand 2 of 'sth' out of range
+[^:]*:1174: Error: operand 2 of 'sth' not a valid memory reference
+[^:]*:1175: Error: operand 2 of 'sth' not a valid memory reference
+[^:]*:1176: Error: offset in operand 2 of 'sth' not divisible by 2
+[^:]*:1177: Error: operand 2 of 'sth' out of range
+[^:]*:1178: Error: operand 2 of 'sth' out of range
+[^:]*:1179: Error: 'stndw' instruction not supported on this functional unit
+[^:]*:1180: Error: operand 1 of 'stndw' on wrong side
+[^:]*:1181: Error: operand 2 of 'stndw' not a valid memory reference
+[^:]*:1182: Error: operand 2 of 'stndw' not a valid memory reference
+[^:]*:1183: Error: operand 1 of 'stndw' on wrong side
+[^:]*:1184: Error: bad register pair for operand 1 of 'stndw'
+[^:]*:1185: Error: operand 2 of 'stndw' not a valid memory reference
+[^:]*:1186: Error: bad operand 2 of 'stndw'
+[^:]*:1187: Error: bad operand 2 of 'stndw'
+[^:]*:1188: Error: offset in operand 2 of 'stndw' out of range
+[^:]*:1189: Error: offset in operand 2 of 'stndw' out of range
+[^:]*:1190: Error: offset in operand 2 of 'stndw' out of range
+[^:]*:1191: Error: offset in operand 2 of 'stndw' out of range
+[^:]*:1192: Error: operand 2 of 'stndw' not a valid memory reference
+[^:]*:1193: Error: 'stnw' instruction not supported on this functional unit
+[^:]*:1194: Error: operand 1 of 'stnw' on wrong side
+[^:]*:1195: Error: operand 2 of 'stnw' not a valid memory reference
+[^:]*:1196: Error: operand 2 of 'stnw' not a valid memory reference
+[^:]*:1197: Error: operand 1 of 'stnw' on wrong side
+[^:]*:1198: Error: bad register for operand 1 of 'stnw'
+[^:]*:1199: Error: operand 2 of 'stnw' not a valid memory reference
+[^:]*:1200: Error: bad operand 2 of 'stnw'
+[^:]*:1201: Error: bad operand 2 of 'stnw'
+[^:]*:1202: Error: offset in operand 2 of 'stnw' out of range
+[^:]*:1203: Error: offset in operand 2 of 'stnw' out of range
+[^:]*:1204: Error: offset in operand 2 of 'stnw' out of range
+[^:]*:1205: Error: offset in operand 2 of 'stnw' out of range
+[^:]*:1206: Error: operand 2 of 'stnw' not a valid memory reference
+[^:]*:1207: Error: operand 2 of 'stnw' not a valid memory reference
+[^:]*:1208: Error: offset in operand 2 of 'stnw' not divisible by 4
+[^:]*:1209: Error: 'stw' instruction not supported on this functional unit
+[^:]*:1210: Error: operand 1 of 'stw' on wrong side
+[^:]*:1211: Error: operand 2 of 'stw' not a valid memory reference
+[^:]*:1212: Error: operand 2 of 'stw' not a valid memory reference
+[^:]*:1213: Error: operand 1 of 'stw' on wrong side
+[^:]*:1214: Error: bad register for operand 1 of 'stw'
+[^:]*:1215: Error: operand 2 of 'stw' not a valid memory reference
+[^:]*:1216: Error: bad operand 2 of 'stw'
+[^:]*:1217: Error: bad operand 2 of 'stw'
+[^:]*:1218: Error: offset in operand 2 of 'stw' out of range
+[^:]*:1219: Error: offset in operand 2 of 'stw' out of range
+[^:]*:1220: Error: offset in operand 2 of 'stw' out of range
+[^:]*:1221: Error: offset in operand 2 of 'stw' out of range
+[^:]*:1222: Error: operand 2 of 'stw' not a valid memory reference
+[^:]*:1223: Error: operand 2 of 'stw' not a valid memory reference
+[^:]*:1224: Error: offset in operand 2 of 'stw' not divisible by 4
+[^:]*:1225: Error: operand 2 of 'stw' out of range
+[^:]*:1226: Error: operand 2 of 'stw' out of range
+[^:]*:1227: Error: 'neg' instruction not supported on this functional unit
+[^:]*:1228: Error: bad register for operand 1 of 'neg'
+[^:]*:1228: Error: bad register for operand 2 of 'neg'
+[^:]*:1229: Error: too many operands to 'neg'
+[^:]*:1230: Error: operand 2 of 'neg' on wrong side
+[^:]*:1231: Error: operand 1 of 'neg' on wrong side
+[^:]*:1232: Error: bad register for operand 1 of 'neg'
+[^:]*:1232: Error: bad register for operand 2 of 'neg'
+[^:]*:1233: Error: operand 2 of 'neg' on wrong side
+[^:]*:1234: Error: operand 1 of 'neg' on wrong side
+[^:]*:1235: Error: 'sub' instruction not supported on this functional unit
+[^:]*:1236: Error: bad number of operands to 'sub'
+[^:]*:1237: Error: operand 1 of 'sub' on wrong side
+[^:]*:1238: Error: bad operand combination for 'sub'
+[^:]*:1239: Error: junk after operand 2 of 'sub'
+[^:]*:1240: Error: operand 1 of 'sub' out of range
+[^:]*:1241: Error: operand 1 of 'sub' out of range
+[^:]*:1242: Error: operand 1 of 'sub' out of range
+[^:]*:1243: Error: operand 1 of 'sub' out of range
+[^:]*:1244: Error: bad number of operands to 'sub'
+[^:]*:1245: Error: operand 3 of 'sub' on wrong side
+[^:]*:1246: Error: bad operand combination for 'sub'
+[^:]*:1247: Error: operand 1 of 'sub' out of range
+[^:]*:1248: Error: operand 1 of 'sub' out of range
+[^:]*:1249: Error: junk after operand 2 of 'sub'
+[^:]*:1249: Error: bad register for operand 3 of 'sub'
+[^:]*:1250: Error: bad number of operands to 'sub'
+[^:]*:1251: Error: operand 1 of 'sub' on wrong side
+[^:]*:1252: Error: operand 2 of 'sub' on wrong side
+[^:]*:1253: Error: bad register for operand 2 of 'sub'
+[^:]*:1254: Error: operand 2 of 'sub' out of range
+[^:]*:1255: Error: operand 2 of 'sub' out of range
+[^:]*:1256: Error: 'subab' instruction not supported on this functional unit
+[^:]*:1257: Error: bad number of operands to 'subab'
+[^:]*:1258: Error: operand 2 of 'subab' on wrong side
+[^:]*:1259: Error: 'subab' instruction not supported on this functional unit
+[^:]*:1260: Error: 'subab' instruction not supported on this functional unit
+[^:]*:1261: Error: operand 2 of 'subab' out of range
+[^:]*:1262: Error: operand 2 of 'subab' out of range
+[^:]*:1263: Error: 'subabs4' instruction not supported on this functional unit
+[^:]*:1264: Error: bad number of operands to 'subabs4'
+[^:]*:1265: Error: operand 3 of 'subabs4' on wrong side
+[^:]*:1266: Error: operand 2 of 'subabs4' on wrong side
+[^:]*:1267: Error: 'subah' instruction not supported on this functional unit
+[^:]*:1268: Error: bad number of operands to 'subah'
+[^:]*:1269: Error: operand 2 of 'subah' on wrong side
+[^:]*:1270: Error: 'subah' instruction not supported on this functional unit
+[^:]*:1271: Error: 'subah' instruction not supported on this functional unit
+[^:]*:1272: Error: operand 2 of 'subah' out of range
+[^:]*:1273: Error: operand 2 of 'subah' out of range
+[^:]*:1274: Error: 'subaw' instruction not supported on this functional unit
+[^:]*:1275: Error: bad number of operands to 'subaw'
+[^:]*:1276: Error: operand 2 of 'subaw' on wrong side
+[^:]*:1277: Error: 'subaw' instruction not supported on this functional unit
+[^:]*:1278: Error: 'subaw' instruction not supported on this functional unit
+[^:]*:1279: Error: operand 2 of 'subaw' out of range
+[^:]*:1280: Error: operand 2 of 'subaw' out of range
+[^:]*:1281: Error: 'subc' instruction not supported on this functional unit
+[^:]*:1282: Error: bad number of operands to 'subc'
+[^:]*:1283: Error: operand 1 of 'subc' on wrong side
+[^:]*:1284: Error: operand 2 of 'subc' on wrong side
+[^:]*:1285: Error: 'subdp' instruction not supported on this functional unit
+[^:]*:1286: Error: bad number of operands to 'subdp'
+[^:]*:1287: Error: operand 1 of 'subdp' on wrong side
+[^:]*:1288: Error: bad operand combination for 'subdp'
+[^:]*:1289: Error: operand 1 of 'subdp' on wrong side
+[^:]*:1290: Error: bad operand combination for 'subdp'
+[^:]*:1291: Error: 'subsp' instruction not supported on this functional unit
+[^:]*:1292: Error: bad number of operands to 'subsp'
+[^:]*:1293: Error: operand 3 of 'subsp' on wrong side
+[^:]*:1294: Error: bad operand combination for 'subsp'
+[^:]*:1295: Error: bad number of operands to 'subsp'
+[^:]*:1296: Error: operand 3 of 'subsp' on wrong side
+[^:]*:1297: Error: bad operand combination for 'subsp'
+[^:]*:1298: Error: 'subu' instruction not supported on this functional unit
+[^:]*:1299: Error: bad number of operands to 'subu'
+[^:]*:1300: Error: bad register pair for operand 3 of 'subu'
+[^:]*:1301: Error: operand 3 of 'subu' on wrong side
+[^:]*:1302: Error: bad operand combination for 'subu'
+[^:]*:1303: Error: 'sub2' instruction not supported on this functional unit
+[^:]*:1304: Error: bad number of operands to 'sub2'
+[^:]*:1305: Error: operand 3 of 'sub2' on wrong side
+[^:]*:1306: Error: operand 2 of 'sub2' on wrong side
+[^:]*:1307: Error: bad number of operands to 'sub2'
+[^:]*:1308: Error: operand 3 of 'sub2' on wrong side
+[^:]*:1309: Error: operand 2 of 'sub2' on wrong side
+[^:]*:1310: Error: bad number of operands to 'sub2'
+[^:]*:1311: Error: operand 3 of 'sub2' on wrong side
+[^:]*:1312: Error: operand 2 of 'sub2' on wrong side
+[^:]*:1313: Error: 'sub4' instruction not supported on this functional unit
+[^:]*:1314: Error: bad number of operands to 'sub4'
+[^:]*:1315: Error: operand 3 of 'sub4' on wrong side
+[^:]*:1316: Error: operand 2 of 'sub4' on wrong side
+[^:]*:1317: Error: 'swap2' instruction not supported on this functional unit
+[^:]*:1318: Error: too many operands to 'swap2'
+[^:]*:1319: Error: 'swap2' instruction not supported on this functional unit
+[^:]*:1320: Error: operand 1 of 'swap2' on wrong side
+[^:]*:1321: Error: too many operands to 'swap2'
+[^:]*:1322: Error: 'swap2' instruction not supported on this functional unit
+[^:]*:1323: Error: operand 1 of 'swap2' on wrong side
+[^:]*:1324: Error: 'swap4' instruction not supported on this functional unit
+[^:]*:1325: Error: bad number of operands to 'swap4'
+[^:]*:1326: Error: operand 2 of 'swap4' on wrong side
+[^:]*:1327: Error: operand 1 of 'swap4' on wrong side
+[^:]*:1328: Error: 'swe' instruction not supported on this functional unit
+[^:]*:1329: Error: too many operands to 'swe'
+[^:]*:1330: Error: 'swenr' instruction not supported on this functional unit
+[^:]*:1331: Error: too many operands to 'swenr'
+[^:]*:1332: Error: 'unpkhu4' instruction not supported on this functional unit
+[^:]*:1333: Error: too many operands to 'unpkhu4'
+[^:]*:1334: Error: operand 2 of 'unpkhu4' on wrong side
+[^:]*:1335: Error: operand 1 of 'unpkhu4' on wrong side
+[^:]*:1336: Error: too many operands to 'unpkhu4'
+[^:]*:1337: Error: operand 2 of 'unpkhu4' on wrong side
+[^:]*:1338: Error: operand 1 of 'unpkhu4' on wrong side
+[^:]*:1339: Error: 'unpklu4' instruction not supported on this functional unit
+[^:]*:1340: Error: too many operands to 'unpklu4'
+[^:]*:1341: Error: operand 2 of 'unpklu4' on wrong side
+[^:]*:1342: Error: operand 1 of 'unpklu4' on wrong side
+[^:]*:1343: Error: too many operands to 'unpklu4'
+[^:]*:1344: Error: operand 2 of 'unpklu4' on wrong side
+[^:]*:1345: Error: operand 1 of 'unpklu4' on wrong side
+[^:]*:1346: Error: 'not' instruction not supported on this functional unit
+[^:]*:1347: Error: too many operands to 'not'
+[^:]*:1348: Error: operand 2 of 'not' on wrong side
+[^:]*:1349: Error: operand 1 of 'not' on wrong side
+[^:]*:1350: Error: too many operands to 'not'
+[^:]*:1351: Error: operand 2 of 'not' on wrong side
+[^:]*:1352: Error: operand 1 of 'not' on wrong side
+[^:]*:1353: Error: too many operands to 'not'
+[^:]*:1354: Error: operand 2 of 'not' on wrong side
+[^:]*:1355: Error: operand 1 of 'not' on wrong side
+[^:]*:1356: Error: 'xor' instruction not supported on this functional unit
+[^:]*:1357: Error: bad number of operands to 'xor'
+[^:]*:1358: Error: operand 3 of 'xor' on wrong side
+[^:]*:1359: Error: operand 2 of 'xor' on wrong side
+[^:]*:1360: Error: operand 1 of 'xor' out of range
+[^:]*:1361: Error: operand 1 of 'xor' out of range
+[^:]*:1362: Error: bad number of operands to 'xor'
+[^:]*:1363: Error: operand 3 of 'xor' on wrong side
+[^:]*:1364: Error: operand 2 of 'xor' on wrong side
+[^:]*:1365: Error: operand 1 of 'xor' out of range
+[^:]*:1366: Error: operand 1 of 'xor' out of range
+[^:]*:1367: Error: bad number of operands to 'xor'
+[^:]*:1368: Error: operand 3 of 'xor' on wrong side
+[^:]*:1369: Error: operand 2 of 'xor' on wrong side
+[^:]*:1370: Error: operand 1 of 'xor' out of range
+[^:]*:1371: Error: operand 1 of 'xor' out of range
+[^:]*:1372: Error: 'xormpy' instruction not supported on this functional unit
+[^:]*:1373: Error: bad number of operands to 'xormpy'
+[^:]*:1374: Error: operand 1 of 'xormpy' on wrong side
+[^:]*:1375: Error: operand 2 of 'xormpy' on wrong side
+[^:]*:1376: Error: 'xpnd2' instruction not supported on this functional unit
+[^:]*:1377: Error: too many operands to 'xpnd2'
+[^:]*:1378: Error: operand 2 of 'xpnd2' on wrong side
+[^:]*:1379: Error: operand 1 of 'xpnd2' on wrong side
+[^:]*:1380: Error: 'xpnd4' instruction not supported on this functional unit
+[^:]*:1381: Error: too many operands to 'xpnd4'
+[^:]*:1382: Error: operand 2 of 'xpnd4' on wrong side
+[^:]*:1383: Error: operand 1 of 'xpnd4' on wrong side
+[^:]*:1384: Error: 'zero' instruction not supported on this functional unit
+[^:]*:1385: Error: too many operands to 'zero'
+[^:]*:1386: Error: operand 1 of 'zero' on wrong side
+[^:]*:1387: Error: too many operands to 'zero'
+[^:]*:1388: Error: operand 1 of 'zero' on wrong side
+[^:]*:1389: Error: too many operands to 'zero'
+[^:]*:1390: Error: operand 1 of 'zero' on wrong side
+[^:]*:1391: Error: operand 2 of 'sub' out of range
+[^:]*:1392: Error: operand 2 of 'sub' out of range
+[^:]*:1393: Error: operand 2 of 'sub' out of range
+[^:]*:1394: Error: operand 2 of 'sub' out of range
+[^:]*:1395: Error: operand 2 of 'sub' out of range
+[^:]*:1396: Error: operand 2 of 'sub' out of range
+[^:]*:1397: Error: operand 1 of 'addab' not a valid base address register
+[^:]*:1398: Error: operand 1 of 'addah' not a valid base address register
+[^:]*:1399: Error: operand 1 of 'addaw' not a valid base address register
--- /dev/null
+# Test bad instructions and operands.
+.text
+.globl f
+f:
+ nonesuch foo bar
+ nop nonconst
+ nop 2,
+ nop 2,3
+ nop 2 , 4
+ nop 2 4
+ nop 0
+ nop -1
+ nop 10000
+ nop 10
+ nop 15
+ abs .L1 a1,
+ abs .L1 a1
+ abs .S1 a1,a2
+ abs .L1 foo,bar
+ abs .L1X foo,bar
+ abs .L1 A0,A00
+ abs .L1 A32,A1
+ abs .L1 B1,A1
+ abs .L1 A1,B1
+ abs .L1X A1,A1
+ abs .L1X B1,B1
+ abs .L2 A3,B4
+ abs .L2 B4,A3
+ abs .L2X A7,A8
+ abs .L2X b9,b10
+ abs .L1 A2:A1,A3:A2
+ abs .L2 B5:B4,B2:B3
+ abs .L1 A3:B2,A5:A4
+ abs .L2 B1:B0,A5:A4
+ abs .L1X B1:B0,A1:A0
+ abs .L1 A1:A0,A11
+ abs2 .L1 a1
+ abs2 .S1 a1,a2
+ abs2 .L1 foo,a3:a2
+ abs2 .L2X b1,b2
+ absdp .L1 a3:a2,a1:a0
+ absdp .S2 b1:b0
+ absdp .S2 b1,b0
+ absdp .S2X a1:a0,b1:b0
+ abssp .L1 a0,a0
+ abssp .S1 a1:a0
+ abssp .S1X a0,a1
+ abssp .S2 a1,b0
+ add .M1 a0,a0,a0
+ add .L1 a0,b0,a0
+ add .L1X a0,a0,a0
+ add .L1 a1:a0,a3:a2,a5:a4
+ add .L1X 16,b2,a3
+ add .L1X -17,b2,a3
+ add .L1X 5,a3:a2,a7:a6
+ add .L2 100,b5:b4,b9:b8
+ add .L1 a0,a0
+ add .S1 a0,a0,a1:a0
+ add .S2 b1,b2
+ add .S1X 4,a5,a7
+ add .S2X -17,a9,b11
+ add .S1 16,a14,a13
+ add .D1T1 a1,a1,a1
+ add .D1 a1,a1
+ add .D2 b1,-17,b2
+ add .D2 b1,32,b4
+ add .D1X b1,b1,a1
+ add .D2X a5,-17,b1
+ add .D2X a20,16,b4
+ addab .L1 a4,a5,a6
+ addab .D1X a7,a8,a9
+ addab .D1 a2,a3
+ addab .D2 a1,b2,b3
+ addab .D1 a1,-1,a2
+ addab .D2 b1,32,b2
+ addab .D1X b14,-1,a2
+ addab .D2 b15,32768,b20
+ addab .D1 a14,32,a20
+ addad .D1X a4,a5,a6
+ addad .S1 a10,a9,a8
+ addad .D1 a1,a2,a3,a4
+ addad .D2 b4,-1,b4
+ addad .D2 b4,32,b3
+ addad .D1 a1,b2,a3
+ addad .D2 b14,foo,b4
+ addah .L1 a4,a5,a6
+ addah .D1X a7,a8,a9
+ addah .D1 a2,a3
+ addah .D2 a1,b2,b3
+ addah .D1 a1,-1,a2
+ addah .D2 b1,32,b2
+ addah .D1X b14,-1,a2
+ addah .D2 b15,32768,b20
+ addah .D1 a14,32,a20
+ addaw .L1 a4,a5,a6
+ addaw .D1X a7,a8,a9
+ addaw .D1 a2,a3
+ addaw .D2 a1,b2,b3
+ addaw .D1 a1,-1,a2
+ addaw .D2 b1,32,b2
+ addaw .D1X b14,-1,a2
+ addaw .D2 b15,32768,b20
+ addaw .D1 a14,32,a20
+ adddp .D1 a1:a0,a1:a0,a1:a0
+ adddp .L1 a1:a0,a1:a0
+ adddp .L2 b1,b1,b1
+ adddp .L1 a1:a0,b1:b0,a1:a0
+ adddp .L2X b1:b0,b3:b2,b5:b4
+ addk .L1 0,a1
+ addk .S2 32768,b1
+ addk .S1 -32769,a1
+ addk .S2 0
+ addk .S2X 0,a1
+ mvk .M1 0,a1
+ mvk .S2 32768,b1
+ mvk .S1 -32769,a1
+ mvk .S2 0,b1,0
+ mvk .S1X 0,b1
+ mvkh .L1 0,a1
+ mvkh .S2 0,b1,0
+ mvkh .S1X 0,b1
+ mvklh .L1 0,a1
+ mvklh .S2 0,b1,0
+ mvklh .S1X 0,b1
+ mvkl .L1 0,a1
+ mvkl .S2 0,b1,0
+ mvkl .S1X 0,b1
+ addkpc .S1 f,a1,0
+ addkpc .S2X f,a1,0
+ addkpc .S2 0,b2,0
+ addkpc .S2 f,b2
+ addkpc .S2 f,b2,-1
+ addkpc .S2 f,b2,8
+ b .L1 f
+ b .S1X f
+ b .S1 f,0
+ b .S1 0
+ call .L1 f
+ call .S1X f
+ call .S1 f,0
+ call .S1 0
+ bdec .L1 f,a1
+ bdec .S1X f,b1
+ bdec .S1 f,b1
+ bdec .S2 0,b2
+ bdec .S2 f,b1,0
+ bpos .L1 f,a1
+ bpos .S1X f,b1
+ bpos .S1 f,b1
+ bpos .S2 0,b2
+ bpos .S2 f,b1,0
+ bnop .L1 f,0
+ bnop .S1X f,0
+ bnop f,-1
+ bnop 0,0
+ bnop f,8
+ callnop .L1 f,0
+ callnop .S1X f,0
+ callnop f,-1
+ callnop 0,0
+ callnop f,8
+ callp .L1 f,a3
+ callp .S1X f,b3
+ callp .S1 f,a4
+ callp .S1 0,a3
+ callp .S1 f,b3
+ callp .S2 f,a3
+ addsp .D1 a1,a2,a3
+ addsp .L1 a1
+ addsp .L2 a2,0
+ addsp .L1 b1,a1,a3
+ addsp .S2X b1,b2,b3
+ addsub .M1 a2,a3,a5:a4
+ addsub .L1 a1
+ addsub .L1 a1,a2,a3
+ addsub .L2 a1,b1,b3:b2
+ addsub2 .M1 a2,a3,a5:a4
+ addsub2 .L1 a1
+ addsub2 .L1 a1,a2,a3
+ addsub2 .L2 a1,b1,b3:b2
+ addu .D2 b4,b5,b7:b6
+ addu .L2 b1,b2
+ addu .L1 b1,a1,a3:a2
+ addu .L2X a4,b7:b6,b5
+ add2 .M1 a1,a2,a3
+ add2 .S1 a1,a2,a3,a4
+ add2 .L1 b1,a1,a2
+ add2 .D2X b1,b2,b3
+ add4 .S1 a1,a2,a3
+ add4 .L1 a1,a2,a3,a4
+ add4 .L1 b1,a1,a2
+ add4 .L2X b1,b2,b3
+ and .M2 b1,b2,b3
+ and .L1 -17,a4,a5
+ and .L2 16,b3,b4
+ and .S1X -17,b4,a5
+ and .S2X 16,a3,b4
+ and .D1 -17,a4,a5
+ and .D2 16,b3,b4
+ and .D1 b1,a2,a3
+ andn .M1 a1,a2,a3
+ andn .S1 a1
+ andn .D1X b2,b2,a3
+ andn .S2 0,b2,b3
+ avg2 .S1 a1,a2,a3
+ avg2 .M1 a1,a2
+ avg2 .M1 b1,a2,a2
+ avg2 .M2X a1,a2,b3
+ avgu4 .S1 a1,a2,a3
+ avgu4 .M1 a1,a2
+ avgu4 .M1 b1,a2,a2
+ avgu4 .M2X a1,a2,b3
+ b .L2 b1
+ b .S2 b1,0
+ call .M2 b1
+ call .S2 b1,0
+ callret .D2 b1
+ callret .S2 b1,0
+ ret .L2 b1
+ ret .S2 b1,0
+ b .S2X irp
+ b .L2 irp
+ b .S2X nrp
+ b .M2 nrp
+ bitc4 .M1 a1,a2,a3
+ bitc4 .L1 a1,a2
+ bitc4 .M2 b2,a1
+ bitc4 .M2X b3,b4
+ bitr .M1 a1
+ bitr .S1 a1,a2
+ bitr .M2 b2,a1
+ bitr .M2X b3,b4
+ bnop .M1 a5,0
+ bnop .S1X b5,0
+ bnop .S2 b3,-1
+ bnop .S2 b3,8
+ bnop .S2 b3
+ callnop .M1 a5,0
+ callnop .S1X b5,0
+ callnop .S2 b3,-1
+ callnop .S2 b3,8
+ callnop .S2 b3
+ clr .L1 a1,0,1,a2
+ clr .M2 b1,b2,b3
+ clr .S1 a1,a1
+ clr .S1X a1,0,0,a1
+ clr .S2 b1,a1,b1
+ cmpeq .S1 a1,a2,a3
+ cmpeq .L1 a1,a2,a3,a4
+ cmpeq .L1 a1:a0,a3:a2,a5
+ cmpeq .L2 -17,b4,b5
+ cmpeq .L2 16,b4,b5
+ cmpeq .L1 -17,a5:a4,a3
+ cmpeq .L1 16,a5:a4,a3
+ cmpeq .L1X -16,a5:a4,a3
+ cmpeq2 .L1 a1,a2,a3
+ cmpeq2 .S1 a1,a2
+ cmpeq2 .S1 a1,b2,a3
+ cmpeq2 .S2X b1,b2,b3
+ cmpeq4 .D1 a1,a2,a3
+ cmpeq4 .S1 a1
+ cmpeq4 .S2 a1,b2,b3
+ cmpeq4 .S1X a4,a5,a6
+ cmpeqdp .M1 a3:a2,a1:a0,a5
+ cmpeqdp .S1 a3:a2
+ cmpeqdp .S1 a3,a2,a1
+ cmpeqdp .S2 a3:a2,b1:b0,b5
+ cmpeqdp .S2X b3:b2,b1:b0,b31
+ cmpeqsp .S1 a1
+ cmpeqsp .M2 b1,b2,b3
+ cmpeqsp .S2X b1,b2,b3
+ cmpeqsp .S1 b1,a2,a3
+ cmpgt .S1 a1,a2,a3
+ cmpgt .L1 a1,a2,a3,a4
+ cmpgt .L1 a1:a0,a3:a2,a5
+ cmpgt .L2 -17,b4,b5
+ cmpgt .L2 16,b4,b5
+ cmpgt .L1 -17,a5:a4,a3
+ cmpgt .L1 16,a5:a4,a3
+ cmpgt .L1X -16,a5:a4,a3
+ cmpgt2 .L1 a1,a2,a3
+ cmpgt2 .S1 a1,a2
+ cmpgt2 .S1 b1,a2,a3
+ cmpgt2 .S2X b1,b3,b3
+ cmpgtdp .L1 a1:a0,a1:a0,a0
+ cmpgtdp .S1 a1:a0
+ cmpgtdp .S1 b1:b0,a1:a0,a2
+ cmpgtdp .S2X b5:b4,b3:b2,b1
+ cmpgtsp .L1 a1,a1,a0
+ cmpgtsp .S1 a1
+ cmpgtsp .S1 b1,a1,a2
+ cmpgtsp .S2X b5,b3,b1
+ cmpgtu .S1 a1,a2,a3
+ cmpgtu .L1 a1,a2,a3,a4
+ cmpgtu .L1 a1:a0,a3:a2,a5
+ cmpgtu .L2 -1,b4,b5
+ cmpgtu .L2 32,b4,b5
+ cmpgtu .L1 -1,a5:a4,a3
+ cmpgtu .L1 32,a5:a4,a3
+ cmpgtu .L1X 0,a5:a4,a3
+ cmpgtu4 .D1 a1,a2,a3
+ cmpgtu4 .S1 a1,a2
+ cmpgtu4 .S1 a1,a2,b3
+ cmpgtu4 .S2X b1,b2,b3
+ cmplt .S1 a1,a2,a3
+ cmplt .L1 a1,a2,a3,a4
+ cmplt .L1 a1:a0,a3:a2,a5
+ cmplt .L2 -17,b4,b5
+ cmplt .L2 16,b4,b5
+ cmplt .L1 -17,a5:a4,a3
+ cmplt .L1 16,a5:a4,a3
+ cmplt .L1X -16,a5:a4,a3
+ cmplt2 .L1 a1,a2,a3
+ cmplt2 .S1 a1,a2
+ cmplt2 .S1 a2,b1,a3
+ cmplt2 .S2X b1,b3,b3
+ cmpltdp .L1 a1:a0,a1:a0,a0
+ cmpltdp .S1 a1:a0
+ cmpltdp .S1 b1:b0,a1:a0,a2
+ cmpltdp .S2X b5:b4,b3:b2,b1
+ cmpltsp .L1 a1,a1,a0
+ cmpltsp .S1 a1
+ cmpltsp .S1 b1,a1,a2
+ cmpltsp .S2X b5,b3,b1
+ cmpltu .S1 a1,a2,a3
+ cmpltu .L1 a1,a2,a3,a4
+ cmpltu .L1 a1:a0,a3:a2,a5
+ cmpltu .L2 -1,b4,b5
+ cmpltu .L2 32,b4,b5
+ cmpltu .L1 -1,a5:a4,a3
+ cmpltu .L1 32,a5:a4,a3
+ cmpltu .L1X 0,a5:a4,a3
+ cmpltu4 .D1 a1,a2,a3
+ cmpltu4 .S1 a1,a2
+ cmpltu4 .S1 a1,a2,b3
+ cmpltu4 .S2X b1,b2,b3
+ cmpy .S1 a1,a2,a5:a4
+ cmpy .M1 a1,a2
+ cmpy .M1 b1,a1,a3:a2
+ cmpy .M2X b3,b4,b7:b6
+ cmpyr .S1 a1,a2,a5
+ cmpyr .M1 a1,a2
+ cmpyr .M1 b1,a1,a3
+ cmpyr .M2X b3,b4,b7
+ cmpyr1 .L1 a1,a2,a5
+ cmpyr1 .M1 a1,a2
+ cmpyr1 .M1 b1,a1,a3
+ cmpyr1 .M2X b3,b4,b7
+ ddotp4 .D1 a1,a3,a5:a4
+ ddotp4 .M1 a1,a3
+ ddotp4 .M1X a1,a2,a5:a4
+ ddotp4 .M2 a1,b1,b3:b2
+ ddotph2 .L1 a1:a0,a3,a5:a4
+ ddotph2 .M1 a1:a0,a3
+ ddotph2 .M1X a1:a0,a2,a5:a4
+ ddotph2 .M2 a1:a0,b1,b3:b2
+ ddotph2r .S1 a1:a0,a3,a5
+ ddotph2r .M1 a1:a0,a3
+ ddotph2r .M1X a1:a0,a2,a5
+ ddotph2r .M2 a1:a0,b1,b3
+ ddotpl2 .L1 a1:a0,a3,a5:a4
+ ddotpl2 .M1 a1:a0,a3
+ ddotpl2 .M1X a1:a0,a2,a5:a4
+ ddotpl2 .M2 a1:a0,b1,b3:b2
+ ddotpl2r .L1 a1:a0,a3,a5
+ ddotpl2r .M1 a1:a0,a3
+ ddotpl2r .M1X a1:a0,a2,a5
+ ddotpl2r .M2 a1:a0,b1,b3
+ deal .D1 a1,a2
+ deal .M1 a1,a2,a3
+ deal .M2 b1,a1
+ deal .M2X b1,b2
+ dint .S1
+ dint a1
+ dmv .M1 a1,a2,a5:a4
+ dmv .S1 a1,a2
+ dmv .S2 a1,b2,b5:b4
+ dmv .S2X b1,b2,b5:b4
+ dotp2 .L1 a1,a2,a3
+ dotp2 .M1 a1,a2
+ dotp2 .M1 b1,a2,a3
+ dotp2 .M1X a1,a2,a3
+ dotp2 .M2 a1,b2,b5:b4
+ dotp2 .M2X b3,b4,b7:b6
+ dotpn2 .L1 a1,a2,a3
+ dotpn2 .M1 a1,a2
+ dotpn2 .M1 b1,a2,a3
+ dotpn2 .M1X a1,a2,a3
+ dotpnrsu2 .L1 a1,a2,a3
+ dotpnrsu2 .M1 a1,a2
+ dotpnrsu2 .M1 b1,a2,a3
+ dotpnrsu2 .M1X a1,a2,a3
+ dotpnrus2 .L1 a1,a2,a3
+ dotpnrus2 .M1 a1,a2
+ dotpnrus2 .M1 a2,b1,a3
+ dotpnrus2 .M1X a1,a2,a3
+ dotprsu2 .L1 a1,a2,a3
+ dotprsu2 .M1 a1,a2
+ dotprsu2 .M1 b1,a2,a3
+ dotprsu2 .M1X a1,a2,a3
+ dotprus2 .L1 a1,a2,a3
+ dotprus2 .M1 a1,a2
+ dotprus2 .M1 a2,b1,a3
+ dotprus2 .M1X a1,a2,a3
+ dotpsu4 .L1 a1,a2,a3
+ dotpsu4 .M1 a1,a2
+ dotpsu4 .M1 b1,a2,a3
+ dotpsu4 .M1X a1,a2,a3
+ dotpus4 .L1 a1,a2,a3
+ dotpus4 .M1 a1,a2
+ dotpus4 .M1 a2,b1,a3
+ dotpus4 .M1X a1,a2,a3
+ dotpu4 .L1 a1,a2,a3
+ dotpu4 .M1 a1,a2
+ dotpu4 .M1 b1,a2,a3
+ dotpu4 .M1X a1,a2,a3
+ dpack2 .M1 a0,a1,a3:a2
+ dpack2 .L1 a0,a1
+ dpack2 .L1 a1,a2,b3:b2
+ dpack2 .L2X b3,b4,b7:b6
+ dpackx2 .M1 a0,a1,a3:a2
+ dpackx2 .L1 a0,a1
+ dpackx2 .L1 a1,a2,b3:b2
+ dpackx2 .L2X b3,b4,b7:b6
+ dpint .S1 a5:a4,a3
+ dpint .L1X b5:b4,a3
+ dpint .L2 a5:a4,b3
+ dpsp .S1 a5:a4,a3
+ dpsp .L1X b5:b4,a3
+ dpsp .L2 a5:a4,b3
+ dptrunc .S1 a5:a4,a3
+ dptrunc .L1X b5:b4,a3
+ dptrunc .L2 a5:a4,b3
+ ext .L1 a1,0,1,a2
+ ext .M2 b1,b2,b3
+ ext .S1 a1,a1
+ ext .S1X a1,0,0,a1
+ ext .S2 b1,a1,b1
+ clr .S1 a0,-1,0,a1
+ clr .S1 a0,32,0,a1
+ clr .S1 a0,0,-1,a1
+ clr .S1 a0,0,32,a1
+ ext .S1 a0,-1,0,a1
+ ext .S1 a0,32,0,a1
+ ext .S1 a0,0,-1,a1
+ ext .S1 a0,0,32,a1
+ extu .L1 a1,0,1,a2
+ extu .M2 b1,b2,b3
+ extu .S1 a1,a1
+ extu .S1X a1,0,0,a1
+ extu .S2 b1,a1,b1
+ extu .S1 a0,-1,0,a1
+ extu .S1 a0,32,0,a1
+ extu .S1 a0,0,-1,a1
+ extu .S1 a0,0,32,a1
+ gmpy .L1 a1,a2,a3
+ gmpy .M1 a1,a2
+ gmpy .M1X a1,a2,a3
+ gmpy .M2 a1,b2,b3
+ gmpy4 .S1 a1,a2,a3
+ gmpy4 .M1 a1,a2,a3,a4
+ gmpy4 .M1 b1,a1,a2
+ gmpy4 .M2X b1,b2,b3
+ idle .S1
+ idle a0
+ intdp .S1 a5,a3:a2
+ intdp .L1 a5
+ intdp .L2 b0,a1:a0
+ intdp .L1X b5,b3:b2
+ intdpu .D1 a5,a3:a2
+ intdpu .L1 a5
+ intdpu .L2 b0,a1:a0
+ intdpu .L1X b5,b3:b2
+ intsp .S1 a5,a3
+ intsp .L1 a5
+ intsp .L2 b0,a1
+ intsp .L1X b5,b3
+ intspu .D1 a5,a3
+ intspu .L1 a5
+ intspu .L2 b0,a1
+ intspu .L1X b5,b3
+ cmtl .D2T1 *b0,a0
+ cmtl .D1T1 *a0,a1
+ cmtl .L1 *a0,a1
+ cmtl .D2T2 *+b0(0),b1
+ cmtl .D2T2 *-b0[0],b1
+ cmtl .D2T2 *++b0,b1
+ cmtl .D2T2 *--b0,b1
+ cmtl .D2T2 *b0++,b1
+ cmtl .D2T2 *b0--,b1
+ cmtl .D2T2 *+b0[b1],b2
+ cmtl .D2T2 *a0,b1
+ cmtl .D2T2 *b0,a1
+ ll .D2T1 *b0,a0
+ ll .D1T1 *a0,a1
+ ll .S1 *a0,a1
+ ll .D2T2 *+b0(0),b1
+ ll .D2T2 *-b0[0],b1
+ ll .D2T2 *++b0,b1
+ ll .D2T2 *--b0,b1
+ ll .D2T2 *b0++,b1
+ ll .D2T2 *b0--,b1
+ ll .D2T2 *+b0[b1],b2
+ ll .D2T2 *a0,b1
+ ll .D2T2 *b0,a1
+ sl .D2T1 a0,*b0
+ sl .D1T1 a1,*a0
+ sl .L1 a1,*a0
+ sl .D2T2 b1,*+b0(0)
+ sl .D2T2 b1,*-b0[0]
+ sl .D2T2 b1,*++b0
+ sl .D2T2 b1,*--b0
+ sl .D2T2 b1,*b0++
+ sl .D2T2 b1,*b0--
+ sl .D2T2 b2,*+b0[b1]
+ sl .D2T2 b1,*a0
+ sl .D2T2 a1,*b0
+ ldb .L1 *a1,a0
+ ldb .D1T1 *a1,b1
+ ldb .D1T1 *b1,a1
+ ldb .D2T2 *a1,b1
+ ldb .D2T2 *b1,a1
+ ldb .D1T1 *a1
+ ldb .D1T1 *+a1[b1],a2
+ ldb .D1T1 *+a1,a2
+ ldb .D1T1 *-a1,a2
+ ldb .D1T1 *a1++[32],a2
+ ldb .D1T1 *a1++(32),a2
+ ldb .D1T1 *--a1[-1],a2
+ ldb .D1T1 *--a1(-1),a2
+ ldb .D1T1 *+a1(a2),a3
+ ldb .D2T2 *+b14[foo],b16
+ ldbu .S1 *a1,a0
+ ldbu .D1T1 *a1,b1
+ ldbu .D1T1 *b1,a1
+ ldbu .D2T2 *a1,b1
+ ldbu .D2T2 *b1,a1
+ ldbu .D1T1 *a1
+ ldbu .D1T1 *+a1[b1],a2
+ ldbu .D1T1 *+a1,a2
+ ldbu .D1T1 *-a1,a2
+ ldbu .D1T1 *a1++[32],a2
+ ldbu .D1T1 *a1++(32),a2
+ ldbu .D1T1 *--a1[-1],a2
+ ldbu .D1T1 *--a1(-1),a2
+ ldbu .D1T1 *+a1(a2),a3
+ ldbu .D2T2 *+b14[foo],b16
+ lddw .L1 *a1,a1:a0
+ lddw .D1T1 *a1,b1:b0
+ lddw .D1T1 *b1,a1:a0
+ lddw .D2T2 *a1,b1:b0
+ lddw .D2T2 *b1,a1:a0
+ lddw .D1T1 *a1
+ lddw .D1T1 *+a1[b1],a3:a2
+ lddw .D1T1 *+a1,a3:a2
+ lddw .D1T1 *-a1,a3:a2
+ lddw .D1T1 *a1++[32],a3:a2
+ lddw .D1T1 *a1++(256),a3:a2
+ lddw .D1T1 *--a1[-1],a3:a2
+ lddw .D1T1 *--a1(-8),a3:a2
+ lddw .D1T1 *+a1(a2),a3:a2
+ lddw .D2T2 *+b14[foo],b17:b16
+ lddw .D1T1 *+a1(1),a3:a2
+ lddw .D2T2 *+b14(b15),b17:b16
+ ldh .M1 *a1,a0
+ ldh .D1T1 *a1,b1
+ ldh .D1T1 *b1,a1
+ ldh .D2T2 *a1,b1
+ ldh .D2T2 *b1,a1
+ ldh .D1T1 *a1
+ ldh .D1T1 *+a1[b1],a2
+ ldh .D1T1 *+a1,a2
+ ldh .D1T1 *-a1,a2
+ ldh .D1T1 *a1++[32],a2
+ ldh .D1T1 *a1++(64),a2
+ ldh .D1T1 *--a1[-1],a2
+ ldh .D1T1 *--a1(-2),a2
+ ldh .D1T1 *+a1(a2),a3
+ ldh .D2T2 *+b14[foo],b16
+ ldh .D2T2 *+b1(1),b2
+ ldhu .S1 *a1,a0
+ ldhu .D1T1 *a1,b1
+ ldhu .D1T1 *b1,a1
+ ldhu .D2T2 *a1,b1
+ ldhu .D2T2 *b1,a1
+ ldhu .D1T1 *a1
+ ldhu .D1T1 *+a1[b1],a2
+ ldhu .D1T1 *+a1,a2
+ ldhu .D1T1 *-a1,a2
+ ldhu .D1T1 *a1++[32],a2
+ ldhu .D1T1 *a1++(64),a2
+ ldhu .D1T1 *--a1[-1],a2
+ ldhu .D1T1 *--a1(-2),a2
+ ldhu .D1T1 *+a1(a2),a3
+ ldhu .D2T2 *+b14[foo],b16
+ ldhu .D2T2 *+b1(1),b2
+ ldndw .L1 *a1,a1:a0
+ ldndw .D1T1 *a1,b1:b0
+ ldndw .D1T1 *b1,a1:a0
+ ldndw .D2T2 *a1,b1:b0
+ ldndw .D2T2 *b1,a1:a0
+ ldndw .D1T1 *a1
+ ldndw .D1T1 *+a1[b1],a3:a2
+ ldndw .D1T1 *+a1,a3:a2
+ ldndw .D1T1 *-a1,a3:a2
+ ldndw .D1T1 *a1++[32],a3:a2
+ ldndw .D1T1 *a1++(32),a3:a2
+ ldndw .D1T1 *--a1[-1],a3:a2
+ ldndw .D1T1 *--a1(-1),a3:a2
+ ldndw .D2T2 *+b14[foo],b17:b16
+ ldnw .S1 *a1,a0
+ ldnw .D1T1 *a1,b1
+ ldnw .D1T1 *b1,a1
+ ldnw .D2T2 *a1,b1
+ ldnw .D2T2 *b1,a1
+ ldnw .D1T1 *a1
+ ldnw .D1T1 *+a1[b1],a2
+ ldnw .D1T1 *+a1,a2
+ ldnw .D1T1 *-a1,a2
+ ldnw .D1T1 *a1++[32],a2
+ ldnw .D1T1 *a1++(128),a2
+ ldnw .D1T1 *--a1[-1],a2
+ ldnw .D1T1 *--a1(-4),a2
+ ldnw .D1T1 *+a1(a2),a3
+ ldnw .D2T2 *+b14[foo],b16
+ ldnw .D2T2 *+b1(2),b2
+ ldw .S1 *a1,a0
+ ldw .D1T1 *a1,b1
+ ldw .D1T1 *b1,a1
+ ldw .D2T2 *a1,b1
+ ldw .D2T2 *b1,a1
+ ldw .D1T1 *a1
+ ldw .D1T1 *+a1[b1],a2
+ ldw .D1T1 *+a1,a2
+ ldw .D1T1 *-a1,a2
+ ldw .D1T1 *a1++[32],a2
+ ldw .D1T1 *a1++(128),a2
+ ldw .D1T1 *--a1[-1],a2
+ ldw .D1T1 *--a1(-4),a2
+ ldw .D1T1 *+a1(a2),a3
+ ldw .D2T2 *+b14[foo],b16
+ ldw .D2T2 *+b1(2),b2
+ ldb .D2T2 *+b14[-1],b1
+ ldb .D2T2 *+b14[32768],b1
+ ldbu .D2T2 *+b14[-1],b1
+ ldbu .D2T2 *+b14[32768],b1
+ ldh .D2T2 *+b14[-1],b1
+ ldh .D2T2 *+b14[32768],b1
+ ldhu .D2T2 *+b14[-1],b1
+ ldhu .D2T2 *+b14[32768],b1
+ ldw .D2T2 *+b14[-1],b1
+ ldw .D2T2 *+b14[32768],b1
+ lmbd .S1 a1,a2,a3
+ lmbd .L1 a1,a2
+ lmbd .L1 b1,a2,a3
+ lmbd .L2X b1,b2,b3
+ lmbd .L1 -17,a1,a2
+ lmbd .L1 16,a1,a2
+ max2 .M1 a1,a2,a3
+ max2 .L1 a1,a2
+ max2 .L1 b1,a2,a3
+ max2 .L2X b1,b2,b3
+ max2 .S2X b1,b2,b3
+ max2 .S2 a1,b2,b3
+ maxu4 .S1 a1,a2,a3
+ maxu4 .L1 a1,a2
+ maxu4 .L1 b1,a2,a3
+ maxu4 .L2X b1,b2,b3
+ min2 .M1 a1,a2,a3
+ min2 .L1 a1,a2
+ min2 .L1 b1,a2,a3
+ min2 .L2X b1,b2,b3
+ min2 .S2X b1,b2,b3
+ min2 .S2 a1,b2,b3
+ minu4 .S1 a1,a2,a3
+ minu4 .L1 a1,a2
+ minu4 .L1 b1,a2,a3
+ minu4 .L2X b1,b2,b3
+ mpy .L1 a1,a2,a3
+ mpy .M1 a1,a2
+ mpy .M1 b1,a2,a3
+ mpy .M2X b1,b2,b3
+ mpy .M2 -17,b1,b2
+ mpy .M1 16,a1,a2
+ mpy .M2X 0,b2,b3
+ mpydp .D1 a1:a0,a1:a0,a1:a0
+ mpydp .M1 a1:a0,a1:a0
+ mpydp .M1 b1:b0,a1:a0,a3:a2
+ mpydp .M2X b1:b0,a1:a0,b1:b0
+ mpyh .S1 a1,a2,a3
+ mpyh .M1 a1,a2
+ mpyh .M1 b1,a2,a3
+ mpyh .M2X b1,b2,b3
+ mpyhi .D1 a1,a2,a5:a4
+ mpyhi .M1 a1,a2
+ mpyhi .M1 b1,a2,a5:a4
+ mpyhi .M2X b1,b2,b5:b4
+ mpyhir .D1 a1,a2,a3
+ mpyhir .M1 a1,a2
+ mpyhir .M1 b1,a2,a3
+ mpyhir .M2X b1,b2,b3
+ mpyhl .L1 a1,a2,a3
+ mpyhl .M1 a1,a2
+ mpyhl .M1 b1,a2,a3
+ mpyhl .M2X b1,b2,b3
+ mpyhlu .S1 a1,a2,a3
+ mpyhlu .M1 a1,a2
+ mpyhlu .M1 b1,a2,a3
+ mpyhlu .M2X b1,b2,b3
+ mpyhslu .S1 a1,a2,a3
+ mpyhslu .M1 a1,a2
+ mpyhslu .M1 b1,a2,a3
+ mpyhslu .M2X b1,b2,b3
+ mpyhsu .S1 a1,a2,a3
+ mpyhsu .M1 a1,a2
+ mpyhsu .M1 b1,a2,a3
+ mpyhsu .M2X b1,b2,b3
+ mpyhu .D1 a1,a2,a3
+ mpyhu .M1 a1,a2
+ mpyhu .M1 b1,a2,a3
+ mpyhu .M2X b1,b2,b3
+ mpyhuls .S1 a1,a2,a3
+ mpyhuls .M1 a1,a2
+ mpyhuls .M1 b1,a2,a3
+ mpyhuls .M2X b1,b2,b3
+ mpyhus .S1 a1,a2,a3
+ mpyhus .M1 a1,a2
+ mpyhus .M1 b1,a2,a3
+ mpyhus .M2X b1,b2,b3
+ mpyi .L1 a1,a2,a3
+ mpyi .M1 a1,a2
+ mpyi .M1 b1,a2,a3
+ mpyi .M2X b1,b2,b3
+ mpyi .M1 -17,a2,a3
+ mpyi .M2 16,b2,b3
+ mpyid .D1 a1,a2,a3:a2
+ mpyid .M1 a1,a2
+ mpyid .M1 b1,a2,a3:a2
+ mpyid .M2X b1,b2,b3:b2
+ mpyid .M1 -17,a2,a3:a2
+ mpyid .M2 16,b2,b3:b2
+ mpyih .D1 a1,a2,a5:a4
+ mpyih .M1 a1,a2
+ mpyih .M1 b1,a2,a5:a4
+ mpyih .M2X b1,b2,b5:b4
+ mpyihr .D1 a1,a2,a3
+ mpyihr .M1 a1,a2
+ mpyihr .M1 b1,a2,a3
+ mpyihr .M2X b1,b2,b3
+ mpyil .S1 a1,a2,a5:a4
+ mpyil .M1 a1,a2
+ mpyil .M1 b1,a2,a5:a4
+ mpyil .M2X b1,b2,b5:b4
+ mpyilr .L1 a1,a2,a3
+ mpyilr .M1 a1,a2
+ mpyilr .M1 b1,a2,a3
+ mpyilr .M2X b1,b2,b3
+ mpylh .S1 a1,a2,a3
+ mpylh .M1 a1,a2
+ mpylh .M1 b1,a2,a3
+ mpylh .M2X b1,b2,b3
+ mpylhu .D1 a1,a2,a3
+ mpylhu .M1 a1,a2
+ mpylhu .M1 b1,a2,a3
+ mpylhu .M2X b1,b2,b3
+ mpyli .S1 a1,a2,a3:a2
+ mpyli .M1 a1,a2
+ mpyli .M1 b1,a2,a3:a2
+ mpyli .M2X b1,b2,b3:b2
+ mpylir .D1 a1,a2,a3
+ mpylir .M1 a1,a2
+ mpylir .M1 b1,a2,a3
+ mpylir .M2X b1,b2,b3
+ mpylshu .L1 a1,a2,a3
+ mpylshu .M1 a1,a2
+ mpylshu .M1 b1,a2,a3
+ mpylshu .M2X b1,b2,b3
+ mpyluhs .S1 a1,a2,a3
+ mpyluhs .M1 a1,a2
+ mpyluhs .M1 b1,a2,a3
+ mpyluhs .M2X b1,b2,b3
+ mpysp .D1 a1,a2,a3
+ mpysp .M1 a1,a2
+ mpysp .M1 b1,a2,a3
+ mpysp .M2X b1,b2,b3
+ mpyspdp .L1 a1,a1:a0,a1:a0
+ mpyspdp .M1 a1,a1:a0,a1:a0,a1:a0
+ mpyspdp .M1 b1,a1:a0,a1:a0
+ mpyspdp .M2X b1,b1:b0,b1:b0
+ mpysp2dp .S1 a1,a2,a3:a2
+ mpysp2dp .M1 a1,a2
+ mpysp2dp .M1 b1,a2,a3:a2
+ mpysp2dp .M2X b1,b2,b3:b2
+ mpysu .D1 a1,a2,a3
+ mpysu .M1 a1,a2
+ mpysu .M1 b1,a2,a3
+ mpysu .M2X b1,b2,b3
+ mpysu .M1 -17,a2,a3
+ mpysu .M2 16,b2,b3
+ mpysu4 .S1 a1,a2,a3:a2
+ mpysu4 .M1 a1,a2
+ mpysu4 .M1 b1,a2,a3:a2
+ mpysu4 .M2X b1,b2,b3:b2
+ mpyu .L1 a1,a2,a3
+ mpyu .M1 a1,a2
+ mpyu .M1 b1,a2,a3
+ mpyu .M2X b1,b2,b3
+ mpyu4 .D1 a1,a2,a3:a2
+ mpyu4 .M1 a1,a2
+ mpyu4 .M1 b1,a2,a3:a2
+ mpyu4 .M2X b1,b2,b3:b2
+ mpyus .S1 a1,a2,a3
+ mpyus .M1 a1,a2
+ mpyus .M1 b1,a2,a3
+ mpyus .M2X b1,b2,b3
+ mpyus4 .L1 a1,a2,a3:a2
+ mpyus4 .M1 a1,a2
+ mpyus4 .M1 b1,a2,a3:a2
+ mpyus4 .M2X b1,b2,b3:b2
+ mpy2 .D1 a1,a2,a3:a2
+ mpy2 .M1 a1,a2
+ mpy2 .M1 b1,a2,a3:a2
+ mpy2 .M2X b1,b2,b3:b2
+ mpy2ir .L1 a1,a2,a3:a2
+ mpy2ir .M1 a1,a2
+ mpy2ir .M1 b1,a2,a3:a2
+ mpy2ir .M2X b1,b2,b3:b2
+ mpy32 .L1 a1,a2,a3
+ mpy32 .M1 a1,a2
+ mpy32 .M1 b1,a2,a3
+ mpy32 .M2X b1,b2,b3
+ mpy32 .M1 b1,a2,a3:a2
+ mpy32 .M1X a1,a2,a5:a4
+ mpy32su .L1 a1,a2,a3:a2
+ mpy32su .M1 a1,a2
+ mpy32su .M2X b1,b2,b3:b2
+ mpy32su .M1 b1,a2,a3:a2
+ mpy32u .L1 a1,a2,a3:a2
+ mpy32u .M1 a1,a2
+ mpy32u .M2X b1,b2,b3:b2
+ mpy32u .M1 b1,a2,a3:a2
+ mpy32us .L1 a1,a2,a3:a2
+ mpy32us .M1 a1,a2
+ mpy32us .M2X b1,b2,b3:b2
+ mpy32us .M1 b1,a2,a3:a2
+ mvc .L2 b2,amr
+ mvc .S2X amr,a1
+ mvc .S2 b2,nonesuch
+ mvc .S2 b0,dnum
+ mvc .S2 ecr,b0
+ mvc .S2 b0,efr
+ mvc .S2 icr,b0
+ mvc .S2 b0,ifr
+ mvc .S2 isr,b0
+ mvc .S2 b0,pce1
+ mvc .S2 b0,tsch
+ mvc .S2 b0,tscl
+ mv .M1 a1,a2
+ mv .L1 a1,a2,a3
+ mv .L1 a1,b2
+ mv .L2X b1,b2
+ mv .S1 a1,b2
+ mv .S2X b1,b2
+ mv .D1 a1,b2
+ mv .D2X b1,b2
+ mvd .L1 a1,a2
+ mvd .M1 a3,a4,a5
+ mvd .M1 a1,b2
+ mvd .M2X b3,b4
+ mvk .L1 -17,a0
+ mvk .L1 16,a0
+ mvk .L1X 0,a0
+ mvk .D2 -17,b0
+ mvk .D2 16,b0
+ mvk .D2X 0,b0
+ norm .S1 a1,a0
+ norm .L1 a1:a0,a0,a0
+ norm .L1X b1:b0,a1
+ norm .L2 b1,a1
+ norm .L2X b1,b1
+ or .M1 a1,a2,a3
+ or .L1 a1,a2
+ or .D1 -17,a0,a0
+ or .D1X 16,b0,a0
+ or .L1 -17,a0,a0
+ or .L1X 16,b0,a0
+ or .S2 -17,b0,b0
+ or .S2X 16,a0,b0
+ or .D1 a0,a0,b0
+ or .D2X b0,b0,b0
+ or .L1X a0,a0,a0
+ or .S2 b0,b0,a0
+ pack2 .D1 a0,a0,a0
+ pack2 .L1 a0,a0
+ pack2 .S1 a0,a1,b2
+ pack2 .L2X b0,b0,b0
+ packh2 .M1 a0,a0,a0
+ packh2 .L1 a0,a0
+ packh2 .S1 a0,a1,b2
+ packh2 .L2X b0,b0,b0
+ packh4 .S1 a0,a0,a0
+ packh4 .L1 a0,a0
+ packh4 .L1 a0,a1,b2
+ packh4 .L2X b0,b0,b0
+ packhl2 .M1 a0,a0,a0
+ packhl2 .L1 a0,a0
+ packhl2 .S1 a0,a1,b2
+ packhl2 .L2X b0,b0,b0
+ packlh2 .D1 a0,a0,a0
+ packlh2 .L1 a0,a0
+ packlh2 .S1 a0,a1,b2
+ packlh2 .L2X b0,b0,b0
+ packl4 .S1 a0,a0,a0
+ packl4 .L1 a0,a0
+ packl4 .L1 a0,a1,b2
+ packl4 .L2X b0,b0,b0
+ rcpdp .L1 a1:a0,a1:a0
+ rcpdp .S1 a1:a0
+ rcpdp .S1 b1:b0,a1:a0
+ rcpdp .S2X a1:a0,b1:b0
+ rcpsp .L1 a0,a0
+ rcpsp .S1 a0,a0,a0
+ rcpsp .S2 b0,a0
+ rcpsp .S1X a0,a0
+ rint .S2
+ rint a0
+ rotl .S1 a0,a0,a0
+ rotl .M1 a0,a0
+ rotl .M1 a0,b0,a0
+ rotl .M2X b0,b0,b0
+ rotl .M1 a0,-1,a0
+ rotl .M2 b0,32,b0
+ rotl .M2X b0,0,b0
+ rpack2 .L1 a0,a0,a0
+ rpack2 .S1 a0,a0
+ rpack2 .S2 a0,b0,b0
+ rpack2 .S1X a0,a0,a0
+ rsqrdp .L1 a1:a0,a1:a0
+ rsqrdp .S1 a1:a0
+ rsqrdp .S1 b1:b0,a1:a0
+ rsqrdp .S2X a1:a0,b1:b0
+ rsqrsp .L1 a0,a0
+ rsqrsp .S1 a0,a0,a0
+ rsqrsp .S2 b0,a0
+ rsqrsp .S1X a0,a0
+ sadd .D1 a1,a2,a3
+ sadd .L1 a1,a2
+ sadd .S1 0,a1,a2
+ sadd .L1X 0,a1:a0,a1:a0
+ sadd .L1 b0,a0,a0
+ sadd .L1X a0,a0,a0
+ sadd .L2 -17,b0,b0
+ sadd .L2 16,b0,b0
+ sadd .L1 -17,a1:a0,a1:a0
+ sadd .L1 16,a1:a0,a1:a0
+ sadd2 .L1 a0,a0,a0
+ sadd2 .S1 a0,a0
+ sadd2 .S2 a0,b0,b0
+ sadd2 .S2X b0,b0,b0
+ saddsub .S1 a0,a0,a1:a0
+ saddsub .L1 a0,a0
+ saddsub .L1 a0,a0,a0
+ saddsub .L2 a0,b0,b1:b0
+ saddsub .L2X b0,b0,b1:b0
+ saddsub2 .S1 a0,a0,a1:a0
+ saddsub2 .L1 a0,a0
+ saddsub2 .L1 a0,a0,a0
+ saddsub2 .L2 a0,b0,b1:b0
+ saddsub2 .L2X b0,b0,b1:b0
+ saddsu2 .L1 a0,a0,a0
+ saddsu2 .S1 a0
+ saddsu2 .S2 b0,a0,b0
+ saddsu2 .S2X b0,b0,b0
+ saddus2 .M1 a0,a0,a0
+ saddus2 .S1 a0,a0
+ saddus2 .S1 b0,a0,a0
+ saddus2 .S1X a0,a0,a0
+ saddu4 .D1 a0,a0,a0
+ saddu4 .S1 a0,a0
+ saddu4 .S1 b0,a0,a0
+ saddu4 .S1X a0,a0,a0
+ sat .S1 a1:a0,a0
+ sat .L1X b1:b0,a0
+ sat .L1 a1:a0
+ sat .L1 b1:b0,a0
+ set .L1 a0,0,0,a0
+ set .S1 a0
+ set .S1 a0,-1,0,a0
+ set .S1 a0,32,0,a0
+ set .S1 a0,0,-1,a0
+ set .S1 a0,0,32,a0
+ set .S1X b0,0,0,a0
+ set .S1X a0,a0,a0
+ set .S2 b0,a0,b0
+ shfl .S1 a0,a0
+ shfl .M1 a0,a0,a0
+ shfl .M1 a0,b0
+ shfl .M2X b0,b0
+ shfl3 .M1 a0,a0,a1:a0
+ shfl3 .L1 a0,a0
+ shfl3 .L1 b0,a0,a1:a0
+ shfl3 .L2X b0,b0,b1:b0
+ shl .L1 a0,a0,a0
+ shl .S1 a0,a0
+ shl .S1X a1:a0,a0,a1:a0
+ shl .S1 a0,b0,a0
+ shl .S2X b0,b0,b1:b0
+ shl .S1 a0,-1,a0
+ shl .S1 a0,32,a0
+ shl .S2 b1:b0,-1,b1:b0
+ shl .S2 b1:b0,32,b1:b0
+ shl .S1X b0,-1,a1:a0
+ shl .S1X b0,32,a1:a0
+ shlmb .D1 a0,a0,a0
+ shlmb .L1 a0,a0
+ shlmb .L1 b0,a0,a0
+ shlmb .L2X b0,b0,b0
+ shlmb .S1 b0,a0,a0
+ shlmb .S2X b0,b0,b0
+ shr .L1 a0,a0,a0
+ shr .S1 a0,a0
+ shr .S1X a1:a0,a0,a1:a0
+ shr .S1 a0,b0,a0
+ shr .S1 a0,-1,a0
+ shr .S1 a0,32,a0
+ shr .S2 b1:b0,-1,b1:b0
+ shr .S2 b1:b0,32,b1:b0
+ shr2 .L1 a0,a0,a0
+ shr2 .L1 a0,0,a0
+ shr2 .S1 a0,a0
+ shr2 .S1 a1,b0,a0
+ shr2 .S2X b0,b0,b0
+ shr2 .S1 a0,-1,a0
+ shr2 .S1 a0,32,a0
+ shrmb .M1 a0,a0,a0
+ shrmb .L1 a0,a0
+ shrmb .L1 b0,a0,a0
+ shrmb .L2X b0,b0,b0
+ shrmb .S1 b0,a0,a0
+ shrmb .S2X b0,b0,b0
+ shru .D1 a0,a0,a0
+ shru .S1 a0,a0
+ shru .S1X a1:a0,a0,a1:a0
+ shru .S1 a0,b0,a0
+ shru .S1 a0,-1,a0
+ shru .S1 a0,32,a0
+ shru .S2 b1:b0,-1,b1:b0
+ shru .S2 b1:b0,32,b1:b0
+ shru2 .L1 a0,a0,a0
+ shru2 .L1 a0,0,a0
+ shru2 .S1 a0,a0
+ shru2 .S1 a1,b0,a0
+ shru2 .S2X b0,b0,b0
+ shru2 .S1 a0,-1,a0
+ shru2 .S1 a0,32,a0
+ smpy .L1 a0,a0,a0
+ smpy .M1 a0,a0
+ smpy .M2 a0,b0,b0
+ smpy .M1X a0,a0,a0
+ smpyh .S1 a0,a0,a0
+ smpyh .M1 a0,a0
+ smpyh .M2 a0,b0,b0
+ smpyh .M1X a0,a0,a0
+ smpyhl .D1 a0,a0,a0
+ smpyhl .M1 a0,a0
+ smpyhl .M2 a0,b0,b0
+ smpyhl .M1X a0,a0,a0
+ smpylh .L1 a0,a0,a0
+ smpylh .M1 a0,a0
+ smpylh .M2 a0,b0,b0
+ smpylh .M1X a0,a0,a0
+ smpy2 .S1 a0,a0,a1:a0
+ smpy2 .M1 a0,a0
+ smpy2 .M2 a0,b0,b1:b0
+ smpy2 .M2X b0,b0,b1:b0
+ smpy32 .L1 a0,a0,a0
+ smpy32 .M1 a0,a0
+ smpy32 .M2 a0,b0,b0
+ smpy32 .M1X a0,a0,a0
+ spack2 .L1 a0,a0,a0
+ spack2 .S1 a0,a0
+ spack2 .S1 b0,a0,a0
+ spack2 .S2X b0,b0,b0
+ spacku4 .L1 a0,a0,a0
+ spacku4 .S1 a0,a0
+ spacku4 .S1 b0,a0,a0
+ spacku4 .S2X b0,b0,b0
+ spdp .M1 a0,a1:a0
+ spdp .S1 a0
+ spdp .S1 a0,b1:b0
+ spdp .S2X b0,b1:b0
+ spint .S1 a0,a0
+ spint .L1 a0,a0,a0
+ spint .L2 b0,a0
+ spint .L1X a0,a0
+ sptrunc .D1 a0,a0
+ sptrunc .L1 a0,a0,a0
+ sptrunc .L2 b0,a0
+ sptrunc .L1X a0,a0
+ sshl .L1 a0,a0,a0
+ sshl .S1 a0,a0
+ sshl .S1 a0,b0,a0
+ sshl .S1X a0,a0,a0
+ sshl .S2 b0,-1,b0
+ sshl .S2 b0,32,b0
+ sshvl .S1 a0,a0,a0
+ sshvl .M1 a0,a0
+ sshvl .M1 a0,b0,a0
+ sshvl .M1X a0,a0,a0
+ sshvr .L1 a0,a0,a0
+ sshvr .M1 a0,a0
+ sshvr .M1 a0,b0,a0
+ sshvr .M1X a0,a0,a0
+ ssub .S1 a0,a0,a0
+ ssub .L1 a0,a0
+ ssub .L1 a0,a0,b0
+ ssub .L1X a0,a0,a0
+ ssub .L2 -17,b0,b0
+ ssub .L2 16,b0,b0
+ ssub .L1X 0,a1:a0,a1:a0
+ ssub .L1 -17,a1:a0,a1:a0
+ ssub .L1 16,a1:a0,a1:a0
+ ssub2 .S1 a0,a0,a0
+ ssub2 .L1 a0,a0
+ ssub2 .L1 a0,b0,a0
+ ssub2 .L1X a0,a0,a0
+ stb .L1 a0,*a1
+ stb .D1T1 b1,*a1
+ stb .D1T1 a1,*b1
+ stb .D2T2 b1,*a1
+ stb .D2T2 a1,*b1
+ stb .D1T1 *a1
+ stb .D1T1 a2,*+a1[b1]
+ stb .D1T1 a2,*+a1
+ stb .D1T1 a2,*-a1
+ stb .D1T1 a2,*a1++[32]
+ stb .D1T1 a2,*a1++(32)
+ stb .D1T1 a2,*--a1[-1]
+ stb .D1T1 a2,*--a1(-1)
+ stb .D1T1 a3,*+a1(a2)
+ stb .D2T2 b16,*+b14[foo]
+ stb .D2T2 b1,*+b14[-1]
+ stb .D2T2 b1,*+b14[32768]
+ stdw .L1 a1:a0,*a1
+ stdw .D1T1 b1:b0,*a1
+ stdw .D1T1 a1:a0,*b1
+ stdw .D2T2 b1:b0,*a1
+ stdw .D2T2 a1:a0,*b1
+ stdw .D1T1 *a1
+ stdw .D1T1 a3:a2,*+a1[b1]
+ stdw .D1T1 a3:a2,*+a1
+ stdw .D1T1 a3:a2,*-a1
+ stdw .D1T1 a3:a2,*a1++[32]
+ stdw .D1T1 a3:a2,*a1++(256)
+ stdw .D1T1 a3:a2,*--a1[-1]
+ stdw .D1T1 a3:a2,*--a1(-8)
+ stdw .D1T1 a3:a2,*+a1(a2)
+ stdw .D2T2 b17:b16,*+b14[foo]
+ stdw .D1T1 a3:a2,*+a1(1)
+ stdw .D2T2 b17:b16,*+b14(b15)
+ sth .M1 a0,*a1
+ sth .D1T1 b1,*a1
+ sth .D1T1 a1,*b1
+ sth .D2T2 b1,*a1
+ sth .D2T2 a1,*b1
+ sth .D1T1 *a1
+ sth .D1T1 a2,*+a1[b1]
+ sth .D1T1 a2,*+a1
+ sth .D1T1 a2,*-a1
+ sth .D1T1 a2,*a1++[32]
+ sth .D1T1 a2,*a1++(64)
+ sth .D1T1 a2,*--a1[-1]
+ sth .D1T1 a2,*--a1(-2)
+ sth .D1T1 a3,*+a1(a2)
+ sth .D2T2 b16,*+b14[foo]
+ sth .D2T2 b2,*+b1(1)
+ sth .D2T2 b1,*+b14[-1]
+ sth .D2T2 b1,*+b14[32768]
+ stndw .L1 a1:a0,*a1
+ stndw .D1T1 b1:b0,*a1
+ stndw .D1T1 a1:a0,*b1
+ stndw .D2T2 b1:b0,*a1
+ stndw .D2T2 a1:a0,*b1
+ stndw .D1T1 *a1
+ stndw .D1T1 a3:a2,*+a1[b1]
+ stndw .D1T1 a3:a2,*+a1
+ stndw .D1T1 a3:a2,*-a1
+ stndw .D1T1 a3:a2,*a1++[32]
+ stndw .D1T1 a3:a2,*a1++(32)
+ stndw .D1T1 a3:a2,*--a1[-1]
+ stndw .D1T1 a3:a2,*--a1(-1)
+ stndw .D2T2 b17:b16,*+b14[foo]
+ stnw .S1 a0,*a1
+ stnw .D1T1 b1,*a1
+ stnw .D1T1 a1,*b1
+ stnw .D2T2 b1,*a1
+ stnw .D2T2 a1,*b1
+ stnw .D1T1 *a1
+ stnw .D1T1 a2,*+a1[b1]
+ stnw .D1T1 a2,*+a1
+ stnw .D1T1 a2,*-a1
+ stnw .D1T1 a2,*a1++[32]
+ stnw .D1T1 a2,*a1++(128)
+ stnw .D1T1 a2,*--a1[-1]
+ stnw .D1T1 a2,*--a1(-4)
+ stnw .D1T1 a3,*+a1(a2)
+ stnw .D2T2 b16,*+b14[foo]
+ stnw .D2T2 b2,*+b1(2)
+ stw .S1 a0,*a1
+ stw .D1T1 b1,*a1
+ stw .D1T1 a1,*b1
+ stw .D2T2 b1,*a1
+ stw .D2T2 a1,*b1
+ stw .D1T1 *a1
+ stw .D1T1 a2,*+a1[b1]
+ stw .D1T1 a2,*+a1
+ stw .D1T1 a2,*-a1
+ stw .D1T1 a2,*a1++[32]
+ stw .D1T1 a2,*a1++(128)
+ stw .D1T1 a2,*--a1[-1]
+ stw .D1T1 a2,*--a1(-4)
+ stw .D1T1 a3,*+a1(a2)
+ stw .D2T2 b16,*+b14[foo]
+ stw .D2T2 b2,*+b1(2)
+ stw .D2T2 b1,*+b14[-1]
+ stw .D2T2 b1,*+b14[32768]
+ neg .D1 a1,a2
+ neg .S1 a1:a0,a1:a0
+ neg .S1 a1,a1,a1
+ neg .S1 a1,b1
+ neg .S1X a1,a1
+ neg .L2X b1:b0,b1:b0
+ neg .L2 b0,a0
+ neg .L2X b0,b0
+ sub .M1 a0,a0,a0
+ sub .L1 a0,a0
+ sub .L1 b0,b0,a0
+ sub .L2X b0,b0,b0
+ sub .L1X 0,a1:a0,a1:a0
+ sub .L2 -17,b0,b0
+ sub .L2 16,b0,b0
+ sub .L1 -17,a1:a0,a1:a0
+ sub .L1 16,a1:a0,a1:a0
+ sub .S1 a0,a0
+ sub .S1 a0,a0,b0
+ sub .S1X a0,a0,a0
+ sub .S1 -17,a0,a0
+ sub .S1 16,a0,a0
+ sub .S1 0,a1:a0,a1:a0
+ sub .D1 a0
+ sub .D1 b0,a0,a0
+ sub .D1X a0,a0,a0
+ sub .D1X b0,0,a0
+ sub .D1 a0,-1,a0
+ sub .D1 a0,32,a0
+ subab .S1 a0,a0,a0
+ subab .D1 a0,a0
+ subab .D1 a0,b0,a0
+ subab .D1X a0,b0,a0
+ subab .D1X b0,0,a0
+ subab .D2 b0,-1,b0
+ subab .D2 b14,32,b14
+ subabs4 .S1 a0,a0,a0
+ subabs4 .L1 a0,a0
+ subabs4 .L1 a0,a0,b0
+ subabs4 .L2X b0,b0,b0
+ subah .M1 a0,a0,a0
+ subah .D1 a0,a0
+ subah .D1 a0,b0,a0
+ subah .D1X a0,b0,a0
+ subah .D1X b0,0,a0
+ subah .D2 b0,-1,b0
+ subah .D2 b14,32,b14
+ subaw .L1 a0,a0,a0
+ subaw .D1 a0,a0
+ subaw .D1 a0,b0,a0
+ subaw .D1X a0,b0,a0
+ subaw .D1X b0,0,a0
+ subaw .D2 b0,-1,b0
+ subaw .D2 b14,32,b14
+ subc .S1 a0,a0,a0
+ subc .L1 a0,a0
+ subc .L1 b0,a0,a0
+ subc .L2X b0,b0,b0
+ subdp .D1 a1:a0,a1:a0,a1:a0
+ subdp .L1 a1:a0
+ subdp .L1 b1:b0,a1:a0,a1:a0
+ subdp .L1X a1:a0,a1:a0,a1:a0
+ subdp .S1 b1:b0,a1:a0,a1:a0
+ subdp .S1X a1:a0,a1:a0,a1:a0
+ subsp .M1 a0,a0,a0
+ subsp .L1 a0,a0
+ subsp .L1 a0,a0,b0
+ subsp .L2X b0,b0,b0
+ subsp .S1 a0,a0
+ subsp .S1 a0,a0,b0
+ subsp .S2X b0,b0,b0
+ subu .S1 a0,a0,a1:a0
+ subu .L1 a0,a0
+ subu .L1 a0,a0,a0
+ subu .L2 b0,b0,a1:a0
+ subu .L1X a0,a0,a1:a0
+ sub2 .M1 a0,a0,a0
+ sub2 .L1 a0,a0
+ sub2 .L1 a0,a0,b0
+ sub2 .L2X b0,b0,b0
+ sub2 .S1 a0,a0
+ sub2 .S1 a0,a0,b0
+ sub2 .S2X b0,b0,b0
+ sub2 .D1 a0,a0
+ sub2 .D1 a0,a0,b0
+ sub2 .D2X b0,b0,b0
+ sub4 .S1 a0,a0,a0
+ sub4 .L1 a0,a0
+ sub4 .L1 a0,a0,b0
+ sub4 .L2X b0,b0,b0
+ swap2 .D1 a0,a0
+ swap2 .L1 a0,a0,a0
+ swap2 .L1X b0,a0
+ swap2 .L2 a0,b0
+ swap2 .S1 a0,a0,a0
+ swap2 .S1X b0,a0
+ swap2 .S2 a0,b0
+ swap4 .S1 a0,a0
+ swap4 .L1 a0
+ swap4 .L1 a0,b0
+ swap4 .L1X a0,a0
+ swe .S1
+ swe a0
+ swenr .L1
+ swenr b0
+ unpkhu4 .D1 a0,a0
+ unpkhu4 .L1 a0,a0,a0
+ unpkhu4 .L1 a0,b0
+ unpkhu4 .L2X b0,b0
+ unpkhu4 .S1 a0,a0,a0
+ unpkhu4 .S1 a0,b0
+ unpkhu4 .S2X b0,b0
+ unpklu4 .M1 a0,a0
+ unpklu4 .L1 a0,a0,a0
+ unpklu4 .L1 a0,b0
+ unpklu4 .L2X b0,b0
+ unpklu4 .S1 a0,a0,a0
+ unpklu4 .S1 a0,b0
+ unpklu4 .S2X b0,b0
+ not .M1 a0,a0
+ not .L1 a0,a0,a0
+ not .L1 a0,b0
+ not .L1X a0,a0
+ not .S1 a0,a0,a0
+ not .S1 a0,b0
+ not .S1X a0,a0
+ not .D1 a0,a0,a0
+ not .D1 a0,b0
+ not .D1X a0,a0
+ xor .M1 a0,a0,a0
+ xor .L1 a0,a0
+ xor .L2 b0,b0,a0
+ xor .L2X b0,b0,b0
+ xor .L1 -17,a0,a0
+ xor .L1 16,a0,a0
+ xor .S1 a0,a0
+ xor .S2 b0,b0,a0
+ xor .S2X b0,b0,b0
+ xor .S1 -17,a0,a0
+ xor .S1 16,a0,a0
+ xor .D1 a0,a0
+ xor .D2 b0,b0,a0
+ xor .D2X b0,b0,b0
+ xor .D1 -17,a0,a0
+ xor .D1 16,a0,a0
+ xormpy .L1 a0,a0,a0
+ xormpy .M1 a0,a0
+ xormpy .M1 b0,a0,a0
+ xormpy .M1X a0,a0,a0
+ xpnd2 .S1 a0,a0
+ xpnd2 .M1 a0,a0,a0
+ xpnd2 .M1 a0,b0
+ xpnd2 .M1X a0,a0
+ xpnd4 .L1 a0,a0
+ xpnd4 .M1 a0,a0,a0
+ xpnd4 .M1 a0,b0
+ xpnd4 .M1X a0,a0
+ zero .M1 a0
+ zero .L1 a0,a0
+ zero .L2 a0
+ zero .D1 a0,a0
+ zero .D2 a0
+ zero .S1 a0,a0
+ zero .S2 a0
+ sub .L1 a0,17,a0
+ sub .L1 a0,-16,a0
+ sub .L1 a1:a0,17,a1:a0
+ sub .L1 a1:a0,-16,a1:a0
+ sub .S1 a0,17,a0
+ sub .S1 a0,-16,a0
+ addab .D1X b13,0,a5
+ addah .D1X b13,0,a5
+ addaw .D1X b13,0,a5
--- /dev/null
+#name: C6X bad instructions 2
+#as: -march=c62x
+#error-output: insns-bad-2.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:6: Error: register number 31 not supported on this architecture
+[^:]*:7: Error: register number 31 not supported on this architecture
+[^:]*:8: Error: register number 31 not supported on this architecture
+[^:]*:9: Error: register number 31 not supported on this architecture
+[^:]*:24: Error: register number 31 not supported on this architecture
+[^:]*:25: Error: register number 31 not supported on this architecture
+[^:]*:26: Error: register number 31 not supported on this architecture
+[^:]*:27: Error: register number 31 not supported on this architecture
+[^:]*:42: Error: register number 31 not supported on this architecture
+[^:]*:43: Error: register number 31 not supported on this architecture
+[^:]*:44: Error: register number 31 not supported on this architecture
+[^:]*:45: Error: register number 31 not supported on this architecture
+[^:]*:46: Error: register number 31 not supported on this architecture
+[^:]*:47: Error: register number 30 not supported on this architecture
--- /dev/null
+# Test bad registers depending on architecture
+.text
+.globl f
+f:
+ abs .L1 a15,a15
+ abs .L1 a31,a15
+ abs .L1 a15,a31
+ abs .L2X a15,b31
+ abs .L2X a31,b15
+.arch c64x
+ abs .L1 a15,a15
+ abs .L1 a31,a15
+ abs .L1 a15,a31
+ abs .L2X a15,b31
+ abs .L2X a31,b15
+.arch c64x+
+ abs .L1 a15,a15
+ abs .L1 a31,a15
+ abs .L1 a15,a31
+ abs .L2X a15,b31
+ abs .L2X a31,b15
+.arch c67x
+ abs .L1 a15,a15
+ abs .L1 a31,a15
+ abs .L1 a15,a31
+ abs .L2X a15,b31
+ abs .L2X a31,b15
+.arch c67x+
+ abs .L1 a15,a15
+ abs .L1 a31,a15
+ abs .L1 a15,a31
+ abs .L2X a15,b31
+ abs .L2X a31,b15
+.arch c674x
+ abs .L1 a15,a15
+ abs .L1 a31,a15
+ abs .L1 a15,a31
+ abs .L2X a15,b31
+ abs .L2X a31,b15
+.arch c62x
+ abs .L1 a15,a15
+ abs .L1 a31,a15
+ abs .L1 a15,a31
+ abs .L2X a15,b31
+ abs .L2X a31,b15
+ ldb .D1T1 *a31,a0
+ ldb .D1T1 *+a1[a30],a0
--- /dev/null
+#name: C674x bad instructions
+#as: -march=c674x
+#error-output: insns-c674x-bad.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:6: Error: 'cmtl' instruction not supported on this architecture
+[^:]*:7: Error: 'll' instruction not supported on this architecture
+[^:]*:8: Error: 'sl' instruction not supported on this architecture
+[^:]*:14: Error: 'cmtl' instruction not supported on this architecture
+[^:]*:15: Error: 'll' instruction not supported on this architecture
+[^:]*:16: Error: 'sl' instruction not supported on this architecture
--- /dev/null
+# Test instructions not present on C674x.
+.text
+.nocmp
+.globl f
+f:
+ cmtl .D2T2 *b0,b1
+ ll .D2T2 *b0,b1
+ sl .D2T2 b0,*b1
+.atomic
+ cmtl .D2T2 *b0,b1
+ ll .D2T2 *b0,b1
+ sl .D2T2 b0,*b1
+.noatomic
+ cmtl .D2T2 *b0,b1
+ ll .D2T2 *b0,b1
+ sl .D2T2 b0,*b1
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C674x instructions generating PC-relative relocations
+#as: -march=c674x -mlittle-endian
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+[ \t]*\.\.\.
+0+1c <[^>]*> 00806162[ \t]+addkpc \.S2 00000000 <f>,b1,3
+0+20 <[^>]*> a1f9e162[ \t]+\[a2\] addkpc \.S2 00000004 <f\+0x4>,b3,7
+0+24 <[^>]*> 02030162[ \t]+addkpc \.S2 0000002c <g>,b4,0
+0+28 <[^>]*> 02808162[ \t]+addkpc \.S2 00000020 <f\+0x20>,b5,4
+[ \t]*28: R_C6000_PCR_S7[ \t]+ext1\+0x8
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+48 <[^>]*> 00000012[ \t]+b \.S2 00000040 <f2>
+[ \t]*48: R_C6000_PCR_S21[ \t]+ext3\+0x4
+0+4c <[^>]*> 00000010[ \t]+b \.S1 00000040 <f2>
+[ \t]*4c: R_C6000_PCR_S21[ \t]+ext2
+0+50 <[^>]*> 00000012[ \t]+b \.S2 00000040 <f2>
+[ \t]*50: R_C6000_PCR_S21[ \t]+nrp
+0+54 <[^>]*> 00000012[ \t]+b \.S2 00000040 <f2>
+[ \t]*54: R_C6000_PCR_S21[ \t]+irp
+0+58 <[^>]*> 00000010[ \t]+b \.S1 00000040 <f2>
+[ \t]*58: R_C6000_PCR_S21[ \t]+a1
+0+5c <[^>]*> 00000012[ \t]+b \.S2 00000040 <f2>
+0+60 <[^>]*> 6ffffc92[ \t]+\[b2\] b \.S2 00000044 <f2\+0x4>
+0+64 <[^>]*> 00000192[ \t]+b \.S2 0000006c <g2>
+0+68 <[^>]*> 00000012[ \t]+b \.S2 00000060 <f2\+0x20>
+[ \t]*68: R_C6000_PCR_S21[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+88 <[^>]*> 00000012[ \t]+b \.S2 00000080 <f3>
+[ \t]*88: R_C6000_PCR_S21[ \t]+ext3\+0x4
+0+8c <[^>]*> 00000010[ \t]+b \.S1 00000080 <f3>
+[ \t]*8c: R_C6000_PCR_S21[ \t]+ext2
+0+90 <[^>]*> 00000012[ \t]+b \.S2 00000080 <f3>
+[ \t]*90: R_C6000_PCR_S21[ \t]+nrp
+0+94 <[^>]*> 00000012[ \t]+b \.S2 00000080 <f3>
+[ \t]*94: R_C6000_PCR_S21[ \t]+irp
+0+98 <[^>]*> 00000010[ \t]+b \.S1 00000080 <f3>
+[ \t]*98: R_C6000_PCR_S21[ \t]+a1
+0+9c <[^>]*> 00000012[ \t]+b \.S2 00000080 <f3>
+0+a0 <[^>]*> 6ffffc92[ \t]+\[b2\] b \.S2 00000084 <f3\+0x4>
+0+a4 <[^>]*> 00000192[ \t]+b \.S2 000000ac <g3>
+0+a8 <[^>]*> 00000012[ \t]+b \.S2 000000a0 <f3\+0x20>
+[ \t]*a8: R_C6000_PCR_S21[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+c8 <[^>]*> 01001022[ \t]+bdec \.S2 000000c0 <f4>,b2
+[ \t]*c8: R_C6000_PCR_S10[ \t]+ext3\+0x4
+0+cc <[^>]*> 01001020[ \t]+bdec \.S1 000000c0 <f4>,a2
+[ \t]*cc: R_C6000_PCR_S10[ \t]+ext2
+0+d0 <[^>]*> 01001022[ \t]+bdec \.S2 000000c0 <f4>,b2
+[ \t]*d0: R_C6000_PCR_S10[ \t]+nrp
+0+d4 <[^>]*> 01001022[ \t]+bdec \.S2 000000c0 <f4>,b2
+[ \t]*d4: R_C6000_PCR_S10[ \t]+irp
+0+d8 <[^>]*> 01001020[ \t]+bdec \.S1 000000c0 <f4>,a2
+[ \t]*d8: R_C6000_PCR_S10[ \t]+a1
+0+dc <[^>]*> 01001022[ \t]+bdec \.S2 000000c0 <f4>,b2
+0+e0 <[^>]*> 917f3022[ \t]+\[!a1\] bdec \.S2 000000c4 <f4\+0x4>,b2
+0+e4 <[^>]*> 01007022[ \t]+bdec \.S2 000000ec <g4>,b2
+0+e8 <[^>]*> 01001022[ \t]+bdec \.S2 000000e0 <f4\+0x20>,b2
+[ \t]*e8: R_C6000_PCR_S10[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+108 <[^>]*> 01000022[ \t]+bpos \.S2 00000100 <f5>,b2
+[ \t]*108: R_C6000_PCR_S10[ \t]+ext3\+0x4
+0+10c <[^>]*> 01000020[ \t]+bpos \.S1 00000100 <f5>,a2
+[ \t]*10c: R_C6000_PCR_S10[ \t]+ext2
+0+110 <[^>]*> 01000022[ \t]+bpos \.S2 00000100 <f5>,b2
+[ \t]*110: R_C6000_PCR_S10[ \t]+nrp
+0+114 <[^>]*> 01000022[ \t]+bpos \.S2 00000100 <f5>,b2
+[ \t]*114: R_C6000_PCR_S10[ \t]+irp
+0+118 <[^>]*> 01000020[ \t]+bpos \.S1 00000100 <f5>,a2
+[ \t]*118: R_C6000_PCR_S10[ \t]+a1
+0+11c <[^>]*> 01000022[ \t]+bpos \.S2 00000100 <f5>,b2
+0+120 <[^>]*> 517f2022[ \t]+\[!b1\] bpos \.S2 00000104 <f5\+0x4>,b2
+0+124 <[^>]*> 01006022[ \t]+bpos \.S2 0000012c <g5>,b2
+0+128 <[^>]*> 01000022[ \t]+bpos \.S2 00000120 <f5\+0x20>,b2
+[ \t]*128: R_C6000_PCR_S10[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+148 <[^>]*> 00000122[ \t]+bnop \.S2 00000140 <f6>,0
+[ \t]*148: R_C6000_PCR_S12[ \t]+ext3\+0x4
+0+14c <[^>]*> 00002120[ \t]+bnop \.S1 00000140 <f6>,1
+[ \t]*14c: R_C6000_PCR_S12[ \t]+ext2
+0+150 <[^>]*> 00004120[ \t]+bnop \.S1 00000140 <f6>,2
+[ \t]*150: R_C6000_PCR_S12[ \t]+nrp
+0+154 <[^>]*> 00006122[ \t]+bnop \.S2 00000140 <f6>,3
+[ \t]*154: R_C6000_PCR_S12[ \t]+irp
+0+158 <[^>]*> 00008120[ \t]+bnop \.S1 00000140 <f6>,4
+[ \t]*158: R_C6000_PCR_S12[ \t]+a1
+0+15c <[^>]*> 0000a122[ \t]+bnop \.S2 00000140 <f6>,5
+0+160 <[^>]*> 5ff9c122[ \t]+\[!b1\] bnop \.S2 00000144 <f6\+0x4>,6
+0+164 <[^>]*> 0003e120[ \t]+bnop \.S1 0000016c <g6>,7
+0+168 <[^>]*> 00000122[ \t]+bnop \.S2 00000160 <f6\+0x20>,0
+[ \t]*168: R_C6000_PCR_S12[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+188 <[^>]*> 00000122[ \t]+bnop \.S2 00000180 <f7>,0
+[ \t]*188: R_C6000_PCR_S12[ \t]+ext3\+0x4
+0+18c <[^>]*> 00002120[ \t]+bnop \.S1 00000180 <f7>,1
+[ \t]*18c: R_C6000_PCR_S12[ \t]+ext2
+0+190 <[^>]*> 00004120[ \t]+bnop \.S1 00000180 <f7>,2
+[ \t]*190: R_C6000_PCR_S12[ \t]+nrp
+0+194 <[^>]*> 00006122[ \t]+bnop \.S2 00000180 <f7>,3
+[ \t]*194: R_C6000_PCR_S12[ \t]+irp
+0+198 <[^>]*> 00008120[ \t]+bnop \.S1 00000180 <f7>,4
+[ \t]*198: R_C6000_PCR_S12[ \t]+a1
+0+19c <[^>]*> 0000a122[ \t]+bnop \.S2 00000180 <f7>,5
+0+1a0 <[^>]*> cff9c122[ \t]+\[a0\] bnop \.S2 00000184 <f7\+0x4>,6
+0+1a4 <[^>]*> 0003e120[ \t]+bnop \.S1 000001ac <g7>,7
+0+1a8 <[^>]*> 00000122[ \t]+bnop \.S2 000001a0 <f7\+0x20>,0
+[ \t]*1a8: R_C6000_PCR_S12[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+1c8 <[^>]*> 10000012[ \t]+callp \.S2 000001c0 <f8>,b3
+[ \t]*1c8: R_C6000_PCR_S21[ \t]+ext3\+0x4
+0+1cc <[^>]*> 10000010[ \t]+callp \.S1 000001c0 <f8>,a3
+[ \t]*1cc: R_C6000_PCR_S21[ \t]+ext2
+0+1d0 <[^>]*> 10000010[ \t]+callp \.S1 000001c0 <f8>,a3
+[ \t]*1d0: R_C6000_PCR_S21[ \t]+nrp
+0+1d4 <[^>]*> 10000012[ \t]+callp \.S2 000001c0 <f8>,b3
+[ \t]*1d4: R_C6000_PCR_S21[ \t]+irp
+0+1d8 <[^>]*> 10000010[ \t]+callp \.S1 000001c0 <f8>,a3
+[ \t]*1d8: R_C6000_PCR_S21[ \t]+a1
+0+1dc <[^>]*> 10000012[ \t]+callp \.S2 000001c0 <f8>,b3
+0+1e0 <[^>]*> 1ffffc92[ \t]+callp \.S2 000001c4 <f8\+0x4>,b3
+0+1e4 <[^>]*> 10000190[ \t]+callp \.S1 000001ec <g8>,a3
+0+1e8 <[^>]*> 10000012[ \t]+callp \.S2 000001e0 <f8\+0x20>,b3
+[ \t]*1e8: R_C6000_PCR_S21[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+208 <[^>]*> 00000012[ \t]+b \.S2 00000200 <f9>
+[ \t]*208: R_C6000_PCR_S21[ \t]+ext3\+0x4
+0+20c <[^>]*> 00000010[ \t]+b \.S1 00000200 <f9>
+[ \t]*20c: R_C6000_PCR_S21[ \t]+ext2
+0+210 <[^>]*> 00000012[ \t]+b \.S2 00000200 <f9>
+[ \t]*210: R_C6000_PCR_S21[ \t]+nrp
+0+214 <[^>]*> 00000012[ \t]+b \.S2 00000200 <f9>
+[ \t]*214: R_C6000_PCR_S21[ \t]+irp
+0+218 <[^>]*> 00000010[ \t]+b \.S1 00000200 <f9>
+[ \t]*218: R_C6000_PCR_S21[ \t]+a1
+0+21c <[^>]*> 00000012[ \t]+b \.S2 00000200 <f9>
+0+220 <[^>]*> 6ffffc92[ \t]+\[b2\] b \.S2 00000204 <f9\+0x4>
+0+224 <[^>]*> 00000192[ \t]+b \.S2 0000022c <g9>
+0+228 <[^>]*> 00000012[ \t]+b \.S2 00000220 <f9\+0x20>
+[ \t]*228: R_C6000_PCR_S21[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+248 <[^>]*> 00000012[ \t]+b \.S2 00000240 <f10>
+[ \t]*248: R_C6000_PCR_S21[ \t]+ext3\+0x4
+0+24c <[^>]*> 00000010[ \t]+b \.S1 00000240 <f10>
+[ \t]*24c: R_C6000_PCR_S21[ \t]+ext2
+0+250 <[^>]*> 00000012[ \t]+b \.S2 00000240 <f10>
+[ \t]*250: R_C6000_PCR_S21[ \t]+nrp
+0+254 <[^>]*> 00000012[ \t]+b \.S2 00000240 <f10>
+[ \t]*254: R_C6000_PCR_S21[ \t]+irp
+0+258 <[^>]*> 00000010[ \t]+b \.S1 00000240 <f10>
+[ \t]*258: R_C6000_PCR_S21[ \t]+a1
+0+25c <[^>]*> 00000012[ \t]+b \.S2 00000240 <f10>
+0+260 <[^>]*> 6ffffc92[ \t]+\[b2\] b \.S2 00000244 <f10\+0x4>
+0+264 <[^>]*> 00000192[ \t]+b \.S2 0000026c <g10>
+0+268 <[^>]*> 00000012[ \t]+b \.S2 00000260 <f10\+0x20>
+[ \t]*268: R_C6000_PCR_S21[ \t]+b1
+[ \t]*\.\.\.
+[ \t]*\.\.\.
+0+288 <[^>]*> 10000012[ \t]+callp \.S2 00000280 <f11>,b3
+[ \t]*288: R_C6000_PCR_S21[ \t]+ext3\+0x4
+0+28c <[^>]*> 10000010[ \t]+callp \.S1 00000280 <f11>,a3
+[ \t]*28c: R_C6000_PCR_S21[ \t]+ext2
+0+290 <[^>]*> 10000010[ \t]+callp \.S1 00000280 <f11>,a3
+[ \t]*290: R_C6000_PCR_S21[ \t]+nrp
+0+294 <[^>]*> 10000012[ \t]+callp \.S2 00000280 <f11>,b3
+[ \t]*294: R_C6000_PCR_S21[ \t]+irp
+0+298 <[^>]*> 10000010[ \t]+callp \.S1 00000280 <f11>,a3
+[ \t]*298: R_C6000_PCR_S21[ \t]+a1
+0+29c <[^>]*> 10000012[ \t]+callp \.S2 00000280 <f11>,b3
+0+2a0 <[^>]*> 1ffffc92[ \t]+callp \.S2 00000284 <f11\+0x4>,b3
+0+2a4 <[^>]*> 10000190[ \t]+callp \.S1 000002ac <g11>,a3
+0+2a8 <[^>]*> 10000012[ \t]+callp \.S2 000002a0 <f11\+0x20>,b3
+[ \t]*2a8: R_C6000_PCR_S21[ \t]+b1
+[ \t]*\.\.\.
--- /dev/null
+# Test C674x instructions generating PC-relative relocations.
+.text
+.nocmp
+.globl ext1
+.globl ext2
+.globl ext3
+.globl a1
+.globl b1
+.globl irp
+.globl nrp
+f:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ addkpc .S2 f,b1,3
+ [a2] addkpc .S2 f+4,b3,7
+ addkpc .S2 g,b4,0
+ addkpc .S2 ext1+8,b5,4
+g:
+ nop
+ nop
+ nop
+ nop
+ nop
+f2:
+ nop
+ nop
+ b .S2 ext3+4
+ b .S1 ext2
+ b .S2 (nrp)
+ b .S2 (irp)
+ b .S1 (a1)
+ b .S2 f2
+ [b2] b .S2 f2+4
+ b .S2 g2
+ b .S2 (b1)
+g2:
+ nop
+ nop
+ nop
+ nop
+ nop
+f3:
+ nop
+ nop
+ call .S2 ext3+4
+ call .S1 ext2
+ call .S2 (nrp)
+ call .S2 (irp)
+ call .S1 (a1)
+ call .S2 f3
+ [b2] call .S2 f3+4
+ call .S2 g3
+ call .S2 (b1)
+g3:
+ nop
+ nop
+ nop
+ nop
+ nop
+f4:
+ nop
+ nop
+ bdec .S2 ext3+4,b2
+ bdec .S1 ext2,a2
+ bdec .S2 (nrp),b2
+ bdec .S2 (irp),b2
+ bdec .S1 (a1),a2
+ bdec .S2 f4,b2
+ [!a1] bdec .S2 f4+4,b2
+ bdec .S2 g4,b2
+ bdec .S2 (b1),b2
+g4:
+ nop
+ nop
+ nop
+ nop
+ nop
+f5:
+ nop
+ nop
+ bpos .S2 ext3+4,b2
+ bpos .S1 ext2,a2
+ bpos .S2 (nrp),b2
+ bpos .S2 (irp),b2
+ bpos .S1 (a1),a2
+ bpos .S2 f5,b2
+ [!b1] bpos .S2 f5+4,b2
+ bpos .S2 g5,b2
+ bpos .S2 (b1),b2
+g5:
+ nop
+ nop
+ nop
+ nop
+ nop
+f6:
+ nop
+ nop
+ bnop .S2 ext3+4,0
+ bnop .S1 ext2,1
+ bnop (nrp),2
+ bnop .S2 (irp),3
+ bnop .S1 (a1),4
+ bnop .S2 f6,5
+ [!b1] bnop .S2 f6+4,6
+ bnop g6,7
+ bnop .S2 (b1),0
+g6:
+ nop
+ nop
+ nop
+ nop
+ nop
+f7:
+ nop
+ nop
+ callnop .S2 ext3+4,0
+ callnop .S1 ext2,1
+ callnop (nrp),2
+ callnop .S2 (irp),3
+ callnop .S1 (a1),4
+ callnop .S2 f7,5
+ [a0] callnop .S2 f7+4,6
+ callnop g7,7
+ callnop .S2 (b1),0
+g7:
+ nop
+ nop
+ nop
+ nop
+ nop
+f8:
+ nop
+ nop
+ callp .S2 ext3+4,b3
+ callp .S1 ext2,a3
+ callp .S1 (nrp),a3
+ callp .S2 (irp),b3
+ callp .S1 (a1),a3
+ callp .S2 f8,b3
+ callp .S2 f8+4,b3
+ callp .S1 g8,a3
+ callp .S2 (b1),b3
+g8:
+ nop
+ nop
+ nop
+ nop
+ nop
+f9:
+ nop
+ nop
+ callret .S2 ext3+4
+ callret .S1 ext2
+ callret .S2 (nrp)
+ callret .S2 (irp)
+ callret .S1 (a1)
+ callret .S2 f9
+ [b2] callret .S2 f9+4
+ callret .S2 g9
+ callret .S2 (b1)
+g9:
+ nop
+ nop
+ nop
+ nop
+ nop
+f10:
+ nop
+ nop
+ ret .S2 ext3+4
+ ret .S1 ext2
+ ret .S2 (nrp)
+ ret .S2 (irp)
+ ret .S1 (a1)
+ ret .S2 f10
+ [b2] ret .S2 f10+4
+ ret .S2 g10
+ ret .S2 (b1)
+g10:
+ nop
+ nop
+ nop
+ nop
+ nop
+f11:
+ nop
+ nop
+ retp .S2 ext3+4,b3
+ retp .S1 ext2,a3
+ retp .S1 (nrp),a3
+ retp .S2 (irp),b3
+ retp .S1 (a1),a3
+ retp .S2 f11,b3
+ retp .S2 f11+4,b3
+ retp .S1 g11,a3
+ retp .S2 (b1),b3
+g11:
+ nop
+ nop
+ nop
+ nop
+ nop
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C674x instructions generating relocations
+#as: -march=c674x -mlittle-endian
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+0+00 <[^>]*> 1280003c[ \t]+addab \.D1X b14,0,a5
+[ \t]*0: R_C6000_SBR_U15_B[ \t]+ext1
+0+04 <[^>]*> 138000be[ \t]+addab \.D2 b15,0,b7
+[ \t]*4: R_C6000_SBR_U15_B[ \t]+ext2\+0x7
+0+08 <[^>]*> 1a00003c[ \t]+addab \.D1X b14,0,a20
+[ \t]*8: R_C6000_SBR_U15_B[ \t]+a1
+0+0c <[^>]*> 1f00003e[ \t]+addab \.D2 b14,0,b30
+[ \t]*c: R_C6000_SBR_U15_B[ \t]+b1
+0+10 <[^>]*> 1780043c[ \t]+addab \.D1X b14,4,a15
+0+14 <[^>]*> 1800043e[ \t]+addab \.D2 b14,4,b16
+0+18 <[^>]*> 1280005c[ \t]+addah \.D1X b14,0,a5
+[ \t]*18: R_C6000_SBR_U15_H[ \t]+ext1
+0+1c <[^>]*> 138000de[ \t]+addah \.D2 b15,0,b7
+[ \t]*1c: R_C6000_SBR_U15_H[ \t]+ext2\+0x6
+0+20 <[^>]*> 1a00005c[ \t]+addah \.D1X b14,0,a20
+[ \t]*20: R_C6000_SBR_U15_H[ \t]+a1
+0+24 <[^>]*> 1f00005e[ \t]+addah \.D2 b14,0,b30
+[ \t]*24: R_C6000_SBR_U15_H[ \t]+b1
+0+28 <[^>]*> 1780045c[ \t]+addah \.D1X b14,4,a15
+0+2c <[^>]*> 1800045e[ \t]+addah \.D2 b14,4,b16
+0+30 <[^>]*> 1280007c[ \t]+addaw \.D1X b14,0,a5
+[ \t]*30: R_C6000_SBR_U15_W[ \t]+ext1
+0+34 <[^>]*> 138000fe[ \t]+addaw \.D2 b15,0,b7
+[ \t]*34: R_C6000_SBR_U15_W[ \t]+ext2\+0x8
+0+38 <[^>]*> 1a00007c[ \t]+addaw \.D1X b14,0,a20
+[ \t]*38: R_C6000_SBR_U15_W[ \t]+a1
+0+3c <[^>]*> 1f00007e[ \t]+addaw \.D2 b14,0,b30
+[ \t]*3c: R_C6000_SBR_U15_W[ \t]+b1
+0+40 <[^>]*> 1780047c[ \t]+addaw \.D1X b14,4,a15
+0+44 <[^>]*> 1800047e[ \t]+addaw \.D2 b14,4,b16
+0+48 <[^>]*> 1280007c[ \t]+addaw \.D1X b14,0,a5
+[ \t]*48: R_C6000_DSBT_INDEX[ \t]+__c6xabi_DSBT_BASE
+0+4c <[^>]*> 138000fe[ \t]+addaw \.D2 b15,0,b7
+[ \t]*4c: R_C6000_SBR_GOT_U15_W[ \t]+ext2\+0x8
+0+50 <[^>]*> 00800050[ \t]+addk \.S1 0,a1
+[ \t]*50: R_C6000_ABS_S16[ \t]+ext1\+0x3
+0+54 <[^>]*> 01800052[ \t]+addk \.S2 0,b3
+[ \t]*54: R_C6000_SBR_S16[ \t]+ext2\+0x5
+0+58 <[^>]*> 02000250[ \t]+addk \.S1 4,a4
+0+5c <[^>]*> 02fffe52[ \t]+addk \.S2 -4,b5
+0+60 <[^>]*> 00800028[ \t]+mvk \.S1 0,a1
+[ \t]*60: R_C6000_ABS_S16[ \t]+ext1\+0x3
+0+64 <[^>]*> 0180002a[ \t]+mvk \.S2 0,b3
+[ \t]*64: R_C6000_SBR_S16[ \t]+ext2\+0x5
+0+68 <[^>]*> 02000228[ \t]+mvk \.S1 4,a4
+0+6c <[^>]*> 02fffe2a[ \t]+mvk \.S2 -4,b5
+0+70 <[^>]*> 00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*70: R_C6000_ABS_H16[ \t]+ext3\+0x1
+0+74 <[^>]*> 0100006a[ \t]+mvkh \.S2 0,b2
+[ \t]*74: R_C6000_SBR_GOT_H16_W[ \t]+ext2\+0x2
+0+78 <[^>]*> 01800068[ \t]+mvkh \.S1 0,a3
+[ \t]*78: R_C6000_SBR_H16_B[ \t]+ext1\+0x3
+0+7c <[^>]*> 0200006a[ \t]+mvkh \.S2 0,b4
+[ \t]*7c: R_C6000_SBR_H16_H[ \t]+ext3\+0x4
+0+80 <[^>]*> 02800068[ \t]+mvkh \.S1 0,a5
+[ \t]*80: R_C6000_SBR_H16_W[ \t]+ext2\+0x5
+0+84 <[^>]*> 0300016a[ \t]+mvkh \.S2 131072,b6
+0+88 <[^>]*> 00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*88: R_C6000_ABS_L16[ \t]+ext3\+0x1
+0+8c <[^>]*> 0100006a[ \t]+mvkh \.S2 0,b2
+[ \t]*8c: R_C6000_SBR_GOT_L16_W[ \t]+ext2\+0x2
+0+90 <[^>]*> 01800068[ \t]+mvkh \.S1 0,a3
+[ \t]*90: R_C6000_SBR_L16_B[ \t]+ext1\+0x3
+0+94 <[^>]*> 0200006a[ \t]+mvkh \.S2 0,b4
+[ \t]*94: R_C6000_SBR_L16_H[ \t]+ext3\+0x4
+0+98 <[^>]*> 02800068[ \t]+mvkh \.S1 0,a5
+[ \t]*98: R_C6000_SBR_L16_W[ \t]+ext2\+0x5
+0+9c <[^>]*> 030000ea[ \t]+mvkh \.S2 65536,b6
+0+a0 <[^>]*> 00800028[ \t]+mvk \.S1 0,a1
+[ \t]*a0: R_C6000_ABS_L16[ \t]+ext3\+0x1
+0+a4 <[^>]*> 0100002a[ \t]+mvk \.S2 0,b2
+[ \t]*a4: R_C6000_SBR_GOT_L16_W[ \t]+ext2\+0x2
+0+a8 <[^>]*> 01800028[ \t]+mvk \.S1 0,a3
+[ \t]*a8: R_C6000_SBR_L16_B[ \t]+ext1\+0x3
+0+ac <[^>]*> 0200002a[ \t]+mvk \.S2 0,b4
+[ \t]*ac: R_C6000_SBR_L16_H[ \t]+ext3\+0x4
+0+b0 <[^>]*> 02800028[ \t]+mvk \.S1 0,a5
+[ \t]*b0: R_C6000_SBR_L16_W[ \t]+ext2\+0x5
+0+b4 <[^>]*> 030000aa[ \t]+mvk \.S2 1,b6
+0+b8 <[^>]*> 0080002e[ \t]+ldb \.D2T2 \*\+b14\(0\),b1
+[ \t]*b8: R_C6000_SBR_U15_B[ \t]+ext1
+0+bc <[^>]*> 008000ac[ \t]+ldb \.D2T1 \*\+b15\(0\),a1
+[ \t]*bc: R_C6000_SBR_U15_B[ \t]+ext2\+0x7
+0+c0 <[^>]*> 008000ae[ \t]+ldb \.D2T2 \*\+b15\(0\),b1
+[ \t]*c0: R_C6000_SBR_U15_B[ \t]+b1
+0+c4 <[^>]*> 0080002c[ \t]+ldb \.D2T1 \*\+b14\(0\),a1
+[ \t]*c4: R_C6000_SBR_U15_B[ \t]+a1
+0+c8 <[^>]*> 00b882a6[ \t]+ldb \.D2T2 \*\+b14\(4\),b1
+0+cc <[^>]*> 0080042c[ \t]+ldb \.D2T1 \*\+b14\(4\),a1
+0+d0 <[^>]*> 0080001e[ \t]+ldbu \.D2T2 \*\+b14\(0\),b1
+[ \t]*d0: R_C6000_SBR_U15_B[ \t]+ext1
+0+d4 <[^>]*> 0080009c[ \t]+ldbu \.D2T1 \*\+b15\(0\),a1
+[ \t]*d4: R_C6000_SBR_U15_B[ \t]+ext2\+0x7
+0+d8 <[^>]*> 0080009e[ \t]+ldbu \.D2T2 \*\+b15\(0\),b1
+[ \t]*d8: R_C6000_SBR_U15_B[ \t]+b1
+0+dc <[^>]*> 0080001c[ \t]+ldbu \.D2T1 \*\+b14\(0\),a1
+[ \t]*dc: R_C6000_SBR_U15_B[ \t]+a1
+0+e0 <[^>]*> 00b88296[ \t]+ldbu \.D2T2 \*\+b14\(4\),b1
+0+e4 <[^>]*> 0080041c[ \t]+ldbu \.D2T1 \*\+b14\(4\),a1
+0+e8 <[^>]*> 0080004e[ \t]+ldh \.D2T2 \*\+b14\(0\),b1
+[ \t]*e8: R_C6000_SBR_U15_H[ \t]+ext1
+0+ec <[^>]*> 008000cc[ \t]+ldh \.D2T1 \*\+b15\(0\),a1
+[ \t]*ec: R_C6000_SBR_U15_H[ \t]+ext2\+0x6
+0+f0 <[^>]*> 008000ce[ \t]+ldh \.D2T2 \*\+b15\(0\),b1
+[ \t]*f0: R_C6000_SBR_U15_H[ \t]+b1
+0+f4 <[^>]*> 0080004c[ \t]+ldh \.D2T1 \*\+b14\(0\),a1
+[ \t]*f4: R_C6000_SBR_U15_H[ \t]+a1
+0+f8 <[^>]*> 00b842c6[ \t]+ldh \.D2T2 \*\+b14\(4\),b1
+0+fc <[^>]*> 0080024c[ \t]+ldh \.D2T1 \*\+b14\(4\),a1
+0+100 <[^>]*> 0080000e[ \t]+ldhu \.D2T2 \*\+b14\(0\),b1
+[ \t]*100: R_C6000_SBR_U15_H[ \t]+ext1
+0+104 <[^>]*> 0080008c[ \t]+ldhu \.D2T1 \*\+b15\(0\),a1
+[ \t]*104: R_C6000_SBR_U15_H[ \t]+ext2\+0x6
+0+108 <[^>]*> 0080008e[ \t]+ldhu \.D2T2 \*\+b15\(0\),b1
+[ \t]*108: R_C6000_SBR_U15_H[ \t]+b1
+0+10c <[^>]*> 0080000c[ \t]+ldhu \.D2T1 \*\+b14\(0\),a1
+[ \t]*10c: R_C6000_SBR_U15_H[ \t]+a1
+0+110 <[^>]*> 00b84286[ \t]+ldhu \.D2T2 \*\+b14\(4\),b1
+0+114 <[^>]*> 0080020c[ \t]+ldhu \.D2T1 \*\+b14\(4\),a1
+0+118 <[^>]*> 0080006e[ \t]+ldw \.D2T2 \*\+b14\(0\),b1
+[ \t]*118: R_C6000_SBR_U15_W[ \t]+ext1
+0+11c <[^>]*> 008000ec[ \t]+ldw \.D2T1 \*\+b15\(0\),a1
+[ \t]*11c: R_C6000_SBR_U15_W[ \t]+ext2\+0x4
+0+120 <[^>]*> 008000ee[ \t]+ldw \.D2T2 \*\+b15\(0\),b1
+[ \t]*120: R_C6000_SBR_U15_W[ \t]+b1
+0+124 <[^>]*> 0080006c[ \t]+ldw \.D2T1 \*\+b14\(0\),a1
+[ \t]*124: R_C6000_SBR_U15_W[ \t]+a1
+0+128 <[^>]*> 00b822e6[ \t]+ldw \.D2T2 \*\+b14\(4\),b1
+0+12c <[^>]*> 0080016c[ \t]+ldw \.D2T1 \*\+b14\(4\),a1
+0+130 <[^>]*> 0080006e[ \t]+ldw \.D2T2 \*\+b14\(0\),b1
+[ \t]*130: R_C6000_DSBT_INDEX[ \t]+__c6xabi_DSBT_BASE
+0+134 <[^>]*> 0080006c[ \t]+ldw \.D2T1 \*\+b14\(0\),a1
+[ \t]*134: R_C6000_SBR_GOT_U15_W[ \t]+ext2\+0x4
+0+138 <[^>]*> 0080003e[ \t]+stb \.D2T2 b1,\*\+b14\(0\)
+[ \t]*138: R_C6000_SBR_U15_B[ \t]+ext1
+0+13c <[^>]*> 008000bc[ \t]+stb \.D2T1 a1,\*\+b15\(0\)
+[ \t]*13c: R_C6000_SBR_U15_B[ \t]+ext2\+0x7
+0+140 <[^>]*> 008000be[ \t]+stb \.D2T2 b1,\*\+b15\(0\)
+[ \t]*140: R_C6000_SBR_U15_B[ \t]+b1
+0+144 <[^>]*> 0080003c[ \t]+stb \.D2T1 a1,\*\+b14\(0\)
+[ \t]*144: R_C6000_SBR_U15_B[ \t]+a1
+0+148 <[^>]*> 00b882b6[ \t]+stb \.D2T2 b1,\*\+b14\(4\)
+0+14c <[^>]*> 0080043c[ \t]+stb \.D2T1 a1,\*\+b14\(4\)
+0+150 <[^>]*> 0080005e[ \t]+sth \.D2T2 b1,\*\+b14\(0\)
+[ \t]*150: R_C6000_SBR_U15_H[ \t]+ext1
+0+154 <[^>]*> 008000dc[ \t]+sth \.D2T1 a1,\*\+b15\(0\)
+[ \t]*154: R_C6000_SBR_U15_H[ \t]+ext2\+0x6
+0+158 <[^>]*> 008000de[ \t]+sth \.D2T2 b1,\*\+b15\(0\)
+[ \t]*158: R_C6000_SBR_U15_H[ \t]+b1
+0+15c <[^>]*> 0080005c[ \t]+sth \.D2T1 a1,\*\+b14\(0\)
+[ \t]*15c: R_C6000_SBR_U15_H[ \t]+a1
+0+160 <[^>]*> 00b842d6[ \t]+sth \.D2T2 b1,\*\+b14\(4\)
+0+164 <[^>]*> 0080025c[ \t]+sth \.D2T1 a1,\*\+b14\(4\)
+0+168 <[^>]*> 0080007e[ \t]+stw \.D2T2 b1,\*\+b14\(0\)
+[ \t]*168: R_C6000_SBR_U15_W[ \t]+ext1
+0+16c <[^>]*> 008000fc[ \t]+stw \.D2T1 a1,\*\+b15\(0\)
+[ \t]*16c: R_C6000_SBR_U15_W[ \t]+ext2\+0x4
+0+170 <[^>]*> 008000fe[ \t]+stw \.D2T2 b1,\*\+b15\(0\)
+[ \t]*170: R_C6000_SBR_U15_W[ \t]+b1
+0+174 <[^>]*> 0080007c[ \t]+stw \.D2T1 a1,\*\+b14\(0\)
+[ \t]*174: R_C6000_SBR_U15_W[ \t]+a1
+0+178 <[^>]*> 00b822f6[ \t]+stw \.D2T2 b1,\*\+b14\(4\)
+0+17c <[^>]*> 0080017c[ \t]+stw \.D2T1 a1,\*\+b14\(4\)
+0+180 <[^>]*> 0080007e[ \t]+stw \.D2T2 b1,\*\+b14\(0\)
+[ \t]*180: R_C6000_DSBT_INDEX[ \t]+__c6xabi_DSBT_BASE
+0+184 <[^>]*> 0080007c[ \t]+stw \.D2T1 a1,\*\+b14\(0\)
+[ \t]*184: R_C6000_SBR_GOT_U15_W[ \t]+ext2\+0x4
+[ \t]*\.\.\.
--- /dev/null
+# Test C674x instructions generating relocations.
+.data
+w1:
+ .word 1
+w2:
+ .word 2
+.text
+.nocmp
+.globl ext1
+.globl ext2
+.globl ext3
+.globl a1
+.globl b1
+.globl f
+f:
+ addab .D1X b14,ext1,a5
+ addab .D2 b15,(ext2+7),b7
+ addab .D1X b14,(a1),a20
+ addab .D2 b14,(b1),b30
+ addab .D1X b14,w2-w1,a15
+ addab .D2 b14,w4-w3,b16
+ addah .D1X b14,ext1,a5
+ addah .D2 b15,(ext2+6),b7
+ addah .D1X b14,(a1),a20
+ addah .D2 b14,(b1),b30
+ addah .D1X b14,w2-w1,a15
+ addah .D2 b14,w4-w3,b16
+ addaw .D1X b14,ext1,a5
+ addaw .D2 b15,(ext2+8),b7
+ addaw .D1X b14,(a1),a20
+ addaw .D2 b14,(b1),b30
+ addaw .D1X b14,w2-w1,a15
+ addaw .D2 b14,w4-w3,b16
+ addaw .D1X b14,$DSBT_INDEX(__c6xabi_DSBT_BASE),a5
+ addaw .D2 b15,$GOT(ext2)+8,b7
+ addk .S1 ext1+3,a1
+ addk .S2 $dpr_byte(ext2)+5,b3
+ addk .S1 w2-w1,a4
+ addk .S2 w3-w4,b5
+ mvk .S1 ext1+3,a1
+ mvk .S2 $dpr_byte(ext2)+5,b3
+ mvk .S1 w2-w1,a4
+ mvk .S2 w3-w4,b5
+ mvkh .S1 ext3+1,a1
+ mvkh .S2 $DPR_GOT(ext2)+2,b2
+ mvkh .S1 $DPR_BYTE(ext1)+3,a3
+ mvkh .S2 $DPR_HWORD(ext3)+4,b4
+ mvkh .S1 $DPR_WORD(ext2)+5,a5
+ mvkh .S2 s1-s0,b6
+ mvklh .S1 ext3+1,a1
+ mvklh .S2 $DPR_GOT(ext2)+2,b2
+ mvklh .S1 $DPR_BYTE(ext1)+3,a3
+ mvklh .S2 $DPR_HWORD(ext3)+4,b4
+ mvklh .S1 $DPR_WORD(ext2)+5,a5
+ mvklh .S2 s1-s0,b6
+ mvkl .S1 ext3+1,a1
+ mvkl .S2 $DPR_GOT(ext2)+2,b2
+ mvkl .S1 $DPR_BYTE(ext1)+3,a3
+ mvkl .S2 $DPR_HWORD(ext3)+4,b4
+ mvkl .S1 $DPR_WORD(ext2)+5,a5
+ mvkl .S2 s1-s0,b6
+ ldb .D2T2 *+b14(ext1),b1
+ ldb .D2T1 *+b15(ext2+7),a1
+ ldb .D2T2 *+b15(b1),b1
+ ldb .D2T1 *+b14(a1),a1
+ ldb .D2T2 *+b14(w2-w1),b1
+ ldb .D2T1 *+b14(w4-w3),a1
+ ldbu .D2T2 *+b14(ext1),b1
+ ldbu .D2T1 *+b15(ext2+7),a1
+ ldbu .D2T2 *+b15(b1),b1
+ ldbu .D2T1 *+b14(a1),a1
+ ldbu .D2T2 *+b14(w2-w1),b1
+ ldbu .D2T1 *+b14(w4-w3),a1
+ ldh .D2T2 *+b14(ext1),b1
+ ldh .D2T1 *+b15(ext2+6),a1
+ ldh .D2T2 *+b15(b1),b1
+ ldh .D2T1 *+b14(a1),a1
+ ldh .D2T2 *+b14(w2-w1),b1
+ ldh .D2T1 *+b14(w4-w3),a1
+ ldhu .D2T2 *+b14(ext1),b1
+ ldhu .D2T1 *+b15(ext2+6),a1
+ ldhu .D2T2 *+b15(b1),b1
+ ldhu .D2T1 *+b14(a1),a1
+ ldhu .D2T2 *+b14(w2-w1),b1
+ ldhu .D2T1 *+b14(w4-w3),a1
+ ldw .D2T2 *+b14(ext1),b1
+ ldw .D2T1 *+b15(ext2+4),a1
+ ldw .D2T2 *+b15(b1),b1
+ ldw .D2T1 *+b14(a1),a1
+ ldw .D2T2 *+b14(w2-w1),b1
+ ldw .D2T1 *+b14(w4-w3),a1
+ ldw .D2T2 *+b14($DSBT_INDEX(__c6xabi_DSBT_BASE)),b1
+ ldw .D2T1 *+b14($GOT(ext2)+4),a1
+ stb .D2T2 b1,*+b14(ext1)
+ stb .D2T1 a1,*+b15(ext2+7)
+ stb .D2T2 b1,*+b15(b1)
+ stb .D2T1 a1,*+b14(a1)
+ stb .D2T2 b1,*+b14(w2-w1)
+ stb .D2T1 a1,*+b14(w4-w3)
+ sth .D2T2 b1,*+b14(ext1)
+ sth .D2T1 a1,*+b15(ext2+6)
+ sth .D2T2 b1,*+b15(b1)
+ sth .D2T1 a1,*+b14(a1)
+ sth .D2T2 b1,*+b14(w2-w1)
+ sth .D2T1 a1,*+b14(w4-w3)
+ stw .D2T2 b1,*+b14(ext1)
+ stw .D2T1 a1,*+b15(ext2+4)
+ stw .D2T2 b1,*+b15(b1)
+ stw .D2T1 a1,*+b14(a1)
+ stw .D2T2 b1,*+b14(w2-w1)
+ stw .D2T1 a1,*+b14(w4-w3)
+ stw .D2T2 b1,*+b14($DSBT_INDEX(__c6xabi_DSBT_BASE))
+ stw .D2T1 a1,*+b14($GOT(ext2)+4)
+.data
+w3:
+ .word 3
+w4:
+ .word 4
+s0:
+ .space 131073
+s1:
+ .word 5
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C674x SPLOOP instructions
+#as: -march=c674x -mlittle-endian
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+[0-9a-f]+[048c] <[^>]*> 00030000[ \t]+spmask
+[0-9a-f]+[048c] <[^>]*> 00070000[ \t]+spmask L1
+[0-9a-f]+[048c] <[^>]*> 000b0000[ \t]+spmask L2
+[0-9a-f]+[048c] <[^>]*> 00130000[ \t]+spmask S1
+[0-9a-f]+[048c] <[^>]*> 00230000[ \t]+spmask S2
+[0-9a-f]+[048c] <[^>]*> 00430000[ \t]+spmask D1
+[0-9a-f]+[048c] <[^>]*> 00830000[ \t]+spmask D2
+[0-9a-f]+[048c] <[^>]*> 01030000[ \t]+spmask M1
+[0-9a-f]+[048c] <[^>]*> 02030000[ \t]+spmask M2
+[0-9a-f]+[048c] <[^>]*> 00470000[ \t]+spmask L1,D1
+[0-9a-f]+[048c] <[^>]*> 00470000[ \t]+spmask L1,D1
+[0-9a-f]+[048c] <[^>]*> 03ff0000[ \t]+spmask L1,L2,S1,S2,D1,D2,M1,M2
+[0-9a-f]+[048c] <[^>]*> 01170001[ \t]+spmask L1,S1,M1
+[0-9a-f]+[048c] <[^>]*> 00800fd9[ \t]+\|\| or \.L1 0,a0,a1
+[0-9a-f]+[048c] <[^>]*> 008008f3[ \t]+\|\| or \.D2 0,b0,b1
+[0-9a-f]+[048c] <[^>]*> 018806a0[ \t]+\|\| or \.S1 0,a2,a3
+[0-9a-f]+[048c] <[^>]*> 00032000[ \t]+spmaskr
+[0-9a-f]+[048c] <[^>]*> 00072000[ \t]+spmaskr L1
+[0-9a-f]+[048c] <[^>]*> 000b2000[ \t]+spmaskr L2
+[0-9a-f]+[048c] <[^>]*> 00132000[ \t]+spmaskr S1
+[0-9a-f]+[048c] <[^>]*> 00232000[ \t]+spmaskr S2
+[0-9a-f]+[048c] <[^>]*> 00432000[ \t]+spmaskr D1
+[0-9a-f]+[048c] <[^>]*> 00832000[ \t]+spmaskr D2
+[0-9a-f]+[048c] <[^>]*> 01032000[ \t]+spmaskr M1
+[0-9a-f]+[048c] <[^>]*> 02032000[ \t]+spmaskr M2
+[0-9a-f]+[048c] <[^>]*> 00472000[ \t]+spmaskr L1,D1
+[0-9a-f]+[048c] <[^>]*> 00472000[ \t]+spmaskr L1,D1
+[0-9a-f]+[048c] <[^>]*> 03ff2000[ \t]+spmaskr L1,L2,S1,S2,D1,D2,M1,M2
+[0-9a-f]+[048c] <[^>]*> 01172001[ \t]+spmaskr L1,S1,M1
+[0-9a-f]+[048c] <[^>]*> 00800fd9[ \t]+\|\| or \.L1 0,a0,a1
+[0-9a-f]+[048c] <[^>]*> 008008f3[ \t]+\|\| or \.D2 0,b0,b1
+[0-9a-f]+[048c] <[^>]*> 018806a0[ \t]+\|\| or \.S1 0,a2,a3
+[0-9a-f]+[048c] <[^>]*> c0038000[ \t]+\[a0\] sploop 1
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 00036000[ \t]+spkernelr
+[0-9a-f]+[048c] <[^>]*> 2003a000[ \t]+\[b0\] sploopd 1
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 00034000[ \t]+spkernel 0,0
+[0-9a-f]+[048c] <[^>]*> d003e000[ \t]+\[!a0\] sploopw 1
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 00034000[ \t]+spkernel 0,0
+[0-9a-f]+[048c] <[^>]*> 00038000[ \t]+sploop 1
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 00034000[ \t]+spkernel 0,0
+[0-9a-f]+[048c] <[^>]*> 00038000[ \t]+sploop 1
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0fc34000[ \t]+spkernel 63,0
+[0-9a-f]+[048c] <[^>]*> 00838000[ \t]+sploop 2
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0f834000[ \t]+spkernel 31,0
+[0-9a-f]+[048c] <[^>]*> 00838000[ \t]+sploop 2
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0fc34000[ \t]+spkernel 31,1
+[0-9a-f]+[048c] <[^>]*> 01038000[ \t]+sploop 3
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0f834000[ \t]+spkernel 15,2
+[0-9a-f]+[048c] <[^>]*> 01838000[ \t]+sploop 4
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0fc34000[ \t]+spkernel 15,3
+[0-9a-f]+[048c] <[^>]*> 02038000[ \t]+sploop 5
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0f034000[ \t]+spkernel 7,4
+[0-9a-f]+[048c] <[^>]*> 03838000[ \t]+sploop 8
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0fc34000[ \t]+spkernel 7,7
+[0-9a-f]+[048c] <[^>]*> 04038000[ \t]+sploop 9
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0e034000[ \t]+spkernel 3,8
+[0-9a-f]+[048c] <[^>]*> 06838000[ \t]+sploop 14
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 0f434000[ \t]+spkernel 3,13
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
--- /dev/null
+# Test C674x SPLOOP instructions. The present tests are placeholders
+# to verify encoding that may not be valid when the full set of checks
+# for invalid input are implemented and may need changing to valid
+# code at that point.
+.text
+.nocmp
+.globl f
+f:
+ spmask
+ spmask l1
+ spmask L2
+ spmask s1
+ spmask S2
+ spmask D1
+ spmask d2
+ spmask M1
+ spmask m2
+ spmask D1,L1
+ spmask L1,D1
+ spmask L1,S1,D1,M1,M2,D2,S2,L2
+ spmask M1
+||^ mv .L1 a0,a1
+|| mv .D2 b0,b1
+||^ mv .S1 a2,a3
+ spmaskr
+ spmaskr l1
+ spmaskr L2
+ spmaskr s1
+ spmaskr S2
+ spmaskr D1
+ spmaskr d2
+ spmaskr M1
+ spmaskr m2
+ spmaskr D1,L1
+ spmaskr L1,D1
+ spmaskr L1,S1,D1,M1,M2,D2,S2,L2
+ spmaskr M1
+||^ mv .L1 a0,a1
+|| mv .D2 b0,b1
+||^ mv .S1 a2,a3
+ [a0] sploop 1
+ nop
+ spkernelr
+ [b0] sploopd 1
+ nop
+ spkernel
+ [!a0] sploopw 1
+ nop
+ spkernel
+ sploop 1
+ nop
+ spkernel 0,0
+ sploop 1
+ nop
+ spkernel 63,0
+ sploop 2
+ nop
+ spkernel 31,0
+ sploop 2
+ nop
+ spkernel 31,1
+ sploop 3
+ nop
+ spkernel 15,2
+ sploop 4
+ nop
+ spkernel 15,3
+ sploop 5
+ nop
+ spkernel 7,4
+ sploop 8
+ nop
+ spkernel 7,7
+ sploop 9
+ nop
+ spkernel 3,8
+ sploop 14
+ nop
+ spkernel 3,13
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C674x instructions
+#as: -march=c674x -mlittle-endian
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+[0-9a-f]+[048c] <[^>]*> 03940358[ \t]+abs \.L1 a5,a7
+[0-9a-f]+[048c] <[^>]*> 072c1358[ \t]+abs \.L1X b11,a14
+[0-9a-f]+[048c] <[^>]*> 89c0035a[ \t]+\[a1\] abs \.L2 b16,b19
+[0-9a-f]+[048c] <[^>]*> 7f9c135a[ \t]+\[!b2\] abs \.L2X a7,b31
+[0-9a-f]+[048c] <[^>]*> 49280718[ \t]+\[b1\] abs \.L1 a11:a10,a19:a18
+[0-9a-f]+[048c] <[^>]*> 0030071a[ \t]+abs \.L2 b13:b12,b1:b0
+[0-9a-f]+[048c] <[^>]*> 05248358[ \t]+abs2 \.L1 a9,a10
+[0-9a-f]+[048c] <[^>]*> a2dc9358[ \t]+\[a2\] abs2 \.L1X b23,a5
+[0-9a-f]+[048c] <[^>]*> 070c835a[ \t]+abs2 \.L2 b3,b14
+[0-9a-f]+[048c] <[^>]*> 0cf0935a[ \t]+abs2 \.L2X a28,b25
+[0-9a-f]+[048c] <[^>]*> 0c180b20[ \t]+absdp \.S1 a7:a6,a25:a24
+[0-9a-f]+[048c] <[^>]*> c2080b22[ \t]+\[a0\] absdp \.S2 b3:b2,b5:b4
+[0-9a-f]+[048c] <[^>]*> 04240f20[ \t]+abssp \.S1 a9,a8
+[0-9a-f]+[048c] <[^>]*> 08481f20[ \t]+abssp \.S1X b18,a16
+[0-9a-f]+[048c] <[^>]*> 23800f22[ \t]+\[b0\] abssp \.S2 b0,b7
+[0-9a-f]+[048c] <[^>]*> 9d041f22[ \t]+\[!a1\] abssp \.S2X a1,b26
+[0-9a-f]+[048c] <[^>]*> 0a28a078[ \t]+add \.L1 a5,a10,a20
+[0-9a-f]+[048c] <[^>]*> b22c7078[ \t]+\[!a2\] add \.L1X a3,b11,a4
+[0-9a-f]+[048c] <[^>]*> 53a1207a[ \t]+\[!b1\] add \.L2 b9,b8,b7
+[0-9a-f]+[048c] <[^>]*> 0553d07a[ \t]+add \.L2X b30,a20,b10
+[0-9a-f]+[048c] <[^>]*> 0a2d4478[ \t]+add \.L1 a10,a11,a21:a20
+[0-9a-f]+[048c] <[^>]*> 0769b478[ \t]+add \.L1X a13,b26,a15:a14
+[0-9a-f]+[048c] <[^>]*> dd73a47a[ \t]+\[!a0\] add \.L2 b29,b28,b27:b26
+[0-9a-f]+[048c] <[^>]*> 0b63347a[ \t]+add \.L2X b25,a24,b23:b22
+[0-9a-f]+[048c] <[^>]*> 32082438[ \t]+\[!b0\] add \.L1 a1,a3:a2,a5:a4
+[0-9a-f]+[048c] <[^>]*> 07429438[ \t]+add \.L1X b20,a17:a16,a15:a14
+[0-9a-f]+[048c] <[^>]*> 0a5b043a[ \t]+add \.L2 b24,b23:b22,b21:b20
+[0-9a-f]+[048c] <[^>]*> 6740d43a[ \t]+\[b2\] add \.L2X a6,b17:b16,b15:b14
+[0-9a-f]+[048c] <[^>]*> 03160058[ \t]+add \.L1 -16,a5,a6
+[0-9a-f]+[048c] <[^>]*> cf2df058[ \t]+\[a0\] add \.L1X 15,b11,a30
+[0-9a-f]+[048c] <[^>]*> 0526a05a[ \t]+add \.L2 -11,b9,b10
+[0-9a-f]+[048c] <[^>]*> 0395d05a[ \t]+add \.L2X 14,a5,b7
+[0-9a-f]+[048c] <[^>]*> 0308a418[ \t]+add \.L1 5,a3:a2,a7:a6
+[0-9a-f]+[048c] <[^>]*> 2e73241a[ \t]+\[b0\] add \.L2 -7,b29:b28,b29:b28
+[0-9a-f]+[048c] <[^>]*> d6b161e0[ \t]+\[!a0\] add \.S1 a11,a12,a13
+[0-9a-f]+[048c] <[^>]*> 083dd1e0[ \t]+add \.S1X a14,b15,a16
+[0-9a-f]+[048c] <[^>]*> 09ca21e2[ \t]+add \.S2 b17,b18,b19
+[0-9a-f]+[048c] <[^>]*> 0cfa91e2[ \t]+add \.S2X b20,a30,b25
+[0-9a-f]+[048c] <[^>]*> 059201a0[ \t]+add \.S1 -16,a4,a11
+[0-9a-f]+[048c] <[^>]*> 0ba5b1a0[ \t]+add \.S1X 13,b9,a23
+[0-9a-f]+[048c] <[^>]*> 35e5e1a2[ \t]+\[!b0\] add \.S2 15,b25,b11
+[0-9a-f]+[048c] <[^>]*> 010791a2[ \t]+add \.S2X -4,a1,b2
+[0-9a-f]+[048c] <[^>]*> 01152840[ \t]+add \.D1 a5,a9,a2
+[0-9a-f]+[048c] <[^>]*> 89422842[ \t]+\[a1\] add \.D2 b16,b17,b18
+[0-9a-f]+[048c] <[^>]*> 4317e940[ \t]+\[b1\] add \.D1 a5,31,a6
+[0-9a-f]+[048c] <[^>]*> 0ad80942[ \t]+add \.D2 b22,0,b21
+[0-9a-f]+[048c] <[^>]*> 01042840[ \t]+add \.D1 a1,a1,a2
+[0-9a-f]+[048c] <[^>]*> 91883ab0[ \t]+\[!a1\] add \.D1X a1,b2,a3
+[0-9a-f]+[048c] <[^>]*> 04a0fab2[ \t]+add \.D2X b7,a8,b9
+[0-9a-f]+[048c] <[^>]*> 00842af0[ \t]+add \.D1 a1,1,a1
+[0-9a-f]+[048c] <[^>]*> 0a936af2[ \t]+add \.D2 b4,-5,b21
+[0-9a-f]+[048c] <[^>]*> 52161af0[ \t]+\[!b1\] add \.D1X b5,-16,a4
+[0-9a-f]+[048c] <[^>]*> 0489faf2[ \t]+add \.D2X a2,15,b9
+[0-9a-f]+[048c] <[^>]*> 07955840[ \t]+addab \.D1 a5,a10,a15
+[0-9a-f]+[048c] <[^>]*> ab62f842[ \t]+\[a2\] addab \.D2 b24,b23,b22
+[0-9a-f]+[048c] <[^>]*> 6e67f940[ \t]+\[b2\] addab \.D1 a25,31,a28
+[0-9a-f]+[048c] <[^>]*> 03901942[ \t]+addab \.D2 b4,0,b7
+[0-9a-f]+[048c] <[^>]*> 12ffff3c[ \t]+addab \.D1X b14,32767,a5
+[0-9a-f]+[048c] <[^>]*> 1e8020be[ \t]+addab \.D2 b15,32,b29
+[0-9a-f]+[048c] <[^>]*> 0590fe40[ \t]+addad \.D1 a4,a7,a11
+[0-9a-f]+[048c] <[^>]*> b6951e42[ \t]+\[!a2\] addad \.D2 b5,b8,b13
+[0-9a-f]+[048c] <[^>]*> 7237fec0[ \t]+\[!b2\] addad \.D1 a13,31,a4
+[0-9a-f]+[048c] <[^>]*> 02d41ec2[ \t]+addad \.D2 b21,0,b5
+[0-9a-f]+[048c] <[^>]*> 07955a40[ \t]+addah \.D1 a5,a10,a15
+[0-9a-f]+[048c] <[^>]*> cb62fa42[ \t]+\[a0\] addah \.D2 b24,b23,b22
+[0-9a-f]+[048c] <[^>]*> 2e67fb40[ \t]+\[b0\] addah \.D1 a25,31,a28
+[0-9a-f]+[048c] <[^>]*> 03901b42[ \t]+addah \.D2 b4,0,b7
+[0-9a-f]+[048c] <[^>]*> 12ffff5c[ \t]+addah \.D1X b14,32767,a5
+[0-9a-f]+[048c] <[^>]*> 1e8020de[ \t]+addah \.D2 b15,32,b29
+[0-9a-f]+[048c] <[^>]*> 07955c40[ \t]+addaw \.D1 a5,a10,a15
+[0-9a-f]+[048c] <[^>]*> db62fc42[ \t]+\[!a0\] addaw \.D2 b24,b23,b22
+[0-9a-f]+[048c] <[^>]*> 3e67fd40[ \t]+\[!b0\] addaw \.D1 a25,31,a28
+[0-9a-f]+[048c] <[^>]*> 03901d42[ \t]+addaw \.D2 b4,0,b7
+[0-9a-f]+[048c] <[^>]*> 12ffff7c[ \t]+addaw \.D1X b14,32767,a5
+[0-9a-f]+[048c] <[^>]*> 1e8020fe[ \t]+addaw \.D2 b15,32,b29
+[0-9a-f]+[048c] <[^>]*> 09384318[ \t]+adddp \.L1 a3:a2,a15:a14,a19:a18
+[0-9a-f]+[048c] <[^>]*> 4a191318[ \t]+\[b1\] adddp \.L1X a9:a8,b7:b6,a21:a20
+[0-9a-f]+[048c] <[^>]*> 0938431a[ \t]+adddp \.L2 b3:b2,b15:b14,b19:b18
+[0-9a-f]+[048c] <[^>]*> 4a19131a[ \t]+\[b1\] adddp \.L2X b9:b8,a7:a6,b21:b20
+[0-9a-f]+[048c] <[^>]*> 8e618e58[ \t]+\[a1\] adddp \.S1 a13:a12,a25:a24,a29:a28
+[0-9a-f]+[048c] <[^>]*> 0f425e58[ \t]+adddp \.S1X a19:a18,b17:b16,a31:a30
+[0-9a-f]+[048c] <[^>]*> 8e618e5a[ \t]+\[a1\] adddp \.S2 b13:b12,b25:b24,b29:b28
+[0-9a-f]+[048c] <[^>]*> 0f425e5a[ \t]+adddp \.S2X b19:b18,a17:a16,b31:b30
+[0-9a-f]+[048c] <[^>]*> 02c00050[ \t]+addk \.S1 -32768,a5
+[0-9a-f]+[048c] <[^>]*> 923fffd2[ \t]+\[!a1\] addk \.S2 32767,b4
+[0-9a-f]+[048c] <[^>]*> 0398a218[ \t]+addsp \.L1 a5,a6,a7
+[0-9a-f]+[048c] <[^>]*> 5a28b218[ \t]+\[!b1\] addsp \.L1X a5,b10,a20
+[0-9a-f]+[048c] <[^>]*> abe3221a[ \t]+\[a2\] addsp \.L2 b25,b24,b23
+[0-9a-f]+[048c] <[^>]*> 0553d21a[ \t]+addsp \.L2X b30,a20,b10
+[0-9a-f]+[048c] <[^>]*> 0398ae18[ \t]+addsp \.S1 a5,a6,a7
+[0-9a-f]+[048c] <[^>]*> 6a28be18[ \t]+\[b2\] addsp \.S1X a5,b10,a20
+[0-9a-f]+[048c] <[^>]*> bbe32e1a[ \t]+\[!a2\] addsp \.S2 b25,b24,b23
+[0-9a-f]+[048c] <[^>]*> 0553de1a[ \t]+addsp \.S2X b30,a20,b10
+[0-9a-f]+[048c] <[^>]*> 1c56c198[ \t]+addsub \.L1 a22,a21,a25:a24
+[0-9a-f]+[048c] <[^>]*> 184e9198[ \t]+addsub \.L1X a20,b19,a17:a16
+[0-9a-f]+[048c] <[^>]*> 181c819a[ \t]+addsub \.L2 b4,b7,b17:b16
+[0-9a-f]+[048c] <[^>]*> 1020919a[ \t]+addsub \.L2X b4,a8,b1:b0
+[0-9a-f]+[048c] <[^>]*> 1c56c1b8[ \t]+addsub2 \.L1 a22,a21,a25:a24
+[0-9a-f]+[048c] <[^>]*> 184e91b8[ \t]+addsub2 \.L1X a20,b19,a17:a16
+[0-9a-f]+[048c] <[^>]*> 181c81ba[ \t]+addsub2 \.L2 b4,b7,b17:b16
+[0-9a-f]+[048c] <[^>]*> 102091ba[ \t]+addsub2 \.L2X b4,a8,b1:b0
+[0-9a-f]+[048c] <[^>]*> 73148578[ \t]+\[!b2\] addu \.L1 a4,a5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 0e4e9578[ \t]+addu \.L1X a20,b19,a29:a28
+[0-9a-f]+[048c] <[^>]*> c429657a[ \t]+\[a0\] addu \.L2 b11,b10,b9:b8
+[0-9a-f]+[048c] <[^>]*> 011c957a[ \t]+addu \.L2X b4,a7,b3:b2
+[0-9a-f]+[048c] <[^>]*> 03216538[ \t]+addu \.L1 a11,a9:a8,a7:a6
+[0-9a-f]+[048c] <[^>]*> 2b529538[ \t]+\[b0\] addu \.L1X b20,a21:a20,a23:a22
+[0-9a-f]+[048c] <[^>]*> dd52e53a[ \t]+\[!a0\] addu \.L2 b23,b21:b20,b27:b26
+[0-9a-f]+[048c] <[^>]*> 0941d53a[ \t]+addu \.L2X a14,b17:b16,b19:b18
+[0-9a-f]+[048c] <[^>]*> 0298e060[ \t]+add2 \.S1 a7,a6,a5
+[0-9a-f]+[048c] <[^>]*> 34255060[ \t]+\[!b0\] add2 \.S1X a10,b9,a8
+[0-9a-f]+[048c] <[^>]*> 08464062[ \t]+add2 \.S2 b18,b17,b16
+[0-9a-f]+[048c] <[^>]*> 4af6d062[ \t]+\[b1\] add2 \.S2X b22,a29,b21
+[0-9a-f]+[048c] <[^>]*> 0298e0b8[ \t]+add2 \.L1 a7,a6,a5
+[0-9a-f]+[048c] <[^>]*> 842550b8[ \t]+\[a1\] add2 \.L1X a10,b9,a8
+[0-9a-f]+[048c] <[^>]*> 084640ba[ \t]+add2 \.L2 b18,b17,b16
+[0-9a-f]+[048c] <[^>]*> 9af6d0ba[ \t]+\[!a1\] add2 \.L2X b22,a29,b21
+[0-9a-f]+[048c] <[^>]*> 0298e930[ \t]+add2 \.D1 a7,a6,a5
+[0-9a-f]+[048c] <[^>]*> 54255930[ \t]+\[!b1\] add2 \.D1X a10,b9,a8
+[0-9a-f]+[048c] <[^>]*> 08464932[ \t]+add2 \.D2 b18,b17,b16
+[0-9a-f]+[048c] <[^>]*> aaf6d932[ \t]+\[a2\] add2 \.D2X b22,a29,b21
+[0-9a-f]+[048c] <[^>]*> 6c6fccb8[ \t]+\[b2\] add4 \.L1 a30,a27,a24
+[0-9a-f]+[048c] <[^>]*> 0ce2fcb8[ \t]+add4 \.L1X a23,b24,a25
+[0-9a-f]+[048c] <[^>]*> 0deb0cba[ \t]+add4 \.L2 b24,b26,b27
+[0-9a-f]+[048c] <[^>]*> ba45dcba[ \t]+\[!a2\] add4 \.L2X b14,a17,b20
+[0-9a-f]+[048c] <[^>]*> 71882f78[ \t]+\[!b2\] and \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 058d5f78[ \t]+and \.L1X a10,b3,a11
+[0-9a-f]+[048c] <[^>]*> cede6f7a[ \t]+\[a0\] and \.L2 b19,b23,b29
+[0-9a-f]+[048c] <[^>]*> 04a0ff7a[ \t]+and \.L2X b7,a8,b9
+[0-9a-f]+[048c] <[^>]*> 02920f58[ \t]+and \.L1 -16,a4,a5
+[0-9a-f]+[048c] <[^>]*> 2399ff58[ \t]+\[b0\] and \.L1X 15,b6,a7
+[0-9a-f]+[048c] <[^>]*> d953af5a[ \t]+\[!a0\] and \.L2 -3,b20,b18
+[0-9a-f]+[048c] <[^>]*> 09513f5a[ \t]+and \.L2X 9,a20,b18
+[0-9a-f]+[048c] <[^>]*> 318827e0[ \t]+\[!b0\] and \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 058d57e0[ \t]+and \.S1X a10,b3,a11
+[0-9a-f]+[048c] <[^>]*> 8ede67e2[ \t]+\[a1\] and \.S2 b19,b23,b29
+[0-9a-f]+[048c] <[^>]*> 04a0f7e2[ \t]+and \.S2X b7,a8,b9
+[0-9a-f]+[048c] <[^>]*> 029207a0[ \t]+and \.S1 -16,a4,a5
+[0-9a-f]+[048c] <[^>]*> 4399f7a0[ \t]+\[b1\] and \.S1X 15,b6,a7
+[0-9a-f]+[048c] <[^>]*> 995187a2[ \t]+\[!a1\] and \.S2 12,b20,b18
+[0-9a-f]+[048c] <[^>]*> 095317a2[ \t]+and \.S2X -8,a20,b18
+[0-9a-f]+[048c] <[^>]*> 518829b0[ \t]+\[!b1\] and \.D1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 058d59b0[ \t]+and \.D1X a10,b3,a11
+[0-9a-f]+[048c] <[^>]*> aede69b2[ \t]+\[a2\] and \.D2 b19,b23,b29
+[0-9a-f]+[048c] <[^>]*> 04a0f9b2[ \t]+and \.D2X b7,a8,b9
+[0-9a-f]+[048c] <[^>]*> 029209f0[ \t]+and \.D1 -16,a4,a5
+[0-9a-f]+[048c] <[^>]*> 6399f9f0[ \t]+\[b2\] and \.D1X 15,b6,a7
+[0-9a-f]+[048c] <[^>]*> b95249f2[ \t]+\[!a2\] and \.D2 -14,b20,b18
+[0-9a-f]+[048c] <[^>]*> 0951b9f2[ \t]+and \.D2X 13,a20,b18
+[0-9a-f]+[048c] <[^>]*> 08ca8f98[ \t]+andn \.L1 a20,a18,a17
+[0-9a-f]+[048c] <[^>]*> 773e1f98[ \t]+\[!b2\] andn \.L1X a16,b15,a14
+[0-9a-f]+[048c] <[^>]*> cde6ef9a[ \t]+\[a0\] andn \.L2 b23,b25,b27
+[0-9a-f]+[048c] <[^>]*> 04149f9a[ \t]+andn \.L2X b4,a5,b8
+[0-9a-f]+[048c] <[^>]*> 08ca8db0[ \t]+andn \.S1 a20,a18,a17
+[0-9a-f]+[048c] <[^>]*> 273e1db0[ \t]+\[b0\] andn \.S1X a16,b15,a14
+[0-9a-f]+[048c] <[^>]*> dde6edb2[ \t]+\[!a0\] andn \.S2 b23,b25,b27
+[0-9a-f]+[048c] <[^>]*> 04149db2[ \t]+andn \.S2X b4,a5,b8
+[0-9a-f]+[048c] <[^>]*> 08ca8830[ \t]+andn \.D1 a20,a18,a17
+[0-9a-f]+[048c] <[^>]*> 373e1830[ \t]+\[!b0\] andn \.D1X a16,b15,a14
+[0-9a-f]+[048c] <[^>]*> 8de6e832[ \t]+\[a1\] andn \.D2 b23,b25,b27
+[0-9a-f]+[048c] <[^>]*> 04149832[ \t]+andn \.D2X b4,a5,b8
+[0-9a-f]+[048c] <[^>]*> 072d04f0[ \t]+avg2 \.M1 a8,a11,a14
+[0-9a-f]+[048c] <[^>]*> 4bd234f0[ \t]+\[b1\] avg2 \.M1X a17,b20,a23
+[0-9a-f]+[048c] <[^>]*> 007744f2[ \t]+avg2 \.M2 b26,b29,b0
+[0-9a-f]+[048c] <[^>]*> 949874f2[ \t]+\[!a1\] avg2 \.M2X b3,a6,b9
+[0-9a-f]+[048c] <[^>]*> 072d04b0[ \t]+avgu4 \.M1 a8,a11,a14
+[0-9a-f]+[048c] <[^>]*> 5bd234b0[ \t]+\[!b1\] avgu4 \.M1X a17,b20,a23
+[0-9a-f]+[048c] <[^>]*> 007744b2[ \t]+avgu4 \.M2 b26,b29,b0
+[0-9a-f]+[048c] <[^>]*> a49874b2[ \t]+\[a2\] avgu4 \.M2X b3,a6,b9
+[0-9a-f]+[048c] <[^>]*> 00100362[ \t]+b \.S2 b4
+[0-9a-f]+[048c] <[^>]*> 60101362[ \t]+\[b2\] b \.S2X a4
+[0-9a-f]+[048c] <[^>]*> b0100362[ \t]+\[!a2\] b \.S2 b4
+[0-9a-f]+[048c] <[^>]*> 00101362[ \t]+b \.S2X a4
+[0-9a-f]+[048c] <[^>]*> 00100362[ \t]+b \.S2 b4
+[0-9a-f]+[048c] <[^>]*> 70101362[ \t]+\[!b2\] b \.S2X a4
+[0-9a-f]+[048c] <[^>]*> 00100362[ \t]+b \.S2 b4
+[0-9a-f]+[048c] <[^>]*> c0101362[ \t]+\[a0\] b \.S2X a4
+[0-9a-f]+[048c] <[^>]*> 201800e2[ \t]+\[b0\] b \.S2 irp
+[0-9a-f]+[048c] <[^>]*> d01c00e2[ \t]+\[!a0\] b \.S2 nrp
+[0-9a-f]+[048c] <[^>]*> 001800e2[ \t]+b \.S2 irp
+[0-9a-f]+[048c] <[^>]*> c01c00e2[ \t]+\[a0\] b \.S2 nrp
+[0-9a-f]+[048c] <[^>]*> 201800e2[ \t]+\[b0\] b \.S2 irp
+[0-9a-f]+[048c] <[^>]*> 001c00e2[ \t]+b \.S2 nrp
+[0-9a-f]+[048c] <[^>]*> 201800e2[ \t]+\[b0\] b \.S2 irp
+[0-9a-f]+[048c] <[^>]*> 001c00e2[ \t]+b \.S2 nrp
+[0-9a-f]+[048c] <[^>]*> 0713c0f0[ \t]+bitc4 \.M1 a4,a14
+[0-9a-f]+[048c] <[^>]*> 3797d0f0[ \t]+\[!b0\] bitc4 \.M1X b5,a15
+[0-9a-f]+[048c] <[^>]*> 0d43c0f2[ \t]+bitc4 \.M2 b16,b26
+[0-9a-f]+[048c] <[^>]*> 4f87d0f2[ \t]+\[b1\] bitc4 \.M2X a1,b31
+[0-9a-f]+[048c] <[^>]*> 0713e0f0[ \t]+bitr \.M1 a4,a14
+[0-9a-f]+[048c] <[^>]*> 8797f0f0[ \t]+\[a1\] bitr \.M1X b5,a15
+[0-9a-f]+[048c] <[^>]*> 0d43e0f2[ \t]+bitr \.M2 b16,b26
+[0-9a-f]+[048c] <[^>]*> 9f87f0f2[ \t]+\[!a1\] bitr \.M2X a1,b31
+[0-9a-f]+[048c] <[^>]*> 00940362[ \t]+bnop \.S2 b5,0
+[0-9a-f]+[048c] <[^>]*> 50d0f362[ \t]+\[!b1\] bnop \.S2X a20,7
+[0-9a-f]+[048c] <[^>]*> 00940362[ \t]+bnop \.S2 b5,0
+[0-9a-f]+[048c] <[^>]*> a0d0f362[ \t]+\[a2\] bnop \.S2X a20,7
+[0-9a-f]+[048c] <[^>]*> 05141fc8[ \t]+clr \.S1 a5,0,31,a10
+[0-9a-f]+[048c] <[^>]*> 62abe0ca[ \t]+\[b2\] clr \.S2 b10,31,0,b5
+[0-9a-f]+[048c] <[^>]*> ba9dcfe0[ \t]+\[!a2\] clr \.S1 a7,a14,a21
+[0-9a-f]+[048c] <[^>]*> 0da65fe0[ \t]+clr \.S1X b9,a18,a27
+[0-9a-f]+[048c] <[^>]*> 08524fe2[ \t]+clr \.S2 b20,b18,b16
+[0-9a-f]+[048c] <[^>]*> 7f921fe2[ \t]+\[!b2\] clr \.S2X a4,b16,b31
+[0-9a-f]+[048c] <[^>]*> 018c2a78[ \t]+cmpeq \.L1 a1,a3,a3
+[0-9a-f]+[048c] <[^>]*> c3903a78[ \t]+\[a0\] cmpeq \.L1X a1,b4,a7
+[0-9a-f]+[048c] <[^>]*> 262d4a7a[ \t]+\[b0\] cmpeq \.L2 b10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 07b9ba7a[ \t]+cmpeq \.L2X b13,a14,b15
+[0-9a-f]+[048c] <[^>]*> d8c20a58[ \t]+\[!a0\] cmpeq \.L1 -16,a16,a17
+[0-9a-f]+[048c] <[^>]*> 09c9fa58[ \t]+cmpeq \.L1X 15,b18,a19
+[0-9a-f]+[048c] <[^>]*> 0b506a5a[ \t]+cmpeq \.L2 3,b20,b22
+[0-9a-f]+[048c] <[^>]*> 3cdc9a5a[ \t]+\[!b0\] cmpeq \.L2X 4,a23,b25
+[0-9a-f]+[048c] <[^>]*> 09188a38[ \t]+cmpeq \.L1 a4,a7:a6,a18
+[0-9a-f]+[048c] <[^>]*> 8a293a38[ \t]+\[a1\] cmpeq \.L1X b9,a11:a10,a20
+[0-9a-f]+[048c] <[^>]*> 0cdaaa3a[ \t]+cmpeq \.L2 b21,b23:b22,b25
+[0-9a-f]+[048c] <[^>]*> 4de27a3a[ \t]+\[b1\] cmpeq \.L2X a19,b25:b24,b27
+[0-9a-f]+[048c] <[^>]*> 9b3a0a18[ \t]+\[!a1\] cmpeq \.L1 -16,a15:a14,a22
+[0-9a-f]+[048c] <[^>]*> 58c9ea1a[ \t]+\[!b1\] cmpeq \.L2 15,b19:b18,b17
+[0-9a-f]+[048c] <[^>]*> 05256760[ \t]+cmpeq2 \.S1 a11,a9,a10
+[0-9a-f]+[048c] <[^>]*> a7b99760[ \t]+\[a2\] cmpeq2 \.S1X a12,b14,a15
+[0-9a-f]+[048c] <[^>]*> 0c520762[ \t]+cmpeq2 \.S2 b16,b20,b24
+[0-9a-f]+[048c] <[^>]*> 6b5e7762[ \t]+\[b2\] cmpeq2 \.S2X b19,a23,b22
+[0-9a-f]+[048c] <[^>]*> bd5e8720[ \t]+\[!a2\] cmpeq4 \.S1 a20,a23,a26
+[0-9a-f]+[048c] <[^>]*> 0793f720[ \t]+cmpeq4 \.S1X a31,b4,a15
+[0-9a-f]+[048c] <[^>]*> 72e92722[ \t]+\[!b2\] cmpeq4 \.S2 b9,b26,b5
+[0-9a-f]+[048c] <[^>]*> 04147722[ \t]+cmpeq4 \.S2X b3,a5,b8
+[0-9a-f]+[048c] <[^>]*> 02990a20[ \t]+cmpeqdp \.S1 a9:a8,a7:a6,a5
+[0-9a-f]+[048c] <[^>]*> cf805a20[ \t]+\[a0\] cmpeqdp \.S1X a3:a2,b1:b0,a31
+[0-9a-f]+[048c] <[^>]*> 2cc28a22[ \t]+\[b0\] cmpeqdp \.S2 b21:b20,b17:b16,b25
+[0-9a-f]+[048c] <[^>]*> 04989a22[ \t]+cmpeqdp \.S2X b5:b4,a7:a6,b9
+[0-9a-f]+[048c] <[^>]*> 0b568e20[ \t]+cmpeqsp \.S1 a20,a21,a22
+[0-9a-f]+[048c] <[^>]*> 3ce2fe20[ \t]+\[!b0\] cmpeqsp \.S1X a23,b24,a25
+[0-9a-f]+[048c] <[^>]*> de6f4e22[ \t]+\[!a0\] cmpeqsp \.S2 b26,b27,b28
+[0-9a-f]+[048c] <[^>]*> 0ffbbe22[ \t]+cmpeqsp \.S2X b29,a30,b31
+[0-9a-f]+[048c] <[^>]*> 018c28f8[ \t]+cmpgt \.L1 a1,a3,a3
+[0-9a-f]+[048c] <[^>]*> 839038f8[ \t]+\[a1\] cmpgt \.L1X a1,b4,a7
+[0-9a-f]+[048c] <[^>]*> 462d48fa[ \t]+\[b1\] cmpgt \.L2 b10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 07b9b8fa[ \t]+cmpgt \.L2X b13,a14,b15
+[0-9a-f]+[048c] <[^>]*> 98c208d8[ \t]+\[!a1\] cmpgt \.L1 -16,a16,a17
+[0-9a-f]+[048c] <[^>]*> 09c9f8d8[ \t]+cmpgt \.L1X 15,b18,a19
+[0-9a-f]+[048c] <[^>]*> 0b5068da[ \t]+cmpgt \.L2 3,b20,b22
+[0-9a-f]+[048c] <[^>]*> 5cdc98da[ \t]+\[!b1\] cmpgt \.L2X 4,a23,b25
+[0-9a-f]+[048c] <[^>]*> 091888b8[ \t]+cmpgt \.L1 a4,a7:a6,a18
+[0-9a-f]+[048c] <[^>]*> aa2938b8[ \t]+\[a2\] cmpgt \.L1X b9,a11:a10,a20
+[0-9a-f]+[048c] <[^>]*> 0cdaa8ba[ \t]+cmpgt \.L2 b21,b23:b22,b25
+[0-9a-f]+[048c] <[^>]*> 6de278ba[ \t]+\[b2\] cmpgt \.L2X a19,b25:b24,b27
+[0-9a-f]+[048c] <[^>]*> bb3a0898[ \t]+\[!a2\] cmpgt \.L1 -16,a15:a14,a22
+[0-9a-f]+[048c] <[^>]*> 78c9e89a[ \t]+\[!b2\] cmpgt \.L2 15,b19:b18,b17
+[0-9a-f]+[048c] <[^>]*> 83903af8[ \t]+\[a1\] cmplt \.L1X a1,b4,a7
+[0-9a-f]+[048c] <[^>]*> 07b9bafa[ \t]+cmplt \.L2X b13,a14,b15
+[0-9a-f]+[048c] <[^>]*> 98c20ad8[ \t]+\[!a1\] cmplt \.L1 -16,a16,a17
+[0-9a-f]+[048c] <[^>]*> 09c9fad8[ \t]+cmplt \.L1X 15,b18,a19
+[0-9a-f]+[048c] <[^>]*> 0b506ada[ \t]+cmplt \.L2 3,b20,b22
+[0-9a-f]+[048c] <[^>]*> 5cdc9ada[ \t]+\[!b1\] cmplt \.L2X 4,a23,b25
+[0-9a-f]+[048c] <[^>]*> 09188ab8[ \t]+cmplt \.L1 a4,a7:a6,a18
+[0-9a-f]+[048c] <[^>]*> aa293ab8[ \t]+\[a2\] cmplt \.L1X b9,a11:a10,a20
+[0-9a-f]+[048c] <[^>]*> 0cdaaaba[ \t]+cmplt \.L2 b21,b23:b22,b25
+[0-9a-f]+[048c] <[^>]*> 6de27aba[ \t]+\[b2\] cmplt \.L2X a19,b25:b24,b27
+[0-9a-f]+[048c] <[^>]*> bb3a0a98[ \t]+\[!a2\] cmplt \.L1 -16,a15:a14,a22
+[0-9a-f]+[048c] <[^>]*> 78c9ea9a[ \t]+\[!b2\] cmplt \.L2 15,b19:b18,b17
+[0-9a-f]+[048c] <[^>]*> 073e0520[ \t]+cmpgt2 \.S1 a16,a15,a14
+[0-9a-f]+[048c] <[^>]*> c5b1b520[ \t]+\[a0\] cmpgt2 \.S1X a13,b12,a11
+[0-9a-f]+[048c] <[^>]*> 04254522[ \t]+cmpgt2 \.S2 b10,b9,b8
+[0-9a-f]+[048c] <[^>]*> 2298f522[ \t]+\[b0\] cmpgt2 \.S2X b7,a6,b5
+[0-9a-f]+[048c] <[^>]*> df804a60[ \t]+\[!a0\] cmpgtdp \.S1 a3:a2,a1:a0,a31
+[0-9a-f]+[048c] <[^>]*> 0ceb9a60[ \t]+cmpgtdp \.S1X a29:a28,b27:b26,a25
+[0-9a-f]+[048c] <[^>]*> 09d2ca62[ \t]+cmpgtdp \.S2 b23:b22,b21:b20,b19
+[0-9a-f]+[048c] <[^>]*> 36ba1a62[ \t]+\[!b0\] cmpgtdp \.S2X b17:b16,a15:a14,b13
+[0-9a-f]+[048c] <[^>]*> 8f846e60[ \t]+\[a1\] cmpgtsp \.S1 a3,a1,a31
+[0-9a-f]+[048c] <[^>]*> 0cefbe60[ \t]+cmpgtsp \.S1X a29,b27,a25
+[0-9a-f]+[048c] <[^>]*> 09d6ee62[ \t]+cmpgtsp \.S2 b23,b21,b19
+[0-9a-f]+[048c] <[^>]*> 46be3e62[ \t]+\[b1\] cmpgtsp \.S2X b17,a15,b13
+[0-9a-f]+[048c] <[^>]*> 018c29f8[ \t]+cmpgtu \.L1 a1,a3,a3
+[0-9a-f]+[048c] <[^>]*> 839039f8[ \t]+\[a1\] cmpgtu \.L1X a1,b4,a7
+[0-9a-f]+[048c] <[^>]*> 462d49fa[ \t]+\[b1\] cmpgtu \.L2 b10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 07b9b9fa[ \t]+cmpgtu \.L2X b13,a14,b15
+[0-9a-f]+[048c] <[^>]*> 98c009d8[ \t]+\[!a1\] cmpgtu \.L1 0,a16,a17
+[0-9a-f]+[048c] <[^>]*> 09cbf9d8[ \t]+cmpgtu \.L1X 31,b18,a19
+[0-9a-f]+[048c] <[^>]*> 0b5069da[ \t]+cmpgtu \.L2 3,b20,b22
+[0-9a-f]+[048c] <[^>]*> 5cdc99da[ \t]+\[!b1\] cmpgtu \.L2X 4,a23,b25
+[0-9a-f]+[048c] <[^>]*> 091889b8[ \t]+cmpgtu \.L1 a4,a7:a6,a18
+[0-9a-f]+[048c] <[^>]*> aa2939b8[ \t]+\[a2\] cmpgtu \.L1X b9,a11:a10,a20
+[0-9a-f]+[048c] <[^>]*> 0cdaa9ba[ \t]+cmpgtu \.L2 b21,b23:b22,b25
+[0-9a-f]+[048c] <[^>]*> 6de279ba[ \t]+\[b2\] cmpgtu \.L2X a19,b25:b24,b27
+[0-9a-f]+[048c] <[^>]*> bb380998[ \t]+\[!a2\] cmpgtu \.L1 0,a15:a14,a22
+[0-9a-f]+[048c] <[^>]*> 78cbe99a[ \t]+\[!b2\] cmpgtu \.L2 31,b19:b18,b17
+[0-9a-f]+[048c] <[^>]*> 0bef2560[ \t]+cmpgtu4 \.S1 a25,a27,a23
+[0-9a-f]+[048c] <[^>]*> c8d2b560[ \t]+\[a0\] cmpgtu4 \.S1X a21,b20,a17
+[0-9a-f]+[048c] <[^>]*> 08b56562[ \t]+cmpgtu4 \.S2 b11,b13,b17
+[0-9a-f]+[048c] <[^>]*> 2ede7562[ \t]+\[b0\] cmpgtu4 \.S2X b19,a23,b29
+[0-9a-f]+[048c] <[^>]*> 018c2af8[ \t]+cmplt \.L1 a1,a3,a3
+[0-9a-f]+[048c] <[^>]*> 83903af8[ \t]+\[a1\] cmplt \.L1X a1,b4,a7
+[0-9a-f]+[048c] <[^>]*> 462d4afa[ \t]+\[b1\] cmplt \.L2 b10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 07b9bafa[ \t]+cmplt \.L2X b13,a14,b15
+[0-9a-f]+[048c] <[^>]*> 98c20ad8[ \t]+\[!a1\] cmplt \.L1 -16,a16,a17
+[0-9a-f]+[048c] <[^>]*> 09c9fad8[ \t]+cmplt \.L1X 15,b18,a19
+[0-9a-f]+[048c] <[^>]*> 0b506ada[ \t]+cmplt \.L2 3,b20,b22
+[0-9a-f]+[048c] <[^>]*> 5cdc9ada[ \t]+\[!b1\] cmplt \.L2X 4,a23,b25
+[0-9a-f]+[048c] <[^>]*> 09188ab8[ \t]+cmplt \.L1 a4,a7:a6,a18
+[0-9a-f]+[048c] <[^>]*> aa293ab8[ \t]+\[a2\] cmplt \.L1X b9,a11:a10,a20
+[0-9a-f]+[048c] <[^>]*> 0cdaaaba[ \t]+cmplt \.L2 b21,b23:b22,b25
+[0-9a-f]+[048c] <[^>]*> 6de27aba[ \t]+\[b2\] cmplt \.L2X a19,b25:b24,b27
+[0-9a-f]+[048c] <[^>]*> bb3a0a98[ \t]+\[!a2\] cmplt \.L1 -16,a15:a14,a22
+[0-9a-f]+[048c] <[^>]*> 78c9ea9a[ \t]+\[!b2\] cmplt \.L2 15,b19:b18,b17
+[0-9a-f]+[048c] <[^>]*> 839038f8[ \t]+\[a1\] cmpgt \.L1X a1,b4,a7
+[0-9a-f]+[048c] <[^>]*> 07b9b8fa[ \t]+cmpgt \.L2X b13,a14,b15
+[0-9a-f]+[048c] <[^>]*> 98c208d8[ \t]+\[!a1\] cmpgt \.L1 -16,a16,a17
+[0-9a-f]+[048c] <[^>]*> 09c9f8d8[ \t]+cmpgt \.L1X 15,b18,a19
+[0-9a-f]+[048c] <[^>]*> 0b5068da[ \t]+cmpgt \.L2 3,b20,b22
+[0-9a-f]+[048c] <[^>]*> 5cdc98da[ \t]+\[!b1\] cmpgt \.L2X 4,a23,b25
+[0-9a-f]+[048c] <[^>]*> 091888b8[ \t]+cmpgt \.L1 a4,a7:a6,a18
+[0-9a-f]+[048c] <[^>]*> aa2938b8[ \t]+\[a2\] cmpgt \.L1X b9,a11:a10,a20
+[0-9a-f]+[048c] <[^>]*> 0cdaa8ba[ \t]+cmpgt \.L2 b21,b23:b22,b25
+[0-9a-f]+[048c] <[^>]*> 6de278ba[ \t]+\[b2\] cmpgt \.L2X a19,b25:b24,b27
+[0-9a-f]+[048c] <[^>]*> bb3a0898[ \t]+\[!a2\] cmpgt \.L1 -16,a15:a14,a22
+[0-9a-f]+[048c] <[^>]*> 78c9e89a[ \t]+\[!b2\] cmpgt \.L2 15,b19:b18,b17
+[0-9a-f]+[048c] <[^>]*> 0741e520[ \t]+cmpgt2 \.S1 a15,a16,a14
+[0-9a-f]+[048c] <[^>]*> c5b1b520[ \t]+\[a0\] cmpgt2 \.S1X a13,b12,a11
+[0-9a-f]+[048c] <[^>]*> 04292522[ \t]+cmpgt2 \.S2 b9,b10,b8
+[0-9a-f]+[048c] <[^>]*> 2298f522[ \t]+\[b0\] cmpgt2 \.S2X b7,a6,b5
+[0-9a-f]+[048c] <[^>]*> df804aa0[ \t]+\[!a0\] cmpltdp \.S1 a3:a2,a1:a0,a31
+[0-9a-f]+[048c] <[^>]*> 0ceb9aa0[ \t]+cmpltdp \.S1X a29:a28,b27:b26,a25
+[0-9a-f]+[048c] <[^>]*> 09d2caa2[ \t]+cmpltdp \.S2 b23:b22,b21:b20,b19
+[0-9a-f]+[048c] <[^>]*> 36ba1aa2[ \t]+\[!b0\] cmpltdp \.S2X b17:b16,a15:a14,b13
+[0-9a-f]+[048c] <[^>]*> 8f846ea0[ \t]+\[a1\] cmpltsp \.S1 a3,a1,a31
+[0-9a-f]+[048c] <[^>]*> 0cefbea0[ \t]+cmpltsp \.S1X a29,b27,a25
+[0-9a-f]+[048c] <[^>]*> 09d6eea2[ \t]+cmpltsp \.S2 b23,b21,b19
+[0-9a-f]+[048c] <[^>]*> 46be3ea2[ \t]+\[b1\] cmpltsp \.S2X b17,a15,b13
+[0-9a-f]+[048c] <[^>]*> 018c2bf8[ \t]+cmpltu \.L1 a1,a3,a3
+[0-9a-f]+[048c] <[^>]*> 83903bf8[ \t]+\[a1\] cmpltu \.L1X a1,b4,a7
+[0-9a-f]+[048c] <[^>]*> 462d4bfa[ \t]+\[b1\] cmpltu \.L2 b10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 07b9bbfa[ \t]+cmpltu \.L2X b13,a14,b15
+[0-9a-f]+[048c] <[^>]*> 98c00bd8[ \t]+\[!a1\] cmpltu \.L1 0,a16,a17
+[0-9a-f]+[048c] <[^>]*> 09cbfbd8[ \t]+cmpltu \.L1X 31,b18,a19
+[0-9a-f]+[048c] <[^>]*> 0b506bda[ \t]+cmpltu \.L2 3,b20,b22
+[0-9a-f]+[048c] <[^>]*> 5cdc9bda[ \t]+\[!b1\] cmpltu \.L2X 4,a23,b25
+[0-9a-f]+[048c] <[^>]*> 09188bb8[ \t]+cmpltu \.L1 a4,a7:a6,a18
+[0-9a-f]+[048c] <[^>]*> aa293bb8[ \t]+\[a2\] cmpltu \.L1X b9,a11:a10,a20
+[0-9a-f]+[048c] <[^>]*> 0cdaabba[ \t]+cmpltu \.L2 b21,b23:b22,b25
+[0-9a-f]+[048c] <[^>]*> 6de27bba[ \t]+\[b2\] cmpltu \.L2X a19,b25:b24,b27
+[0-9a-f]+[048c] <[^>]*> bb380b98[ \t]+\[!a2\] cmpltu \.L1 0,a15:a14,a22
+[0-9a-f]+[048c] <[^>]*> 78cbeb9a[ \t]+\[!b2\] cmpltu \.L2 31,b19:b18,b17
+[0-9a-f]+[048c] <[^>]*> 0be76560[ \t]+cmpgtu4 \.S1 a27,a25,a23
+[0-9a-f]+[048c] <[^>]*> c8d2b560[ \t]+\[a0\] cmpgtu4 \.S1X a21,b20,a17
+[0-9a-f]+[048c] <[^>]*> 08ada562[ \t]+cmpgtu4 \.S2 b13,b11,b17
+[0-9a-f]+[048c] <[^>]*> 2ede7562[ \t]+\[b0\] cmpgtu4 \.S2X b19,a23,b29
+[0-9a-f]+[048c] <[^>]*> 120822b0[ \t]+cmpy \.M1 a1,a2,a5:a4
+[0-9a-f]+[048c] <[^>]*> 131492b0[ \t]+cmpy \.M1X a4,b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 152502b2[ \t]+cmpy \.M2 b8,b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 163172b2[ \t]+cmpy \.M2X b11,a12,b13:b12
+[0-9a-f]+[048c] <[^>]*> 128822f0[ \t]+cmpyr \.M1 a1,a2,a5
+[0-9a-f]+[048c] <[^>]*> 139492f0[ \t]+cmpyr \.M1X a4,b5,a7
+[0-9a-f]+[048c] <[^>]*> 15a502f2[ \t]+cmpyr \.M2 b8,b9,b11
+[0-9a-f]+[048c] <[^>]*> 16b172f2[ \t]+cmpyr \.M2X b11,a12,b13
+[0-9a-f]+[048c] <[^>]*> 12882330[ \t]+cmpyr1 \.M1 a1,a2,a5
+[0-9a-f]+[048c] <[^>]*> 13949330[ \t]+cmpyr1 \.M1X a4,b5,a7
+[0-9a-f]+[048c] <[^>]*> 15a50332[ \t]+cmpyr1 \.M2 b8,b9,b11
+[0-9a-f]+[048c] <[^>]*> 16b17332[ \t]+cmpyr1 \.M2X b11,a12,b13
+[0-9a-f]+[048c] <[^>]*> 12082630[ \t]+ddotp4 \.M1 a1,a2,a5:a4
+[0-9a-f]+[048c] <[^>]*> 13149630[ \t]+ddotp4 \.M1X a4,b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 15250632[ \t]+ddotp4 \.M2 b8,b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 16317632[ \t]+ddotp4 \.M2X b11,a12,b13:b12
+[0-9a-f]+[048c] <[^>]*> 120805f0[ \t]+ddotph2 \.M1 a1:a0,a2,a5:a4
+[0-9a-f]+[048c] <[^>]*> 131455f0[ \t]+ddotph2 \.M1X a3:a2,b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 1524c5f2[ \t]+ddotph2 \.M2 b7:b6,b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 163155f2[ \t]+ddotph2 \.M2X b11:b10,a12,b13:b12
+[0-9a-f]+[048c] <[^>]*> 12880570[ \t]+ddotph2r \.M1 a1:a0,a2,a5
+[0-9a-f]+[048c] <[^>]*> 13945570[ \t]+ddotph2r \.M1X a3:a2,b5,a7
+[0-9a-f]+[048c] <[^>]*> 15a4c572[ \t]+ddotph2r \.M2 b7:b6,b9,b11
+[0-9a-f]+[048c] <[^>]*> 16b15572[ \t]+ddotph2r \.M2X b11:b10,a12,b13
+[0-9a-f]+[048c] <[^>]*> 120805b0[ \t]+ddotpl2 \.M1 a1:a0,a2,a5:a4
+[0-9a-f]+[048c] <[^>]*> 131455b0[ \t]+ddotpl2 \.M1X a3:a2,b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 1524c5b2[ \t]+ddotpl2 \.M2 b7:b6,b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 163155b2[ \t]+ddotpl2 \.M2X b11:b10,a12,b13:b12
+[0-9a-f]+[048c] <[^>]*> 12880530[ \t]+ddotpl2r \.M1 a1:a0,a2,a5
+[0-9a-f]+[048c] <[^>]*> 13945530[ \t]+ddotpl2r \.M1X a3:a2,b5,a7
+[0-9a-f]+[048c] <[^>]*> 15a4c532[ \t]+ddotpl2r \.M2 b7:b6,b9,b11
+[0-9a-f]+[048c] <[^>]*> 16b15532[ \t]+ddotpl2r \.M2X b11:b10,a12,b13
+[0-9a-f]+[048c] <[^>]*> 04a3a0f0[ \t]+deal \.M1 a8,a9
+[0-9a-f]+[048c] <[^>]*> d5abb0f0[ \t]+\[!a0\] deal \.M1X b10,a11
+[0-9a-f]+[048c] <[^>]*> 36b3a0f2[ \t]+\[!b0\] deal \.M2 b12,b13
+[0-9a-f]+[048c] <[^>]*> 07bbb0f2[ \t]+deal \.M2X a14,b15
+[0-9a-f]+[048c] <[^>]*> 10004000[ \t]+dint
+[0-9a-f]+[048c] <[^>]*> 83148ef0[ \t]+\[a1\] dmv \.S1 a4,a5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 05251ef0[ \t]+dmv \.S1X a8,b9,a11:a10
+[0-9a-f]+[048c] <[^>]*> 07358ef2[ \t]+dmv \.S2 b12,b13,b15:b14
+[0-9a-f]+[048c] <[^>]*> 49461ef2[ \t]+\[b1\] dmv \.S2X b16,a17,b19:b18
+[0-9a-f]+[048c] <[^>]*> 053e8330[ \t]+dotp2 \.M1 a20,a15,a10
+[0-9a-f]+[048c] <[^>]*> 90155330[ \t]+\[!a1\] dotp2 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0ab8e332[ \t]+dotp2 \.M2 b7,b14,b21
+[0-9a-f]+[048c] <[^>]*> 58d2f332[ \t]+\[!b1\] dotp2 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> 053e82f0[ \t]+dotp2 \.M1 a20,a15,a11:a10
+[0-9a-f]+[048c] <[^>]*> a01552f0[ \t]+\[a2\] dotp2 \.M1X a10,b5,a1:a0
+[0-9a-f]+[048c] <[^>]*> 6a38e2f2[ \t]+\[b2\] dotp2 \.M2 b7,b14,b21:b20
+[0-9a-f]+[048c] <[^>]*> 0852f2f2[ \t]+dotp2 \.M2X b23,a20,b17:b16
+[0-9a-f]+[048c] <[^>]*> 053e8270[ \t]+dotpn2 \.M1 a20,a15,a10
+[0-9a-f]+[048c] <[^>]*> b0155270[ \t]+\[!a2\] dotpn2 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0ab8e272[ \t]+dotpn2 \.M2 b7,b14,b21
+[0-9a-f]+[048c] <[^>]*> 78d2f272[ \t]+\[!b2\] dotpn2 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> 053e81f0[ \t]+dotpnrsu2 \.M1 a20,a15,a10
+[0-9a-f]+[048c] <[^>]*> c01551f0[ \t]+\[a0\] dotpnrsu2 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0ab8e1f2[ \t]+dotpnrsu2 \.M2 b7,b14,b21
+[0-9a-f]+[048c] <[^>]*> 28d2f1f2[ \t]+\[b0\] dotpnrsu2 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> d551e1f0[ \t]+\[!a0\] dotpnrsu2 \.M1 a15,a20,a10
+[0-9a-f]+[048c] <[^>]*> 001551f0[ \t]+dotpnrsu2 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0a9dc1f2[ \t]+dotpnrsu2 \.M2 b14,b7,b21
+[0-9a-f]+[048c] <[^>]*> 38d2f1f2[ \t]+\[!b0\] dotpnrsu2 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> 053e8370[ \t]+dotprsu2 \.M1 a20,a15,a10
+[0-9a-f]+[048c] <[^>]*> 80155370[ \t]+\[a1\] dotprsu2 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0ab8e372[ \t]+dotprsu2 \.M2 b7,b14,b21
+[0-9a-f]+[048c] <[^>]*> 48d2f372[ \t]+\[b1\] dotprsu2 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> 9551e370[ \t]+\[!a1\] dotprsu2 \.M1 a15,a20,a10
+[0-9a-f]+[048c] <[^>]*> 00155370[ \t]+dotprsu2 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0a9dc372[ \t]+dotprsu2 \.M2 b14,b7,b21
+[0-9a-f]+[048c] <[^>]*> 58d2f372[ \t]+\[!b1\] dotprsu2 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> 053e80b0[ \t]+dotpsu4 \.M1 a20,a15,a10
+[0-9a-f]+[048c] <[^>]*> a01550b0[ \t]+\[a2\] dotpsu4 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0ab8e0b2[ \t]+dotpsu4 \.M2 b7,b14,b21
+[0-9a-f]+[048c] <[^>]*> 68d2f0b2[ \t]+\[b2\] dotpsu4 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> 0551e0b0[ \t]+dotpsu4 \.M1 a15,a20,a10
+[0-9a-f]+[048c] <[^>]*> b01550b0[ \t]+\[!a2\] dotpsu4 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0a9dc0b2[ \t]+dotpsu4 \.M2 b14,b7,b21
+[0-9a-f]+[048c] <[^>]*> 78d2f0b2[ \t]+\[!b2\] dotpsu4 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> 053e81b0[ \t]+dotpu4 \.M1 a20,a15,a10
+[0-9a-f]+[048c] <[^>]*> c01551b0[ \t]+\[a0\] dotpu4 \.M1X a10,b5,a0
+[0-9a-f]+[048c] <[^>]*> 0ab8e1b2[ \t]+dotpu4 \.M2 b7,b14,b21
+[0-9a-f]+[048c] <[^>]*> 28d2f1b2[ \t]+\[b0\] dotpu4 \.M2X b23,a20,b17
+[0-9a-f]+[048c] <[^>]*> 1c6fc698[ \t]+dpack2 \.L1 a30,a27,a25:a24
+[0-9a-f]+[048c] <[^>]*> 174ab698[ \t]+dpack2 \.L1X a21,b18,a15:a14
+[0-9a-f]+[048c] <[^>]*> 1325869a[ \t]+dpack2 \.L2 b12,b9,b7:b6
+[0-9a-f]+[048c] <[^>]*> 1e00769a[ \t]+dpack2 \.L2X b3,a0,b29:b28
+[0-9a-f]+[048c] <[^>]*> 1c6fc678[ \t]+dpackx2 \.L1 a30,a27,a25:a24
+[0-9a-f]+[048c] <[^>]*> 174ab678[ \t]+dpackx2 \.L1X a21,b18,a15:a14
+[0-9a-f]+[048c] <[^>]*> 1325867a[ \t]+dpackx2 \.L2 b12,b9,b7:b6
+[0-9a-f]+[048c] <[^>]*> 1e00767a[ \t]+dpackx2 \.L2X b3,a0,b29:b28
+[0-9a-f]+[048c] <[^>]*> 01900118[ \t]+dpint \.L1 a5:a4,a3
+[0-9a-f]+[048c] <[^>]*> d190011a[ \t]+\[!a0\] dpint \.L2 b5:b4,b3
+[0-9a-f]+[048c] <[^>]*> 01900138[ \t]+dpsp \.L1 a5:a4,a3
+[0-9a-f]+[048c] <[^>]*> 3190013a[ \t]+\[!b0\] dpsp \.L2 b5:b4,b3
+[0-9a-f]+[048c] <[^>]*> 81900038[ \t]+\[a1\] dptrunc \.L1 a5:a4,a3
+[0-9a-f]+[048c] <[^>]*> 0190003a[ \t]+dptrunc \.L2 b5:b4,b3
+[0-9a-f]+[048c] <[^>]*> 05141f48[ \t]+ext \.S1 a5,0,31,a10
+[0-9a-f]+[048c] <[^>]*> 42abe04a[ \t]+\[b1\] ext \.S2 b10,31,0,b5
+[0-9a-f]+[048c] <[^>]*> 9a9dcbe0[ \t]+\[!a1\] ext \.S1 a7,a14,a21
+[0-9a-f]+[048c] <[^>]*> 0da65be0[ \t]+ext \.S1X b9,a18,a27
+[0-9a-f]+[048c] <[^>]*> 08524be2[ \t]+ext \.S2 b20,b18,b16
+[0-9a-f]+[048c] <[^>]*> 5f921be2[ \t]+\[!b1\] ext \.S2X a4,b16,b31
+[0-9a-f]+[048c] <[^>]*> 05141f08[ \t]+extu \.S1 a5,0,31,a10
+[0-9a-f]+[048c] <[^>]*> a2abe00a[ \t]+\[a2\] extu \.S2 b10,31,0,b5
+[0-9a-f]+[048c] <[^>]*> 6a9dcae0[ \t]+\[b2\] extu \.S1 a7,a14,a21
+[0-9a-f]+[048c] <[^>]*> 0da65ae0[ \t]+extu \.S1X b9,a18,a27
+[0-9a-f]+[048c] <[^>]*> 08524ae2[ \t]+extu \.S2 b20,b18,b16
+[0-9a-f]+[048c] <[^>]*> bf921ae2[ \t]+\[!a2\] extu \.S2X a4,b16,b31
+[0-9a-f]+[048c] <[^>]*> 14c327f0[ \t]+gmpy \.M1 a25,a16,a9
+[0-9a-f]+[048c] <[^>]*> 16b0a7f2[ \t]+gmpy \.M2 b5,b12,b13
+[0-9a-f]+[048c] <[^>]*> 728c4470[ \t]+\[!b2\] gmpy4 \.M1 a2,a3,a5
+[0-9a-f]+[048c] <[^>]*> 06acf470[ \t]+gmpy4 \.M1X a7,b11,a13
+[0-9a-f]+[048c] <[^>]*> 0bce2472[ \t]+gmpy4 \.M2 b17,b19,b23
+[0-9a-f]+[048c] <[^>]*> c2ffb472[ \t]+\[a0\] gmpy4 \.M2X b29,a31,b5
+[0-9a-f]+[048c] <[^>]*> 0001e000[ \t]+idle
+[0-9a-f]+[048c] <[^>]*> 01040738[ \t]+intdp \.L1 a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 23141738[ \t]+\[b0\] intdp \.L1X b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> d524073a[ \t]+\[!a0\] intdp \.L2 b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 0614173a[ \t]+intdp \.L2X a5,b13:b12
+[0-9a-f]+[048c] <[^>]*> 01040778[ \t]+intdpu \.L1 a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 33141778[ \t]+\[!b0\] intdpu \.L1X b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 8524077a[ \t]+\[a1\] intdpu \.L2 b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 0614177a[ \t]+intdpu \.L2X a5,b13:b12
+[0-9a-f]+[048c] <[^>]*> 01840958[ \t]+intsp \.L1 a1,a3
+[0-9a-f]+[048c] <[^>]*> 43941958[ \t]+\[b1\] intsp \.L1X b5,a7
+[0-9a-f]+[048c] <[^>]*> 95a4095a[ \t]+\[!a1\] intsp \.L2 b9,b11
+[0-9a-f]+[048c] <[^>]*> 0694195a[ \t]+intsp \.L2X a5,b13
+[0-9a-f]+[048c] <[^>]*> 01840938[ \t]+intspu \.L1 a1,a3
+[0-9a-f]+[048c] <[^>]*> 53941938[ \t]+\[!b1\] intspu \.L1X b5,a7
+[0-9a-f]+[048c] <[^>]*> a5a4093a[ \t]+\[a2\] intspu \.L2 b9,b11
+[0-9a-f]+[048c] <[^>]*> 0694193a[ \t]+intspu \.L2X a5,b13
+[0-9a-f]+[048c] <[^>]*> 03940224[ \t]+ldb \.D1T1 \*\+a5\(0\),a7
+[0-9a-f]+[048c] <[^>]*> 65a43226[ \t]+\[b2\] ldb \.D1T2 \*\+\+a9\(1\),b11
+[0-9a-f]+[048c] <[^>]*> 07b430a4[ \t]+ldb \.D2T1 \*--b13\(1\),a15
+[0-9a-f]+[048c] <[^>]*> b9c436a6[ \t]+\[!a2\] ldb \.D2T2 \*b17\+\+\(1\),b19
+[0-9a-f]+[048c] <[^>]*> 0bd43424[ \t]+ldb \.D1T1 \*a21--\(1\),a23
+[0-9a-f]+[048c] <[^>]*> 7de7e0a6[ \t]+\[!b2\] ldb \.D2T2 \*-b25\(31\),b27
+[0-9a-f]+[048c] <[^>]*> 0ff40224[ \t]+ldb \.D1T1 \*\+a29\(0\),a31
+[0-9a-f]+[048c] <[^>]*> 01004024[ \t]+ldb \.D1T1 \*-a0\(2\),a2
+[0-9a-f]+[048c] <[^>]*> 0310a824[ \t]+ldb \.D1T1 \*-a4\[a5\],a6
+[0-9a-f]+[048c] <[^>]*> 049d0a24[ \t]+ldb \.D1T1 \*\+a7\[a8\],a9
+[0-9a-f]+[048c] <[^>]*> 06297024[ \t]+ldb \.D1T1 \*--a10\(11\),a12
+[0-9a-f]+[048c] <[^>]*> 07b5d224[ \t]+ldb \.D1T1 \*\+\+a13\(14\),a15
+[0-9a-f]+[048c] <[^>]*> 09423424[ \t]+ldb \.D1T1 \*a16--\(17\),a18
+[0-9a-f]+[048c] <[^>]*> 0ace9624[ \t]+ldb \.D1T1 \*a19\+\+\(20\),a21
+[0-9a-f]+[048c] <[^>]*> 0c5af824[ \t]+ldb \.D1T1 \*--a22\[a23\],a24
+[0-9a-f]+[048c] <[^>]*> 0de75a24[ \t]+ldb \.D1T1 \*\+\+a25\[a26\],a27
+[0-9a-f]+[048c] <[^>]*> 0f73bc24[ \t]+ldb \.D1T1 \*a28--\[a29\],a30
+[0-9a-f]+[048c] <[^>]*> 00fc1e24[ \t]+ldb \.D1T1 \*a31\+\+\[a0\],a1
+[0-9a-f]+[048c] <[^>]*> c7ffff2c[ \t]+\[a0\] ldb \.D2T1 \*\+b14\(32767\),a15
+[0-9a-f]+[048c] <[^>]*> 087fffae[ \t]+ldb \.D2T2 \*\+b15\(32767\),b16
+[0-9a-f]+[048c] <[^>]*> 03940214[ \t]+ldbu \.D1T1 \*\+a5\(0\),a7
+[0-9a-f]+[048c] <[^>]*> 65a43216[ \t]+\[b2\] ldbu \.D1T2 \*\+\+a9\(1\),b11
+[0-9a-f]+[048c] <[^>]*> 07b43094[ \t]+ldbu \.D2T1 \*--b13\(1\),a15
+[0-9a-f]+[048c] <[^>]*> b9c43696[ \t]+\[!a2\] ldbu \.D2T2 \*b17\+\+\(1\),b19
+[0-9a-f]+[048c] <[^>]*> 0bd43414[ \t]+ldbu \.D1T1 \*a21--\(1\),a23
+[0-9a-f]+[048c] <[^>]*> 7de7e096[ \t]+\[!b2\] ldbu \.D2T2 \*-b25\(31\),b27
+[0-9a-f]+[048c] <[^>]*> 0ff40214[ \t]+ldbu \.D1T1 \*\+a29\(0\),a31
+[0-9a-f]+[048c] <[^>]*> 01004014[ \t]+ldbu \.D1T1 \*-a0\(2\),a2
+[0-9a-f]+[048c] <[^>]*> 0310a814[ \t]+ldbu \.D1T1 \*-a4\[a5\],a6
+[0-9a-f]+[048c] <[^>]*> 049d0a14[ \t]+ldbu \.D1T1 \*\+a7\[a8\],a9
+[0-9a-f]+[048c] <[^>]*> 06297014[ \t]+ldbu \.D1T1 \*--a10\(11\),a12
+[0-9a-f]+[048c] <[^>]*> 07b5d214[ \t]+ldbu \.D1T1 \*\+\+a13\(14\),a15
+[0-9a-f]+[048c] <[^>]*> 09423414[ \t]+ldbu \.D1T1 \*a16--\(17\),a18
+[0-9a-f]+[048c] <[^>]*> 0ace9614[ \t]+ldbu \.D1T1 \*a19\+\+\(20\),a21
+[0-9a-f]+[048c] <[^>]*> 0c5af814[ \t]+ldbu \.D1T1 \*--a22\[a23\],a24
+[0-9a-f]+[048c] <[^>]*> 0de75a14[ \t]+ldbu \.D1T1 \*\+\+a25\[a26\],a27
+[0-9a-f]+[048c] <[^>]*> 0f73bc14[ \t]+ldbu \.D1T1 \*a28--\[a29\],a30
+[0-9a-f]+[048c] <[^>]*> 00fc1e14[ \t]+ldbu \.D1T1 \*a31\+\+\[a0\],a1
+[0-9a-f]+[048c] <[^>]*> c7ffff1c[ \t]+\[a0\] ldbu \.D2T1 \*\+b14\(32767\),a15
+[0-9a-f]+[048c] <[^>]*> 087fff9e[ \t]+ldbu \.D2T2 \*\+b15\(32767\),b16
+[0-9a-f]+[048c] <[^>]*> 03140364[ \t]+lddw \.D1T1 \*\+a5\(0\),a7:a6
+[0-9a-f]+[048c] <[^>]*> 65243366[ \t]+\[b2\] lddw \.D1T2 \*\+\+a9\(8\),b11:b10
+[0-9a-f]+[048c] <[^>]*> 073431e4[ \t]+lddw \.D2T1 \*--b13\(8\),a15:a14
+[0-9a-f]+[048c] <[^>]*> b94437e6[ \t]+\[!a2\] lddw \.D2T2 \*b17\+\+\(8\),b19:b18
+[0-9a-f]+[048c] <[^>]*> 0b543564[ \t]+lddw \.D1T1 \*a21--\(8\),a23:a22
+[0-9a-f]+[048c] <[^>]*> 7d67e1e6[ \t]+\[!b2\] lddw \.D2T2 \*-b25\(248\),b27:b26
+[0-9a-f]+[048c] <[^>]*> 0f740364[ \t]+lddw \.D1T1 \*\+a29\(0\),a31:a30
+[0-9a-f]+[048c] <[^>]*> 0103e164[ \t]+lddw \.D1T1 \*-a0\(248\),a3:a2
+[0-9a-f]+[048c] <[^>]*> 0310a964[ \t]+lddw \.D1T1 \*-a4\[a5\],a7:a6
+[0-9a-f]+[048c] <[^>]*> 041d0b64[ \t]+lddw \.D1T1 \*\+a7\[a8\],a9:a8
+[0-9a-f]+[048c] <[^>]*> 06297164[ \t]+lddw \.D1T1 \*--a10\(88\),a13:a12
+[0-9a-f]+[048c] <[^>]*> 07345364[ \t]+lddw \.D1T1 \*\+\+a13\(16\),a15:a14
+[0-9a-f]+[048c] <[^>]*> 09407564[ \t]+lddw \.D1T1 \*a16--\(24\),a19:a18
+[0-9a-f]+[048c] <[^>]*> 0a4c9764[ \t]+lddw \.D1T1 \*a19\+\+\(32\),a21:a20
+[0-9a-f]+[048c] <[^>]*> 0c5af964[ \t]+lddw \.D1T1 \*--a22\[a23\],a25:a24
+[0-9a-f]+[048c] <[^>]*> 0d675b64[ \t]+lddw \.D1T1 \*\+\+a25\[a26\],a27:a26
+[0-9a-f]+[048c] <[^>]*> 0f73bd64[ \t]+lddw \.D1T1 \*a28--\[a29\],a31:a30
+[0-9a-f]+[048c] <[^>]*> 007c1f64[ \t]+lddw \.D1T1 \*a31\+\+\[a0\],a1:a0
+[0-9a-f]+[048c] <[^>]*> 03940244[ \t]+ldh \.D1T1 \*\+a5\(0\),a7
+[0-9a-f]+[048c] <[^>]*> 65a43246[ \t]+\[b2\] ldh \.D1T2 \*\+\+a9\(2\),b11
+[0-9a-f]+[048c] <[^>]*> 07b430c4[ \t]+ldh \.D2T1 \*--b13\(2\),a15
+[0-9a-f]+[048c] <[^>]*> b9c436c6[ \t]+\[!a2\] ldh \.D2T2 \*b17\+\+\(2\),b19
+[0-9a-f]+[048c] <[^>]*> 0bd43444[ \t]+ldh \.D1T1 \*a21--\(2\),a23
+[0-9a-f]+[048c] <[^>]*> 7de7e0c6[ \t]+\[!b2\] ldh \.D2T2 \*-b25\(62\),b27
+[0-9a-f]+[048c] <[^>]*> 0ff40244[ \t]+ldh \.D1T1 \*\+a29\(0\),a31
+[0-9a-f]+[048c] <[^>]*> 0103e044[ \t]+ldh \.D1T1 \*-a0\(62\),a2
+[0-9a-f]+[048c] <[^>]*> 0310a844[ \t]+ldh \.D1T1 \*-a4\[a5\],a6
+[0-9a-f]+[048c] <[^>]*> 049d0a44[ \t]+ldh \.D1T1 \*\+a7\[a8\],a9
+[0-9a-f]+[048c] <[^>]*> 06297044[ \t]+ldh \.D1T1 \*--a10\(22\),a12
+[0-9a-f]+[048c] <[^>]*> 07b4f244[ \t]+ldh \.D1T1 \*\+\+a13\(14\),a15
+[0-9a-f]+[048c] <[^>]*> 09413444[ \t]+ldh \.D1T1 \*a16--\(18\),a18
+[0-9a-f]+[048c] <[^>]*> 0acd5644[ \t]+ldh \.D1T1 \*a19\+\+\(20\),a21
+[0-9a-f]+[048c] <[^>]*> 0c5af844[ \t]+ldh \.D1T1 \*--a22\[a23\],a24
+[0-9a-f]+[048c] <[^>]*> 0de75a44[ \t]+ldh \.D1T1 \*\+\+a25\[a26\],a27
+[0-9a-f]+[048c] <[^>]*> 0f73bc44[ \t]+ldh \.D1T1 \*a28--\[a29\],a30
+[0-9a-f]+[048c] <[^>]*> 00fc1e44[ \t]+ldh \.D1T1 \*a31\+\+\[a0\],a1
+[0-9a-f]+[048c] <[^>]*> c7ffff4c[ \t]+\[a0\] ldh \.D2T1 \*\+b14\(65534\),a15
+[0-9a-f]+[048c] <[^>]*> 087fffce[ \t]+ldh \.D2T2 \*\+b15\(65534\),b16
+[0-9a-f]+[048c] <[^>]*> 03940204[ \t]+ldhu \.D1T1 \*\+a5\(0\),a7
+[0-9a-f]+[048c] <[^>]*> 65a43206[ \t]+\[b2\] ldhu \.D1T2 \*\+\+a9\(2\),b11
+[0-9a-f]+[048c] <[^>]*> 07b43084[ \t]+ldhu \.D2T1 \*--b13\(2\),a15
+[0-9a-f]+[048c] <[^>]*> b9c43686[ \t]+\[!a2\] ldhu \.D2T2 \*b17\+\+\(2\),b19
+[0-9a-f]+[048c] <[^>]*> 0bd43404[ \t]+ldhu \.D1T1 \*a21--\(2\),a23
+[0-9a-f]+[048c] <[^>]*> 7de7e086[ \t]+\[!b2\] ldhu \.D2T2 \*-b25\(62\),b27
+[0-9a-f]+[048c] <[^>]*> 0ff40204[ \t]+ldhu \.D1T1 \*\+a29\(0\),a31
+[0-9a-f]+[048c] <[^>]*> 0103e004[ \t]+ldhu \.D1T1 \*-a0\(62\),a2
+[0-9a-f]+[048c] <[^>]*> 0310a804[ \t]+ldhu \.D1T1 \*-a4\[a5\],a6
+[0-9a-f]+[048c] <[^>]*> 049d0a04[ \t]+ldhu \.D1T1 \*\+a7\[a8\],a9
+[0-9a-f]+[048c] <[^>]*> 06297004[ \t]+ldhu \.D1T1 \*--a10\(22\),a12
+[0-9a-f]+[048c] <[^>]*> 07b4f204[ \t]+ldhu \.D1T1 \*\+\+a13\(14\),a15
+[0-9a-f]+[048c] <[^>]*> 09413404[ \t]+ldhu \.D1T1 \*a16--\(18\),a18
+[0-9a-f]+[048c] <[^>]*> 0acd5604[ \t]+ldhu \.D1T1 \*a19\+\+\(20\),a21
+[0-9a-f]+[048c] <[^>]*> 0c5af804[ \t]+ldhu \.D1T1 \*--a22\[a23\],a24
+[0-9a-f]+[048c] <[^>]*> 0de75a04[ \t]+ldhu \.D1T1 \*\+\+a25\[a26\],a27
+[0-9a-f]+[048c] <[^>]*> 0f73bc04[ \t]+ldhu \.D1T1 \*a28--\[a29\],a30
+[0-9a-f]+[048c] <[^>]*> 00fc1e04[ \t]+ldhu \.D1T1 \*a31\+\+\[a0\],a1
+[0-9a-f]+[048c] <[^>]*> c7ffff0c[ \t]+\[a0\] ldhu \.D2T1 \*\+b14\(65534\),a15
+[0-9a-f]+[048c] <[^>]*> 087fff8e[ \t]+ldhu \.D2T2 \*\+b15\(65534\),b16
+[0-9a-f]+[048c] <[^>]*> 03140324[ \t]+ldndw \.D1T1 \*\+a5\(0\),a7:a6
+[0-9a-f]+[048c] <[^>]*> 65a43326[ \t]+\[b2\] ldndw \.D1T2 \*\+\+a9\[1\],b11:b10
+[0-9a-f]+[048c] <[^>]*> 07b431a4[ \t]+ldndw \.D2T1 \*--b13\[1\],a15:a14
+[0-9a-f]+[048c] <[^>]*> b9c437a6[ \t]+\[!a2\] ldndw \.D2T2 \*b17\+\+\[1\],b19:b18
+[0-9a-f]+[048c] <[^>]*> 0bd43524[ \t]+ldndw \.D1T1 \*a21--\[1\],a23:a22
+[0-9a-f]+[048c] <[^>]*> 7de7e1a6[ \t]+\[!b2\] ldndw \.D2T2 \*-b25\[31\],b27:b26
+[0-9a-f]+[048c] <[^>]*> 0ff40324[ \t]+ldndw \.D1T1 \*\+a29\[0\],a31:a30
+[0-9a-f]+[048c] <[^>]*> 0103e124[ \t]+ldndw \.D1T1 \*-a0\(31\),a3:a2
+[0-9a-f]+[048c] <[^>]*> 0390a924[ \t]+ldndw \.D1T1 \*-a4\[a5\],a7:a6
+[0-9a-f]+[048c] <[^>]*> 041d0b24[ \t]+ldndw \.D1T1 \*\+a7\(a8\),a9:a8
+[0-9a-f]+[048c] <[^>]*> 06a97124[ \t]+ldndw \.D1T1 \*--a10\[11\],a13:a12
+[0-9a-f]+[048c] <[^>]*> 07361324[ \t]+ldndw \.D1T1 \*\+\+a13\(16\),a15:a14
+[0-9a-f]+[048c] <[^>]*> 09431524[ \t]+ldndw \.D1T1 \*a16--\(24\),a19:a18
+[0-9a-f]+[048c] <[^>]*> 0a4fd724[ \t]+ldndw \.D1T1 \*a19\+\+\(30\),a21:a20
+[0-9a-f]+[048c] <[^>]*> 0cdaf924[ \t]+ldndw \.D1T1 \*--a22\[a23\],a25:a24
+[0-9a-f]+[048c] <[^>]*> 0d675b24[ \t]+ldndw \.D1T1 \*\+\+a25\(a26\),a27:a26
+[0-9a-f]+[048c] <[^>]*> 0ff3bd24[ \t]+ldndw \.D1T1 \*a28--\[a29\],a31:a30
+[0-9a-f]+[048c] <[^>]*> 007c1f24[ \t]+ldndw \.D1T1 \*a31\+\+\(a0\),a1:a0
+[0-9a-f]+[048c] <[^>]*> 03940334[ \t]+ldnw \.D1T1 \*\+a5\(0\),a7
+[0-9a-f]+[048c] <[^>]*> 65a43336[ \t]+\[b2\] ldnw \.D1T2 \*\+\+a9\(4\),b11
+[0-9a-f]+[048c] <[^>]*> 07b431b4[ \t]+ldnw \.D2T1 \*--b13\(4\),a15
+[0-9a-f]+[048c] <[^>]*> b9c437b6[ \t]+\[!a2\] ldnw \.D2T2 \*b17\+\+\(4\),b19
+[0-9a-f]+[048c] <[^>]*> 0bd43534[ \t]+ldnw \.D1T1 \*a21--\(4\),a23
+[0-9a-f]+[048c] <[^>]*> 7de7e1b6[ \t]+\[!b2\] ldnw \.D2T2 \*-b25\(124\),b27
+[0-9a-f]+[048c] <[^>]*> 0ff40334[ \t]+ldnw \.D1T1 \*\+a29\(0\),a31
+[0-9a-f]+[048c] <[^>]*> 0103e134[ \t]+ldnw \.D1T1 \*-a0\(124\),a2
+[0-9a-f]+[048c] <[^>]*> 0310a934[ \t]+ldnw \.D1T1 \*-a4\[a5\],a6
+[0-9a-f]+[048c] <[^>]*> 049d0b34[ \t]+ldnw \.D1T1 \*\+a7\[a8\],a9
+[0-9a-f]+[048c] <[^>]*> 06297134[ \t]+ldnw \.D1T1 \*--a10\(44\),a12
+[0-9a-f]+[048c] <[^>]*> 07b49334[ \t]+ldnw \.D1T1 \*\+\+a13\(16\),a15
+[0-9a-f]+[048c] <[^>]*> 0940b534[ \t]+ldnw \.D1T1 \*a16--\(20\),a18
+[0-9a-f]+[048c] <[^>]*> 0accd734[ \t]+ldnw \.D1T1 \*a19\+\+\(24\),a21
+[0-9a-f]+[048c] <[^>]*> 0c5af934[ \t]+ldnw \.D1T1 \*--a22\[a23\],a24
+[0-9a-f]+[048c] <[^>]*> 0de75b34[ \t]+ldnw \.D1T1 \*\+\+a25\[a26\],a27
+[0-9a-f]+[048c] <[^>]*> 0f73bd34[ \t]+ldnw \.D1T1 \*a28--\[a29\],a30
+[0-9a-f]+[048c] <[^>]*> 00fc1f34[ \t]+ldnw \.D1T1 \*a31\+\+\[a0\],a1
+[0-9a-f]+[048c] <[^>]*> 03940264[ \t]+ldw \.D1T1 \*\+a5\(0\),a7
+[0-9a-f]+[048c] <[^>]*> 65a43266[ \t]+\[b2\] ldw \.D1T2 \*\+\+a9\(4\),b11
+[0-9a-f]+[048c] <[^>]*> 07b430e4[ \t]+ldw \.D2T1 \*--b13\(4\),a15
+[0-9a-f]+[048c] <[^>]*> b9c436e6[ \t]+\[!a2\] ldw \.D2T2 \*b17\+\+\(4\),b19
+[0-9a-f]+[048c] <[^>]*> 0bd43464[ \t]+ldw \.D1T1 \*a21--\(4\),a23
+[0-9a-f]+[048c] <[^>]*> 7de7e0e6[ \t]+\[!b2\] ldw \.D2T2 \*-b25\(124\),b27
+[0-9a-f]+[048c] <[^>]*> 0ff40264[ \t]+ldw \.D1T1 \*\+a29\(0\),a31
+[0-9a-f]+[048c] <[^>]*> 0103e064[ \t]+ldw \.D1T1 \*-a0\(124\),a2
+[0-9a-f]+[048c] <[^>]*> 0310a864[ \t]+ldw \.D1T1 \*-a4\[a5\],a6
+[0-9a-f]+[048c] <[^>]*> 049d0a64[ \t]+ldw \.D1T1 \*\+a7\[a8\],a9
+[0-9a-f]+[048c] <[^>]*> 06297064[ \t]+ldw \.D1T1 \*--a10\(44\),a12
+[0-9a-f]+[048c] <[^>]*> 07b49264[ \t]+ldw \.D1T1 \*\+\+a13\(16\),a15
+[0-9a-f]+[048c] <[^>]*> 0940b464[ \t]+ldw \.D1T1 \*a16--\(20\),a18
+[0-9a-f]+[048c] <[^>]*> 0accd664[ \t]+ldw \.D1T1 \*a19\+\+\(24\),a21
+[0-9a-f]+[048c] <[^>]*> 0c5af864[ \t]+ldw \.D1T1 \*--a22\[a23\],a24
+[0-9a-f]+[048c] <[^>]*> 0de75a64[ \t]+ldw \.D1T1 \*\+\+a25\[a26\],a27
+[0-9a-f]+[048c] <[^>]*> 0f73bc64[ \t]+ldw \.D1T1 \*a28--\[a29\],a30
+[0-9a-f]+[048c] <[^>]*> 00fc1e64[ \t]+ldw \.D1T1 \*a31\+\+\[a0\],a1
+[0-9a-f]+[048c] <[^>]*> c7ffff6c[ \t]+\[a0\] ldw \.D2T1 \*\+b14\(131068\),a15
+[0-9a-f]+[048c] <[^>]*> 087fffee[ \t]+ldw \.D2T2 \*\+b15\(131068\),b16
+[0-9a-f]+[048c] <[^>]*> 06a0ad78[ \t]+lmbd \.L1 a5,a8,a13
+[0-9a-f]+[048c] <[^>]*> 2b8abd78[ \t]+\[b0\] lmbd \.L1X a21,b2,a23
+[0-9a-f]+[048c] <[^>]*> d4c32d7a[ \t]+\[!a0\] lmbd \.L2 b25,b16,b9
+[0-9a-f]+[048c] <[^>]*> 01883d7a[ \t]+lmbd \.L2X b1,a2,b3
+[0-9a-f]+[048c] <[^>]*> 06a00d58[ \t]+lmbd \.L1 0,a8,a13
+[0-9a-f]+[048c] <[^>]*> 3b883d58[ \t]+\[!b0\] lmbd \.L1X 1,b2,a23
+[0-9a-f]+[048c] <[^>]*> 84c1ed5a[ \t]+\[a1\] lmbd \.L2 15,b16,b9
+[0-9a-f]+[048c] <[^>]*> 018a1d5a[ \t]+lmbd \.L2X -16,a2,b3
+[0-9a-f]+[048c] <[^>]*> 01882858[ \t]+max2 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 43149858[ \t]+\[b1\] max2 \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 94a0e85a[ \t]+\[!a1\] max2 \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d585a[ \t]+max2 \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01882f70[ \t]+max2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 53149f70[ \t]+\[!b1\] max2 \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 04a0ef72[ \t]+max2 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> a62d5f72[ \t]+\[a2\] max2 \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 67b9a878[ \t]+\[b2\] maxu4 \.L1 a13,a14,a15
+[0-9a-f]+[048c] <[^>]*> 09461878[ \t]+maxu4 \.L1X a16,b17,a18
+[0-9a-f]+[048c] <[^>]*> 0ad2687a[ \t]+maxu4 \.L2 b19,b20,b21
+[0-9a-f]+[048c] <[^>]*> bc5ed87a[ \t]+\[!a2\] maxu4 \.L2X b22,a23,b24
+[0-9a-f]+[048c] <[^>]*> 01882838[ \t]+min2 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 73149838[ \t]+\[!b2\] min2 \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> c4a0e83a[ \t]+\[a0\] min2 \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d583a[ \t]+min2 \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01882f30[ \t]+min2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 23149f30[ \t]+\[b0\] min2 \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 04a0ef32[ \t]+min2 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> d62d5f32[ \t]+\[!a0\] min2 \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 37b9a918[ \t]+\[!b0\] minu4 \.L1 a13,a14,a15
+[0-9a-f]+[048c] <[^>]*> 09461918[ \t]+minu4 \.L1X a16,b17,a18
+[0-9a-f]+[048c] <[^>]*> 0ad2691a[ \t]+minu4 \.L2 b19,b20,b21
+[0-9a-f]+[048c] <[^>]*> 8c5ed91a[ \t]+\[a1\] minu4 \.L2X b22,a23,b24
+[0-9a-f]+[048c] <[^>]*> 0deb2c80[ \t]+mpy \.M1 a25,a26,a27
+[0-9a-f]+[048c] <[^>]*> 4f779c80[ \t]+\[b1\] mpy \.M1X a28,b29,a30
+[0-9a-f]+[048c] <[^>]*> 9083ec82[ \t]+\[!a1\] mpy \.M2 b31,b0,b1
+[0-9a-f]+[048c] <[^>]*> 020c5c82[ \t]+mpy \.M2X b2,a3,b4
+[0-9a-f]+[048c] <[^>]*> 53160c00[ \t]+\[!b1\] mpy \.M1 -16,a5,a6
+[0-9a-f]+[048c] <[^>]*> 041dfc00[ \t]+mpy \.M1X 15,b7,a8
+[0-9a-f]+[048c] <[^>]*> 0524ac02[ \t]+mpy \.M2 5,b9,b10
+[0-9a-f]+[048c] <[^>]*> a62f9c02[ \t]+\[a2\] mpy \.M2X -4,a11,b12
+[0-9a-f]+[048c] <[^>]*> 02080700[ \t]+mpydp \.M1 a1:a0,a3:a2,a5:a4
+[0-9a-f]+[048c] <[^>]*> 6520c702[ \t]+\[b2\] mpydp \.M2 b7:b6,b9:b8,b11:b10
+[0-9a-f]+[048c] <[^>]*> 01040080[ \t]+mpyh \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> b2907080[ \t]+\[!a2\] mpyh \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 741cc082[ \t]+\[!b2\] mpyh \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93082[ \t]+mpyh \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040530[ \t]+mpyhi \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> c2107530[ \t]+\[a0\] mpyhi \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 241cc532[ \t]+\[b0\] mpyhi \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293532[ \t]+mpyhi \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 01040430[ \t]+mpyhir \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> d2907430[ \t]+\[!a0\] mpyhir \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 341cc432[ \t]+\[!b0\] mpyhir \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93432[ \t]+mpyhir \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040480[ \t]+mpyhl \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 82907480[ \t]+\[a1\] mpyhl \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 441cc482[ \t]+\[b1\] mpyhl \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93482[ \t]+mpyhl \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040780[ \t]+mpyhlu \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 92907780[ \t]+\[!a1\] mpyhlu \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 541cc782[ \t]+\[!b1\] mpyhlu \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93782[ \t]+mpyhlu \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040580[ \t]+mpyhslu \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> a2907580[ \t]+\[a2\] mpyhslu \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 641cc582[ \t]+\[b2\] mpyhslu \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93582[ \t]+mpyhslu \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040180[ \t]+mpyhsu \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> b2907180[ \t]+\[!a2\] mpyhsu \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 741cc182[ \t]+\[!b2\] mpyhsu \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93182[ \t]+mpyhsu \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040380[ \t]+mpyhu \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> c2907380[ \t]+\[a0\] mpyhu \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 241cc382[ \t]+\[b0\] mpyhu \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93382[ \t]+mpyhu \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040680[ \t]+mpyhuls \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> d2907680[ \t]+\[!a0\] mpyhuls \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 341cc682[ \t]+\[!b0\] mpyhuls \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93682[ \t]+mpyhuls \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040280[ \t]+mpyhus \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 82907280[ \t]+\[a1\] mpyhus \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 441cc282[ \t]+\[b1\] mpyhus \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93282[ \t]+mpyhus \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 91040200[ \t]+\[!a1\] mpyi \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 02907200[ \t]+mpyi \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 541cc202[ \t]+\[!b1\] mpyi \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93202[ \t]+mpyi \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> a1060300[ \t]+\[a2\] mpyi \.M1 -16,a1,a2
+[0-9a-f]+[048c] <[^>]*> 0291f300[ \t]+mpyi \.M1X 15,b4,a5
+[0-9a-f]+[048c] <[^>]*> 641ce302[ \t]+\[b2\] mpyi \.M2 7,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05ab5302[ \t]+mpyi \.M2X -6,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040400[ \t]+mpyid \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> b2107400[ \t]+\[!a2\] mpyid \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 741cc402[ \t]+\[!b2\] mpyid \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293402[ \t]+mpyid \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 01060600[ \t]+mpyid \.M1 -16,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> c2105600[ \t]+\[a0\] mpyid \.M1X 2,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 041de602[ \t]+mpyid \.M2 15,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 252b3602[ \t]+\[b0\] mpyid \.M2X -7,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 01002530[ \t]+mpyhi \.M1 a1,a0,a3:a2
+[0-9a-f]+[048c] <[^>]*> d2107530[ \t]+\[!a0\] mpyhi \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 3418e532[ \t]+\[!b0\] mpyhi \.M2 b7,b6,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293532[ \t]+mpyhi \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 81002430[ \t]+\[a1\] mpyhir \.M1 a1,a0,a2
+[0-9a-f]+[048c] <[^>]*> 02907430[ \t]+mpyhir \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 4418e432[ \t]+\[b1\] mpyhir \.M2 b7,b6,b8
+[0-9a-f]+[048c] <[^>]*> 05a93432[ \t]+mpyhir \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01002570[ \t]+mpyli \.M1 a1,a0,a3:a2
+[0-9a-f]+[048c] <[^>]*> 92107570[ \t]+\[!a1\] mpyli \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 0418e572[ \t]+mpyli \.M2 b7,b6,b9:b8
+[0-9a-f]+[048c] <[^>]*> 55293572[ \t]+\[!b1\] mpyli \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> a10023b0[ \t]+\[a2\] mpylir \.M1 a1,a0,a2
+[0-9a-f]+[048c] <[^>]*> 029073b0[ \t]+mpylir \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 0418e3b2[ \t]+mpylir \.M2 b7,b6,b8
+[0-9a-f]+[048c] <[^>]*> 65a933b2[ \t]+\[b2\] mpylir \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040880[ \t]+mpylh \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> b2907880[ \t]+\[!a2\] mpylh \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 741cc882[ \t]+\[!b2\] mpylh \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93882[ \t]+mpylh \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040b80[ \t]+mpylhu \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> c2907b80[ \t]+\[a0\] mpylhu \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 241ccb82[ \t]+\[b0\] mpylhu \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93b82[ \t]+mpylhu \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040570[ \t]+mpyli \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> d2107570[ \t]+\[!a0\] mpyli \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 341cc572[ \t]+\[!b0\] mpyli \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293572[ \t]+mpyli \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 010403b0[ \t]+mpylir \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 829073b0[ \t]+\[a1\] mpylir \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 041cc3b2[ \t]+mpylir \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 45a933b2[ \t]+\[b1\] mpylir \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 91040980[ \t]+\[!a1\] mpylshu \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 02907980[ \t]+mpylshu \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 041cc982[ \t]+mpylshu \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 55a93982[ \t]+\[!b1\] mpylshu \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040a80[ \t]+mpyluhs \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> a2907a80[ \t]+\[a2\] mpyluhs \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 041cca82[ \t]+mpyluhs \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 65a93a82[ \t]+\[b2\] mpyluhs \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040e00[ \t]+mpysp \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> b2907e00[ \t]+\[!a2\] mpysp \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 041cce02[ \t]+mpysp \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 75a93e02[ \t]+\[!b2\] mpysp \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> c83985b0[ \t]+\[a0\] mpyspdp \.M1 a12,a15:a14,a17:a16
+[0-9a-f]+[048c] <[^>]*> 0a4a55b0[ \t]+mpyspdp \.M1X a18,b19:b18,a21:a20
+[0-9a-f]+[048c] <[^>]*> 0d62c5b2[ \t]+mpyspdp \.M2 b22,b25:b24,b27:b26
+[0-9a-f]+[048c] <[^>]*> 207bb5b2[ \t]+\[b0\] mpyspdp \.M2X b29,a31:a30,b1:b0
+[0-9a-f]+[048c] <[^>]*> 010405f0[ \t]+mpysp2dp \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> d21075f0[ \t]+\[!a0\] mpysp2dp \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 341cc5f2[ \t]+\[!b0\] mpysp2dp \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 052935f2[ \t]+mpysp2dp \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 81040d80[ \t]+\[a1\] mpysu \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 02907d80[ \t]+mpysu \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 441ccd82[ \t]+\[b1\] mpysu \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 05a93d82[ \t]+mpysu \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 91060f00[ \t]+\[!a1\] mpysu \.M1 -16,a1,a2
+[0-9a-f]+[048c] <[^>]*> 0291ff00[ \t]+mpysu \.M1X 15,b4,a5
+[0-9a-f]+[048c] <[^>]*> 041c6f02[ \t]+mpysu \.M2 3,b7,b8
+[0-9a-f]+[048c] <[^>]*> 55aaff02[ \t]+\[!b1\] mpysu \.M2X -9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040170[ \t]+mpysu4 \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> d2107170[ \t]+\[!a0\] mpysu4 \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 341cc172[ \t]+\[!b0\] mpysu4 \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293172[ \t]+mpysu4 \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 81040f80[ \t]+\[a1\] mpyu \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 02907f80[ \t]+mpyu \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 041ccf82[ \t]+mpyu \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 45a93f82[ \t]+\[b1\] mpyu \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040130[ \t]+mpyu4 \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 92107130[ \t]+\[!a1\] mpyu4 \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 541cc132[ \t]+\[!b1\] mpyu4 \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293132[ \t]+mpyu4 \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> a1040e80[ \t]+\[a2\] mpyus \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 02907e80[ \t]+mpyus \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 041cce82[ \t]+mpyus \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 65a93e82[ \t]+\[b2\] mpyus \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01002170[ \t]+mpysu4 \.M1 a1,a0,a3:a2
+[0-9a-f]+[048c] <[^>]*> b2107170[ \t]+\[!a2\] mpysu4 \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 7418e172[ \t]+\[!b2\] mpysu4 \.M2 b7,b6,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293172[ \t]+mpysu4 \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 01040030[ \t]+mpy2 \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> c2107030[ \t]+\[a0\] mpy2 \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 241cc032[ \t]+\[b0\] mpy2 \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293032[ \t]+mpy2 \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 110403f0[ \t]+mpy2ir \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 121073f0[ \t]+mpy2ir \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 141cc3f2[ \t]+mpy2ir \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 152933f2[ \t]+mpy2ir \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> d1040800[ \t]+\[!a0\] mpy32 \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 02907800[ \t]+mpy32 \.M1X a3,b4,a5
+[0-9a-f]+[048c] <[^>]*> 041cc802[ \t]+mpy32 \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> 35a93802[ \t]+\[!b0\] mpy32 \.M2X b9,a10,b11
+[0-9a-f]+[048c] <[^>]*> 01040a00[ \t]+mpy32 \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 82107a00[ \t]+\[a1\] mpy32 \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 441cca02[ \t]+\[b1\] mpy32 \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293a02[ \t]+mpy32 \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 01040b00[ \t]+mpy32su \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 92107b00[ \t]+\[!a1\] mpy32su \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 541ccb02[ \t]+\[!b1\] mpy32su \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293b02[ \t]+mpy32su \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 01040630[ \t]+mpy32u \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> a2107630[ \t]+\[a2\] mpy32u \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 641cc632[ \t]+\[b2\] mpy32u \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293632[ \t]+mpy32u \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> 01040670[ \t]+mpy32us \.M1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> b2107670[ \t]+\[!a2\] mpy32us \.M1X a3,b4,a5:a4
+[0-9a-f]+[048c] <[^>]*> 741cc672[ \t]+\[!b2\] mpy32us \.M2 b6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 05293672[ \t]+mpy32us \.M2X b9,a10,b11:b10
+[0-9a-f]+[048c] <[^>]*> c3940fd8[ \t]+\[a0\] or \.L1 0,a5,a7
+[0-9a-f]+[048c] <[^>]*> 06a01fd8[ \t]+or \.L1X 0,b8,a13
+[0-9a-f]+[048c] <[^>]*> 27b00fda[ \t]+\[b0\] or \.L2 0,b12,b15
+[0-9a-f]+[048c] <[^>]*> 09c41fda[ \t]+or \.L2X 0,a17,b19
+[0-9a-f]+[048c] <[^>]*> d39406a0[ \t]+\[!a0\] or \.S1 0,a5,a7
+[0-9a-f]+[048c] <[^>]*> 06a016a0[ \t]+or \.S1X 0,b8,a13
+[0-9a-f]+[048c] <[^>]*> 07b006a2[ \t]+or \.S2 0,b12,b15
+[0-9a-f]+[048c] <[^>]*> 39c416a2[ \t]+\[!b0\] or \.S2X 0,a17,b19
+[0-9a-f]+[048c] <[^>]*> 839408f0[ \t]+\[a1\] or \.D1 0,a5,a7
+[0-9a-f]+[048c] <[^>]*> 06a018f0[ \t]+or \.D1X 0,b8,a13
+[0-9a-f]+[048c] <[^>]*> 47b008f2[ \t]+\[b1\] or \.D2 0,b12,b15
+[0-9a-f]+[048c] <[^>]*> 09c418f2[ \t]+or \.D2X 0,a17,b19
+[0-9a-f]+[048c] <[^>]*> c28003e2[ \t]+\[a0\] mvc \.S2 amr,b5
+[0-9a-f]+[048c] <[^>]*> 001803a2[ \t]+mvc \.S2 b6,amr
+[0-9a-f]+[048c] <[^>]*> 201c13a2[ \t]+\[b0\] mvc \.S2X a7,amr
+[0-9a-f]+[048c] <[^>]*> 040403e2[ \t]+mvc \.S2 csr,b8
+[0-9a-f]+[048c] <[^>]*> 00a003a2[ \t]+mvc \.S2 b8,csr
+[0-9a-f]+[048c] <[^>]*> 04c403e2[ \t]+mvc \.S2 dnum,b9
+[0-9a-f]+[048c] <[^>]*> 0ea803a2[ \t]+mvc \.S2 b10,ecr
+[0-9a-f]+[048c] <[^>]*> 05f403e2[ \t]+mvc \.S2 efr,b11
+[0-9a-f]+[048c] <[^>]*> 064803e2[ \t]+mvc \.S2 fadcr,b12
+[0-9a-f]+[048c] <[^>]*> 093403a2[ \t]+mvc \.S2 b13,fadcr
+[0-9a-f]+[048c] <[^>]*> 074c03e2[ \t]+mvc \.S2 faucr,b14
+[0-9a-f]+[048c] <[^>]*> 09bc03a2[ \t]+mvc \.S2 b15,faucr
+[0-9a-f]+[048c] <[^>]*> 085003e2[ \t]+mvc \.S2 fmcr,b16
+[0-9a-f]+[048c] <[^>]*> 0a4403a2[ \t]+mvc \.S2 b17,fmcr
+[0-9a-f]+[048c] <[^>]*> 096003e2[ \t]+mvc \.S2 gfpgfr,b18
+[0-9a-f]+[048c] <[^>]*> 0c4c03a2[ \t]+mvc \.S2 b19,gfpgfr
+[0-9a-f]+[048c] <[^>]*> 0a5803e2[ \t]+mvc \.S2 gplya,b20
+[0-9a-f]+[048c] <[^>]*> 0b5403a2[ \t]+mvc \.S2 b21,gplya
+[0-9a-f]+[048c] <[^>]*> 0b5c03e2[ \t]+mvc \.S2 gplyb,b22
+[0-9a-f]+[048c] <[^>]*> 0bdc03a2[ \t]+mvc \.S2 b23,gplyb
+[0-9a-f]+[048c] <[^>]*> 01e003a2[ \t]+mvc \.S2 b24,icr
+[0-9a-f]+[048c] <[^>]*> 0c9003e2[ \t]+mvc \.S2 ier,b25
+[0-9a-f]+[048c] <[^>]*> 026803a2[ \t]+mvc \.S2 b26,ier
+[0-9a-f]+[048c] <[^>]*> 0dfc03e2[ \t]+mvc \.S2 ierr,b27
+[0-9a-f]+[048c] <[^>]*> 0ff003a2[ \t]+mvc \.S2 b28,ierr
+[0-9a-f]+[048c] <[^>]*> 0e8803e2[ \t]+mvc \.S2 ifr,b29
+[0-9a-f]+[048c] <[^>]*> 0f3403e2[ \t]+mvc \.S2 ilc,b30
+[0-9a-f]+[048c] <[^>]*> 06fc03a2[ \t]+mvc \.S2 b31,ilc
+[0-9a-f]+[048c] <[^>]*> 001803e2[ \t]+mvc \.S2 irp,b0
+[0-9a-f]+[048c] <[^>]*> 030403a2[ \t]+mvc \.S2 b1,irp
+[0-9a-f]+[048c] <[^>]*> 010803a2[ \t]+mvc \.S2 b2,isr
+[0-9a-f]+[048c] <[^>]*> 019403e2[ \t]+mvc \.S2 istp,b3
+[0-9a-f]+[048c] <[^>]*> 029003a2[ \t]+mvc \.S2 b4,istp
+[0-9a-f]+[048c] <[^>]*> 02ec03e2[ \t]+mvc \.S2 itsr,b5
+[0-9a-f]+[048c] <[^>]*> 0d9803a2[ \t]+mvc \.S2 b6,itsr
+[0-9a-f]+[048c] <[^>]*> 039c03e2[ \t]+mvc \.S2 nrp,b7
+[0-9a-f]+[048c] <[^>]*> 03a003a2[ \t]+mvc \.S2 b8,nrp
+[0-9a-f]+[048c] <[^>]*> 04f003e2[ \t]+mvc \.S2 ntsr,b9
+[0-9a-f]+[048c] <[^>]*> 0e2803a2[ \t]+mvc \.S2 b10,ntsr
+[0-9a-f]+[048c] <[^>]*> 05c003e2[ \t]+mvc \.S2 pce1,b11
+[0-9a-f]+[048c] <[^>]*> 063c03e2[ \t]+mvc \.S2 rep,b12
+[0-9a-f]+[048c] <[^>]*> 07b403a2[ \t]+mvc \.S2 b13,rep
+[0-9a-f]+[048c] <[^>]*> 073803e2[ \t]+mvc \.S2 rilc,b14
+[0-9a-f]+[048c] <[^>]*> 073c03a2[ \t]+mvc \.S2 b15,rilc
+[0-9a-f]+[048c] <[^>]*> 085403e2[ \t]+mvc \.S2 ssr,b16
+[0-9a-f]+[048c] <[^>]*> 0ac403a2[ \t]+mvc \.S2 b17,ssr
+[0-9a-f]+[048c] <[^>]*> 092c03e2[ \t]+mvc \.S2 tsch,b18
+[0-9a-f]+[048c] <[^>]*> 09a803e2[ \t]+mvc \.S2 tscl,b19
+[0-9a-f]+[048c] <[^>]*> 0a6803e2[ \t]+mvc \.S2 tsr,b20
+[0-9a-f]+[048c] <[^>]*> 0d5403a2[ \t]+mvc \.S2 b21,tsr
+[0-9a-f]+[048c] <[^>]*> 0001e3e2[ \t]+mvc \.S2 amr,b0
+[0-9a-f]+[048c] <[^>]*> 0005e3e2[ \t]+mvc \.S2 csr,b0
+[0-9a-f]+[048c] <[^>]*> 0181e3a2[ \t]+mvc \.S2 b0,icr
+[0-9a-f]+[048c] <[^>]*> 0201e3a2[ \t]+mvc \.S2 b0,ier
+[0-9a-f]+[048c] <[^>]*> 0301e3a2[ \t]+mvc \.S2 b0,irp
+[0-9a-f]+[048c] <[^>]*> 0101e3a2[ \t]+mvc \.S2 b0,isr
+[0-9a-f]+[048c] <[^>]*> 0281e3a2[ \t]+mvc \.S2 b0,istp
+[0-9a-f]+[048c] <[^>]*> 0381e3a2[ \t]+mvc \.S2 b0,nrp
+[0-9a-f]+[048c] <[^>]*> 004203e2[ \t]+mvc \.S2 pce1,b0
+[0-9a-f]+[048c] <[^>]*> 029340f0[ \t]+mvd \.M1 a4,a5
+[0-9a-f]+[048c] <[^>]*> d39b50f0[ \t]+\[!a0\] mvd \.M1X b6,a7
+[0-9a-f]+[048c] <[^>]*> 34a340f2[ \t]+\[!b0\] mvd \.M2 b8,b9
+[0-9a-f]+[048c] <[^>]*> 05ab50f2[ \t]+mvd \.M2X a10,b11
+[0-9a-f]+[048c] <[^>]*> 52c00028[ \t]+\[!b1\] mvk \.S1 -32768,a5
+[0-9a-f]+[048c] <[^>]*> 023fffaa[ \t]+mvk \.S2 32767,b4
+[0-9a-f]+[048c] <[^>]*> 0240a358[ \t]+mvk \.L1 -16,a4
+[0-9a-f]+[048c] <[^>]*> 823ca35a[ \t]+\[a1\] mvk \.L2 15,b4
+[0-9a-f]+[048c] <[^>]*> 4200c040[ \t]+\[b1\] mvk \.D1 6,a4
+[0-9a-f]+[048c] <[^>]*> 0602e042[ \t]+mvk \.D2 -9,b12
+[0-9a-f]+[048c] <[^>]*> 03091a68[ \t]+mvkh \.S1 305397760,a6
+[0-9a-f]+[048c] <[^>]*> a3ff6e6a[ \t]+\[a2\] mvkh \.S2 4275830784,b7
+[0-9a-f]+[048c] <[^>]*> 632b3c68[ \t]+\[b2\] mvkh \.S1 1450704896,a6
+[0-9a-f]+[048c] <[^>]*> 03dd4c6a[ \t]+mvkh \.S2 3130523648,b7
+[0-9a-f]+[048c] <[^>]*> 032b3c28[ \t]+mvk \.S1 22136,a6
+[0-9a-f]+[048c] <[^>]*> b3dd4c2a[ \t]+\[!a2\] mvk \.S2 -17768,b7
+[0-9a-f]+[048c] <[^>]*> 031405a0[ \t]+sub \.S1 0,a5,a6
+[0-9a-f]+[048c] <[^>]*> c41c15a0[ \t]+\[a0\] sub \.S1X 0,b7,a8
+[0-9a-f]+[048c] <[^>]*> 252405a2[ \t]+\[b0\] sub \.S2 0,b9,b10
+[0-9a-f]+[048c] <[^>]*> 062c15a2[ \t]+sub \.S2X 0,a11,b12
+[0-9a-f]+[048c] <[^>]*> d73400d8[ \t]+\[!a0\] sub \.L1 0,a13,a14
+[0-9a-f]+[048c] <[^>]*> 083c10d8[ \t]+sub \.L1X 0,b15,a16
+[0-9a-f]+[048c] <[^>]*> 094400da[ \t]+sub \.L2 0,b17,b18
+[0-9a-f]+[048c] <[^>]*> 3a4c10da[ \t]+\[!b0\] sub \.L2X 0,a19,b20
+[0-9a-f]+[048c] <[^>]*> 4b500498[ \t]+\[b1\] sub \.L1 0,a21:a20,a23:a22
+[0-9a-f]+[048c] <[^>]*> 0d60049a[ \t]+sub \.L2 0,b25:b24,b27:b26
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 00002000[ \t]+nop 2
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 00004000[ \t]+nop 3
+[0-9a-f]+[048c] <[^>]*> 00006000[ \t]+nop 4
+[0-9a-f]+[048c] <[^>]*> 00008000[ \t]+nop 5
+[0-9a-f]+[048c] <[^>]*> 0000a000[ \t]+nop 6
+[0-9a-f]+[048c] <[^>]*> 0000c000[ \t]+nop 7
+[0-9a-f]+[048c] <[^>]*> 0000e000[ \t]+nop 8
+[0-9a-f]+[048c] <[^>]*> 00010000[ \t]+nop 9
+[0-9a-f]+[048c] <[^>]*> 72900c78[ \t]+\[!b2\] norm \.L1 a4,a5
+[0-9a-f]+[048c] <[^>]*> 03981c78[ \t]+norm \.L1X b6,a7
+[0-9a-f]+[048c] <[^>]*> 04a00c7a[ \t]+norm \.L2 b8,b9
+[0-9a-f]+[048c] <[^>]*> c5a81c7a[ \t]+\[a0\] norm \.L2X a10,b11
+[0-9a-f]+[048c] <[^>]*> 03100c18[ \t]+norm \.L1 a5:a4,a6
+[0-9a-f]+[048c] <[^>]*> 25200c1a[ \t]+\[b0\] norm \.L2 b9:b8,b10
+[0-9a-f]+[048c] <[^>]*> 0107edd8[ \t]+xor \.L1 -1,a1,a2
+[0-9a-f]+[048c] <[^>]*> 620ffdd8[ \t]+\[b2\] xor \.L1X -1,b3,a4
+[0-9a-f]+[048c] <[^>]*> b317edda[ \t]+\[!a2\] xor \.L2 -1,b5,b6
+[0-9a-f]+[048c] <[^>]*> 041ffdda[ \t]+xor \.L2X -1,a7,b8
+[0-9a-f]+[048c] <[^>]*> 7107e2a0[ \t]+\[!b2\] xor \.S1 -1,a1,a2
+[0-9a-f]+[048c] <[^>]*> 020ff2a0[ \t]+xor \.S1X -1,b3,a4
+[0-9a-f]+[048c] <[^>]*> 0317e2a2[ \t]+xor \.S2 -1,b5,b6
+[0-9a-f]+[048c] <[^>]*> c41ff2a2[ \t]+\[a0\] xor \.S2X -1,a7,b8
+[0-9a-f]+[048c] <[^>]*> 2107ebf0[ \t]+\[b0\] xor \.D1 -1,a1,a2
+[0-9a-f]+[048c] <[^>]*> 020ffbf0[ \t]+xor \.D1X -1,b3,a4
+[0-9a-f]+[048c] <[^>]*> 0317ebf2[ \t]+xor \.D2 -1,b5,b6
+[0-9a-f]+[048c] <[^>]*> d41ffbf2[ \t]+\[!a0\] xor \.D2X -1,a7,b8
+[0-9a-f]+[048c] <[^>]*> d18828b0[ \t]+\[!a0\] or \.D1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 031498b0[ \t]+or \.D1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 04a0e8b2[ \t]+or \.D2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 362d58b2[ \t]+\[!b0\] or \.D2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 018a08f0[ \t]+or \.D1 -16,a2,a3
+[0-9a-f]+[048c] <[^>]*> 831578f0[ \t]+\[a1\] or \.D1X 11,b5,a6
+[0-9a-f]+[048c] <[^>]*> 44a1e8f2[ \t]+\[b1\] or \.D2 15,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062e78f2[ \t]+or \.D2X -13,a11,b12
+[0-9a-f]+[048c] <[^>]*> 91882ff8[ \t]+\[!a1\] or \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 03149ff8[ \t]+or \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 04a0effa[ \t]+or \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 562d5ffa[ \t]+\[!b1\] or \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 018a0fd8[ \t]+or \.L1 -16,a2,a3
+[0-9a-f]+[048c] <[^>]*> a3157fd8[ \t]+\[a2\] or \.L1X 11,b5,a6
+[0-9a-f]+[048c] <[^>]*> 64a1efda[ \t]+\[b2\] or \.L2 15,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062e7fda[ \t]+or \.L2X -13,a11,b12
+[0-9a-f]+[048c] <[^>]*> b18826e0[ \t]+\[!a2\] or \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 031496e0[ \t]+or \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 04a0e6e2[ \t]+or \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 762d56e2[ \t]+\[!b2\] or \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 018a06a0[ \t]+or \.S1 -16,a2,a3
+[0-9a-f]+[048c] <[^>]*> c31576a0[ \t]+\[a0\] or \.S1X 11,b5,a6
+[0-9a-f]+[048c] <[^>]*> 24a1e6a2[ \t]+\[b0\] or \.S2 15,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062e76a2[ \t]+or \.S2X -13,a11,b12
+[0-9a-f]+[048c] <[^>]*> d1882018[ \t]+\[!a0\] pack2 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 06a0b018[ \t]+pack2 \.L1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 0b8aa01a[ \t]+pack2 \.L2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 34c3301a[ \t]+\[!b0\] pack2 \.L2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> 81882ff0[ \t]+\[a1\] pack2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 06a0bff0[ \t]+pack2 \.S1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 0b8aaff2[ \t]+pack2 \.S2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 44c33ff2[ \t]+\[b1\] pack2 \.S2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> 918823d8[ \t]+\[!a1\] packh2 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 06a0b3d8[ \t]+packh2 \.L1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 0b8aa3da[ \t]+packh2 \.L2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 54c333da[ \t]+\[!b1\] packh2 \.L2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> a1882260[ \t]+\[a2\] packh2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 06a0b260[ \t]+packh2 \.S1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 0b8aa262[ \t]+packh2 \.S2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 64c33262[ \t]+\[b2\] packh2 \.S2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> b1882d38[ \t]+\[!a2\] packh4 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 06a0bd38[ \t]+packh4 \.L1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 0b8aad3a[ \t]+packh4 \.L2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 74c33d3a[ \t]+\[!b2\] packh4 \.L2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> c1882398[ \t]+\[a0\] packhl2 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 06a0b398[ \t]+packhl2 \.L1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 0b8aa39a[ \t]+packhl2 \.L2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 24c3339a[ \t]+\[b0\] packhl2 \.L2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> 01882220[ \t]+packhl2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> d6a0b220[ \t]+\[!a0\] packhl2 \.S1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 3b8aa222[ \t]+\[!b0\] packhl2 \.S2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 04c33222[ \t]+packhl2 \.S2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> 81882378[ \t]+\[a1\] packlh2 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 06a0b378[ \t]+packlh2 \.L1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 0b8aa37a[ \t]+packlh2 \.L2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 44c3337a[ \t]+\[b1\] packlh2 \.L2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> 01882420[ \t]+packlh2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 96a0b420[ \t]+\[!a1\] packlh2 \.S1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 5b8aa422[ \t]+\[!b1\] packlh2 \.S2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 04c33422[ \t]+packlh2 \.S2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> a1882d18[ \t]+\[a2\] packl4 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 06a0bd18[ \t]+packl4 \.L1X a5,b8,a13
+[0-9a-f]+[048c] <[^>]*> 0b8aad1a[ \t]+packl4 \.L2 b21,b2,b23
+[0-9a-f]+[048c] <[^>]*> 64c33d1a[ \t]+\[b2\] packl4 \.L2X b25,a16,b9
+[0-9a-f]+[048c] <[^>]*> 03100b60[ \t]+rcpdp \.S1 a5:a4,a7:a6
+[0-9a-f]+[048c] <[^>]*> b5200b62[ \t]+\[!a2\] rcpdp \.S2 b9:b8,b11:b10
+[0-9a-f]+[048c] <[^>]*> 00800f60[ \t]+rcpsp \.S1 a0,a1
+[0-9a-f]+[048c] <[^>]*> 71881f60[ \t]+\[!b2\] rcpsp \.S1X b2,a3
+[0-9a-f]+[048c] <[^>]*> c2900f62[ \t]+\[a0\] rcpsp \.S2 b4,b5
+[0-9a-f]+[048c] <[^>]*> 03981f62[ \t]+rcpsp \.S2X a6,b7
+[0-9a-f]+[048c] <[^>]*> 10006000[ \t]+rint
+[0-9a-f]+[048c] <[^>]*> 21002770[ \t]+\[b0\] rotl \.M1 a0,a1,a2
+[0-9a-f]+[048c] <[^>]*> 028c9770[ \t]+rotl \.M1X b3,a4,a5
+[0-9a-f]+[048c] <[^>]*> 0418e772[ \t]+rotl \.M2 b6,b7,b8
+[0-9a-f]+[048c] <[^>]*> d5a55772[ \t]+\[!a0\] rotl \.M2X a9,b10,b11
+[0-9a-f]+[048c] <[^>]*> 06b007b0[ \t]+rotl \.M1 a12,0,a13
+[0-9a-f]+[048c] <[^>]*> 37bbf7b0[ \t]+\[!b0\] rotl \.M1X b14,31,a15
+[0-9a-f]+[048c] <[^>]*> 88c227b2[ \t]+\[a1\] rotl \.M2 b16,17,b17
+[0-9a-f]+[048c] <[^>]*> 09cb37b2[ \t]+rotl \.M2X a18,25,b19
+[0-9a-f]+[048c] <[^>]*> 11882ef0[ \t]+rpack2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 13149ef0[ \t]+rpack2 \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 14a0eef2[ \t]+rpack2 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 162d5ef2[ \t]+rpack2 \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 03100ba0[ \t]+rsqrdp \.S1 a5:a4,a7:a6
+[0-9a-f]+[048c] <[^>]*> 45200ba2[ \t]+\[b1\] rsqrdp \.S2 b9:b8,b11:b10
+[0-9a-f]+[048c] <[^>]*> 00800fa0[ \t]+rsqrsp \.S1 a0,a1
+[0-9a-f]+[048c] <[^>]*> 91881fa0[ \t]+\[!a1\] rsqrsp \.S1X b2,a3
+[0-9a-f]+[048c] <[^>]*> 52900fa2[ \t]+\[!b1\] rsqrsp \.S2 b4,b5
+[0-9a-f]+[048c] <[^>]*> 03981fa2[ \t]+rsqrsp \.S2X a6,b7
+[0-9a-f]+[048c] <[^>]*> 01882278[ \t]+sadd \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> a3149278[ \t]+\[a2\] sadd \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 64a0e27a[ \t]+\[b2\] sadd \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d527a[ \t]+sadd \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> b839a638[ \t]+\[!a2\] sadd \.L1 a13,a15:a14,a17:a16
+[0-9a-f]+[048c] <[^>]*> 0b525638[ \t]+sadd \.L1X b18,a21:a20,a23:a22
+[0-9a-f]+[048c] <[^>]*> 0e6b063a[ \t]+sadd \.L2 b24,b27:b26,b29:b28
+[0-9a-f]+[048c] <[^>]*> 7103d63a[ \t]+\[!b2\] sadd \.L2X a30,b1:b0,b3:b2
+[0-9a-f]+[048c] <[^>]*> 02920258[ \t]+sadd \.L1 -16,a4,a5
+[0-9a-f]+[048c] <[^>]*> c399f258[ \t]+\[a0\] sadd \.L1X 15,b6,a7
+[0-9a-f]+[048c] <[^>]*> 24a1825a[ \t]+\[b0\] sadd \.L2 12,b8,b9
+[0-9a-f]+[048c] <[^>]*> 05aab25a[ \t]+sadd \.L2X -11,a10,b11
+[0-9a-f]+[048c] <[^>]*> 07320618[ \t]+sadd \.L1 -16,a13:a12,a15:a14
+[0-9a-f]+[048c] <[^>]*> db51e61a[ \t]+\[!a0\] sadd \.L2 15,b21:b20,b23:b22
+[0-9a-f]+[048c] <[^>]*> 3f778820[ \t]+\[!b0\] sadd \.S1 a28,a29,a30
+[0-9a-f]+[048c] <[^>]*> 0083f820[ \t]+sadd \.S1X a31,b0,a1
+[0-9a-f]+[048c] <[^>]*> 020c4822[ \t]+sadd \.S2 b2,b3,b4
+[0-9a-f]+[048c] <[^>]*> 8398b822[ \t]+\[a1\] sadd \.S2X b5,a6,b7
+[0-9a-f]+[048c] <[^>]*> 01882c30[ \t]+sadd2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 43149c30[ \t]+\[b1\] sadd2 \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 94a0ec32[ \t]+\[!a1\] sadd2 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5c32[ \t]+sadd2 \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 110401d8[ \t]+saddsub \.L1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 131491d8[ \t]+saddsub \.L1X a4,b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 152501da[ \t]+saddsub \.L2 b8,b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 173591da[ \t]+saddsub \.L2X b12,a13,b15:b14
+[0-9a-f]+[048c] <[^>]*> 110401f8[ \t]+saddsub2 \.L1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 131491f8[ \t]+saddsub2 \.L1X a4,b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 152501fa[ \t]+saddsub2 \.L2 b8,b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 173591fa[ \t]+saddsub2 \.L2X b12,a13,b15:b14
+[0-9a-f]+[048c] <[^>]*> 59422c70[ \t]+\[!b1\] saddus2 \.S1 a17,a16,a18
+[0-9a-f]+[048c] <[^>]*> 0ace9c70[ \t]+saddus2 \.S1X a20,b19,a21
+[0-9a-f]+[048c] <[^>]*> 0c5aec72[ \t]+saddus2 \.S2 b23,b22,b24
+[0-9a-f]+[048c] <[^>]*> ade75c72[ \t]+\[a2\] saddus2 \.S2X b26,a25,b27
+[0-9a-f]+[048c] <[^>]*> 0f778c70[ \t]+saddus2 \.S1 a28,a29,a30
+[0-9a-f]+[048c] <[^>]*> 6083fc70[ \t]+\[b2\] saddus2 \.S1X a31,b0,a1
+[0-9a-f]+[048c] <[^>]*> b20c4c72[ \t]+\[!a2\] saddus2 \.S2 b2,b3,b4
+[0-9a-f]+[048c] <[^>]*> 0398bc72[ \t]+saddus2 \.S2X b5,a6,b7
+[0-9a-f]+[048c] <[^>]*> 0f778cf0[ \t]+saddu4 \.S1 a28,a29,a30
+[0-9a-f]+[048c] <[^>]*> 7083fcf0[ \t]+\[!b2\] saddu4 \.S1X a31,b0,a1
+[0-9a-f]+[048c] <[^>]*> c20c4cf2[ \t]+\[a0\] saddu4 \.S2 b2,b3,b4
+[0-9a-f]+[048c] <[^>]*> 0398bcf2[ \t]+saddu4 \.S2X b5,a6,b7
+[0-9a-f]+[048c] <[^>]*> 2a080818[ \t]+\[b0\] sat \.L1 a3:a2,a20
+[0-9a-f]+[048c] <[^>]*> 0798081a[ \t]+sat \.L2 b7:b6,b15
+[0-9a-f]+[048c] <[^>]*> 0107e088[ \t]+set \.S1 a1,31,0,a2
+[0-9a-f]+[048c] <[^>]*> d20c1f8a[ \t]+\[!a0\] set \.S2 b3,0,31,b4
+[0-9a-f]+[048c] <[^>]*> 0394cee0[ \t]+set \.S1 a5,a6,a7
+[0-9a-f]+[048c] <[^>]*> 35213ee0[ \t]+\[!b0\] set \.S1X b8,a9,a10
+[0-9a-f]+[048c] <[^>]*> 86ad8ee2[ \t]+\[a1\] set \.S2 b11,b12,b13
+[0-9a-f]+[048c] <[^>]*> 0839fee2[ \t]+set \.S2X a14,b15,b16
+[0-9a-f]+[048c] <[^>]*> 094780f0[ \t]+shfl \.M1 a17,a18
+[0-9a-f]+[048c] <[^>]*> 4a4f90f0[ \t]+\[b1\] shfl \.M1X b19,a20
+[0-9a-f]+[048c] <[^>]*> 9b5780f2[ \t]+\[!a1\] shfl \.M2 b21,b22
+[0-9a-f]+[048c] <[^>]*> 0c5f90f2[ \t]+shfl \.M2X a23,b24
+[0-9a-f]+[048c] <[^>]*> 110406d8[ \t]+shfl3 \.L1 a0,a1,a3:a2
+[0-9a-f]+[048c] <[^>]*> 131496d8[ \t]+shfl3 \.L1X a4,b5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 152506da[ \t]+shfl3 \.L2 b8,b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 173596da[ \t]+shfl3 \.L2X b12,a13,b15:b14
+[0-9a-f]+[048c] <[^>]*> 01844ce0[ \t]+shl \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 5310bce0[ \t]+\[!b1\] shl \.S1X b4,a5,a6
+[0-9a-f]+[048c] <[^>]*> a49d0ce2[ \t]+\[a2\] shl \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 06297ce2[ \t]+shl \.S2X a10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 693a0c60[ \t]+\[b2\] shl \.S1 a15:a14,a16,a19:a18
+[0-9a-f]+[048c] <[^>]*> 0c52cc62[ \t]+shl \.S2 b21:b20,b22,b25:b24
+[0-9a-f]+[048c] <[^>]*> be6b64e0[ \t]+\[!a2\] shl \.S1 a26,a27,a29:a28
+[0-9a-f]+[048c] <[^>]*> 007bf4e0[ \t]+shl \.S1X b30,a31,a1:a0
+[0-9a-f]+[048c] <[^>]*> 020864e2[ \t]+shl \.S2 b2,b3,b5:b4
+[0-9a-f]+[048c] <[^>]*> 7418f4e2[ \t]+\[!b2\] shl \.S2X a6,b7,b9:b8
+[0-9a-f]+[048c] <[^>]*> 01840ca0[ \t]+shl \.S1 a1,0,a3
+[0-9a-f]+[048c] <[^>]*> c313fca0[ \t]+\[a0\] shl \.S1X b4,31,a6
+[0-9a-f]+[048c] <[^>]*> 249e2ca2[ \t]+\[b0\] shl \.S2 b7,17,b9
+[0-9a-f]+[048c] <[^>]*> 06299ca2[ \t]+shl \.S2X a10,12,b12
+[0-9a-f]+[048c] <[^>]*> d9380c20[ \t]+\[!a0\] shl \.S1 a15:a14,0,a19:a18
+[0-9a-f]+[048c] <[^>]*> 0c53ec22[ \t]+shl \.S2 b21:b20,31,b25:b24
+[0-9a-f]+[048c] <[^>]*> 3e6be4a0[ \t]+\[!b0\] shl \.S1 a26,31,a29:a28
+[0-9a-f]+[048c] <[^>]*> 007814a0[ \t]+shl \.S1X b30,0,a1:a0
+[0-9a-f]+[048c] <[^>]*> 0208a4a2[ \t]+shl \.S2 b2,5,b5:b4
+[0-9a-f]+[048c] <[^>]*> 841934a2[ \t]+\[a1\] shl \.S2X a6,9,b9:b8
+[0-9a-f]+[048c] <[^>]*> 01882c38[ \t]+shlmb \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 43149c38[ \t]+\[b1\] shlmb \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 94a0ec3a[ \t]+\[!a1\] shlmb \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5c3a[ \t]+shlmb \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01882e70[ \t]+shlmb \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 53149e70[ \t]+\[!b1\] shlmb \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> a4a0ee72[ \t]+\[a2\] shlmb \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5e72[ \t]+shlmb \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01844de0[ \t]+shr \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 6310bde0[ \t]+\[b2\] shr \.S1X b4,a5,a6
+[0-9a-f]+[048c] <[^>]*> b49d0de2[ \t]+\[!a2\] shr \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 06297de2[ \t]+shr \.S2X a10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 793a0d60[ \t]+\[!b2\] shr \.S1 a15:a14,a16,a19:a18
+[0-9a-f]+[048c] <[^>]*> 0c52cd62[ \t]+shr \.S2 b21:b20,b22,b25:b24
+[0-9a-f]+[048c] <[^>]*> 01840da0[ \t]+shr \.S1 a1,0,a3
+[0-9a-f]+[048c] <[^>]*> c313fda0[ \t]+\[a0\] shr \.S1X b4,31,a6
+[0-9a-f]+[048c] <[^>]*> 249e2da2[ \t]+\[b0\] shr \.S2 b7,17,b9
+[0-9a-f]+[048c] <[^>]*> 06299da2[ \t]+shr \.S2X a10,12,b12
+[0-9a-f]+[048c] <[^>]*> d9380d20[ \t]+\[!a0\] shr \.S1 a15:a14,0,a19:a18
+[0-9a-f]+[048c] <[^>]*> 0c53ed22[ \t]+shr \.S2 b21:b20,31,b25:b24
+[0-9a-f]+[048c] <[^>]*> 01844df0[ \t]+shr2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 3310bdf0[ \t]+\[!b0\] shr2 \.S1X b4,a5,a6
+[0-9a-f]+[048c] <[^>]*> 849d0df2[ \t]+\[a1\] shr2 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 06297df2[ \t]+shr2 \.S2X a10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 0187e620[ \t]+shr2 \.S1 a1,31,a3
+[0-9a-f]+[048c] <[^>]*> 43101620[ \t]+\[b1\] shr2 \.S1X b4,0,a6
+[0-9a-f]+[048c] <[^>]*> 949ca622[ \t]+\[!a1\] shr2 \.S2 b7,5,b9
+[0-9a-f]+[048c] <[^>]*> 062b3622[ \t]+shr2 \.S2X a10,25,b12
+[0-9a-f]+[048c] <[^>]*> 01882eb0[ \t]+shrmb \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 53149eb0[ \t]+\[!b1\] shrmb \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> a4a0eeb2[ \t]+\[a2\] shrmb \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5eb2[ \t]+shrmb \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 018449e0[ \t]+shru \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 6310b9e0[ \t]+\[b2\] shru \.S1X b4,a5,a6
+[0-9a-f]+[048c] <[^>]*> b49d09e2[ \t]+\[!a2\] shru \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062979e2[ \t]+shru \.S2X a10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 793a0960[ \t]+\[!b2\] shru \.S1 a15:a14,a16,a19:a18
+[0-9a-f]+[048c] <[^>]*> 0c52c962[ \t]+shru \.S2 b21:b20,b22,b25:b24
+[0-9a-f]+[048c] <[^>]*> 018409a0[ \t]+shru \.S1 a1,0,a3
+[0-9a-f]+[048c] <[^>]*> c313f9a0[ \t]+\[a0\] shru \.S1X b4,31,a6
+[0-9a-f]+[048c] <[^>]*> 249e29a2[ \t]+\[b0\] shru \.S2 b7,17,b9
+[0-9a-f]+[048c] <[^>]*> 062999a2[ \t]+shru \.S2X a10,12,b12
+[0-9a-f]+[048c] <[^>]*> d9380920[ \t]+\[!a0\] shru \.S1 a15:a14,0,a19:a18
+[0-9a-f]+[048c] <[^>]*> 0c53e922[ \t]+shru \.S2 b21:b20,31,b25:b24
+[0-9a-f]+[048c] <[^>]*> 01844e30[ \t]+shru2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 3310be30[ \t]+\[!b0\] shru2 \.S1X b4,a5,a6
+[0-9a-f]+[048c] <[^>]*> 849d0e32[ \t]+\[a1\] shru2 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 06297e32[ \t]+shru2 \.S2X a10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 0187e660[ \t]+shru2 \.S1 a1,31,a3
+[0-9a-f]+[048c] <[^>]*> 43101660[ \t]+\[b1\] shru2 \.S1X b4,0,a6
+[0-9a-f]+[048c] <[^>]*> 949ca662[ \t]+\[!a1\] shru2 \.S2 b7,5,b9
+[0-9a-f]+[048c] <[^>]*> 062b3662[ \t]+shru2 \.S2X a10,25,b12
+[0-9a-f]+[048c] <[^>]*> 0398ad00[ \t]+smpy \.M1 a5,a6,a7
+[0-9a-f]+[048c] <[^>]*> 55251d00[ \t]+\[!b1\] smpy \.M1X a8,b9,a10
+[0-9a-f]+[048c] <[^>]*> a6b16d02[ \t]+\[a2\] smpy \.M2 b11,b12,b13
+[0-9a-f]+[048c] <[^>]*> 083ddd02[ \t]+smpy \.M2X b14,a15,b16
+[0-9a-f]+[048c] <[^>]*> 0398a100[ \t]+smpyh \.M1 a5,a6,a7
+[0-9a-f]+[048c] <[^>]*> 65251100[ \t]+\[b2\] smpyh \.M1X a8,b9,a10
+[0-9a-f]+[048c] <[^>]*> b6b16102[ \t]+\[!a2\] smpyh \.M2 b11,b12,b13
+[0-9a-f]+[048c] <[^>]*> 083dd102[ \t]+smpyh \.M2X b14,a15,b16
+[0-9a-f]+[048c] <[^>]*> 0398a500[ \t]+smpyhl \.M1 a5,a6,a7
+[0-9a-f]+[048c] <[^>]*> 75251500[ \t]+\[!b2\] smpyhl \.M1X a8,b9,a10
+[0-9a-f]+[048c] <[^>]*> c6b16502[ \t]+\[a0\] smpyhl \.M2 b11,b12,b13
+[0-9a-f]+[048c] <[^>]*> 083dd502[ \t]+smpyhl \.M2X b14,a15,b16
+[0-9a-f]+[048c] <[^>]*> 0398a900[ \t]+smpylh \.M1 a5,a6,a7
+[0-9a-f]+[048c] <[^>]*> 25251900[ \t]+\[b0\] smpylh \.M1X a8,b9,a10
+[0-9a-f]+[048c] <[^>]*> d6b16902[ \t]+\[!a0\] smpylh \.M2 b11,b12,b13
+[0-9a-f]+[048c] <[^>]*> 083dd902[ \t]+smpylh \.M2X b14,a15,b16
+[0-9a-f]+[048c] <[^>]*> 3a4a2070[ \t]+\[!b0\] smpy2 \.M1 a17,a18,a21:a20
+[0-9a-f]+[048c] <[^>]*> 0c5ed070[ \t]+smpy2 \.M1X a22,b23,a25:a24
+[0-9a-f]+[048c] <[^>]*> 0e6f4072[ \t]+smpy2 \.M2 b26,b27,b29:b28
+[0-9a-f]+[048c] <[^>]*> 807fd072[ \t]+\[a1\] smpy2 \.M2X b30,a31,b1:b0
+[0-9a-f]+[048c] <[^>]*> 1aca2670[ \t]+smpy32 \.M1 a17,a18,a21
+[0-9a-f]+[048c] <[^>]*> 1cded670[ \t]+smpy32 \.M1X a22,b23,a25
+[0-9a-f]+[048c] <[^>]*> 1eef4672[ \t]+smpy32 \.M2 b26,b27,b29
+[0-9a-f]+[048c] <[^>]*> 10ffd672[ \t]+smpy32 \.M2X b30,a31,b1
+[0-9a-f]+[048c] <[^>]*> 01882cb0[ \t]+spack2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 43149cb0[ \t]+\[b1\] spack2 \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 94a0ecb2[ \t]+\[!a1\] spack2 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5cb2[ \t]+spack2 \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01882d30[ \t]+spacku4 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 53149d30[ \t]+\[!b1\] spacku4 \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> a4a0ed32[ \t]+\[a2\] spacku4 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5d32[ \t]+spacku4 \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 673400a0[ \t]+\[b2\] spdp \.S1 a13,a15:a14
+[0-9a-f]+[048c] <[^>]*> 083c10a0[ \t]+spdp \.S1X b15,a17:a16
+[0-9a-f]+[048c] <[^>]*> 0a4800a2[ \t]+spdp \.S2 b18,b21:b20
+[0-9a-f]+[048c] <[^>]*> bb5410a2[ \t]+\[!a2\] spdp \.S2X a21,b23:b22
+[0-9a-f]+[048c] <[^>]*> 77b40158[ \t]+\[!b2\] spint \.L1 a13,a15
+[0-9a-f]+[048c] <[^>]*> 08bc1158[ \t]+spint \.L1X b15,a17
+[0-9a-f]+[048c] <[^>]*> 0ac8015a[ \t]+spint \.L2 b18,b21
+[0-9a-f]+[048c] <[^>]*> cbd4115a[ \t]+\[a0\] spint \.L2X a21,b23
+[0-9a-f]+[048c] <[^>]*> 27b40178[ \t]+\[b0\] sptrunc \.L1 a13,a15
+[0-9a-f]+[048c] <[^>]*> 08bc1178[ \t]+sptrunc \.L1X b15,a17
+[0-9a-f]+[048c] <[^>]*> 0ac8017a[ \t]+sptrunc \.L2 b18,b21
+[0-9a-f]+[048c] <[^>]*> dbd4117a[ \t]+\[!a0\] sptrunc \.L2X a21,b23
+[0-9a-f]+[048c] <[^>]*> 018448e0[ \t]+sshl \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 3310b8e0[ \t]+\[!b0\] sshl \.S1X b4,a5,a6
+[0-9a-f]+[048c] <[^>]*> 849d08e2[ \t]+\[a1\] sshl \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062978e2[ \t]+sshl \.S2X a10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 0737e8a0[ \t]+sshl \.S1 a13,31,a14
+[0-9a-f]+[048c] <[^>]*> 483c18a0[ \t]+\[b1\] sshl \.S1X b15,0,a16
+[0-9a-f]+[048c] <[^>]*> 994728a2[ \t]+\[!a1\] sshl \.S2 b17,25,b18
+[0-9a-f]+[048c] <[^>]*> 0a4cf8a2[ \t]+sshl \.S2X a19,7,b20
+[0-9a-f]+[048c] <[^>]*> 01844730[ \t]+sshvl \.M1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 5310b730[ \t]+\[!b1\] sshvl \.M1X b4,a5,a6
+[0-9a-f]+[048c] <[^>]*> a49d0732[ \t]+\[a2\] sshvl \.M2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 06297732[ \t]+sshvl \.M2X a10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 018446b0[ \t]+sshvr \.M1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 5310b6b0[ \t]+\[!b1\] sshvr \.M1X b4,a5,a6
+[0-9a-f]+[048c] <[^>]*> a49d06b2[ \t]+\[a2\] sshvr \.M2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062976b2[ \t]+sshvr \.M2X a10,b11,b12
+[0-9a-f]+[048c] <[^>]*> 618821f8[ \t]+\[b2\] ssub \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 031491f8[ \t]+ssub \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 04a0e1fa[ \t]+ssub \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> b62d51fa[ \t]+\[!a2\] ssub \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 07b9b3f8[ \t]+ssub \.L1X b13,a14,a15
+[0-9a-f]+[048c] <[^>]*> 794613fa[ \t]+\[!b2\] ssub \.L2X a16,b17,b18
+[0-9a-f]+[048c] <[^>]*> 000003f8[ \t]+ssub \.L1 a0,a0,a0
+[0-9a-f]+[048c] <[^>]*> 0a4e01d8[ \t]+ssub \.L1 -16,a19,a20
+[0-9a-f]+[048c] <[^>]*> cb55f1d8[ \t]+\[a0\] ssub \.L1X 15,b21,a22
+[0-9a-f]+[048c] <[^>]*> 2c5ce1da[ \t]+\[b0\] ssub \.L2 7,b23,b24
+[0-9a-f]+[048c] <[^>]*> 0d66f1da[ \t]+ssub \.L2X -9,a25,b26
+[0-9a-f]+[048c] <[^>]*> 0f720598[ \t]+ssub \.L1 -16,a29:a28,a31:a30
+[0-9a-f]+[048c] <[^>]*> d101e59a[ \t]+\[!a0\] ssub \.L2 15,b1:b0,b3:b2
+[0-9a-f]+[048c] <[^>]*> 01882c98[ \t]+ssub2 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 33149c98[ \t]+\[!b0\] ssub2 \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 84a0ec9a[ \t]+\[a1\] ssub2 \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5c9a[ \t]+ssub2 \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 03940234[ \t]+stb \.D1T1 a7,\*\+a5\(0\)
+[0-9a-f]+[048c] <[^>]*> 65a43236[ \t]+\[b2\] stb \.D1T2 b11,\*\+\+a9\(1\)
+[0-9a-f]+[048c] <[^>]*> 07b430b4[ \t]+stb \.D2T1 a15,\*--b13\(1\)
+[0-9a-f]+[048c] <[^>]*> b9c436b6[ \t]+\[!a2\] stb \.D2T2 b19,\*b17\+\+\(1\)
+[0-9a-f]+[048c] <[^>]*> 0bd43434[ \t]+stb \.D1T1 a23,\*a21--\(1\)
+[0-9a-f]+[048c] <[^>]*> 7de7e0b6[ \t]+\[!b2\] stb \.D2T2 b27,\*-b25\(31\)
+[0-9a-f]+[048c] <[^>]*> 0ff40234[ \t]+stb \.D1T1 a31,\*\+a29\(0\)
+[0-9a-f]+[048c] <[^>]*> 01004034[ \t]+stb \.D1T1 a2,\*-a0\(2\)
+[0-9a-f]+[048c] <[^>]*> 0310a834[ \t]+stb \.D1T1 a6,\*-a4\[a5\]
+[0-9a-f]+[048c] <[^>]*> 049d0a34[ \t]+stb \.D1T1 a9,\*\+a7\[a8\]
+[0-9a-f]+[048c] <[^>]*> 06297034[ \t]+stb \.D1T1 a12,\*--a10\(11\)
+[0-9a-f]+[048c] <[^>]*> 07b5d234[ \t]+stb \.D1T1 a15,\*\+\+a13\(14\)
+[0-9a-f]+[048c] <[^>]*> 09423434[ \t]+stb \.D1T1 a18,\*a16--\(17\)
+[0-9a-f]+[048c] <[^>]*> 0ace9634[ \t]+stb \.D1T1 a21,\*a19\+\+\(20\)
+[0-9a-f]+[048c] <[^>]*> 0c5af834[ \t]+stb \.D1T1 a24,\*--a22\[a23\]
+[0-9a-f]+[048c] <[^>]*> 0de75a34[ \t]+stb \.D1T1 a27,\*\+\+a25\[a26\]
+[0-9a-f]+[048c] <[^>]*> 0f73bc34[ \t]+stb \.D1T1 a30,\*a28--\[a29\]
+[0-9a-f]+[048c] <[^>]*> 00fc1e34[ \t]+stb \.D1T1 a1,\*a31\+\+\[a0\]
+[0-9a-f]+[048c] <[^>]*> c7ffff3c[ \t]+\[a0\] stb \.D2T1 a15,\*\+b14\(32767\)
+[0-9a-f]+[048c] <[^>]*> 087fffbe[ \t]+stb \.D2T2 b16,\*\+b15\(32767\)
+[0-9a-f]+[048c] <[^>]*> 03140344[ \t]+stdw \.D1T1 a7:a6,\*\+a5\(0\)
+[0-9a-f]+[048c] <[^>]*> 65243346[ \t]+\[b2\] stdw \.D1T2 b11:b10,\*\+\+a9\(8\)
+[0-9a-f]+[048c] <[^>]*> 073431c4[ \t]+stdw \.D2T1 a15:a14,\*--b13\(8\)
+[0-9a-f]+[048c] <[^>]*> b94437c6[ \t]+\[!a2\] stdw \.D2T2 b19:b18,\*b17\+\+\(8\)
+[0-9a-f]+[048c] <[^>]*> 0b543544[ \t]+stdw \.D1T1 a23:a22,\*a21--\(8\)
+[0-9a-f]+[048c] <[^>]*> 7d67e1c6[ \t]+\[!b2\] stdw \.D2T2 b27:b26,\*-b25\(248\)
+[0-9a-f]+[048c] <[^>]*> 0f740344[ \t]+stdw \.D1T1 a31:a30,\*\+a29\(0\)
+[0-9a-f]+[048c] <[^>]*> 0103e144[ \t]+stdw \.D1T1 a3:a2,\*-a0\(248\)
+[0-9a-f]+[048c] <[^>]*> 0310a944[ \t]+stdw \.D1T1 a7:a6,\*-a4\[a5\]
+[0-9a-f]+[048c] <[^>]*> 041d0b44[ \t]+stdw \.D1T1 a9:a8,\*\+a7\[a8\]
+[0-9a-f]+[048c] <[^>]*> 06297144[ \t]+stdw \.D1T1 a13:a12,\*--a10\(88\)
+[0-9a-f]+[048c] <[^>]*> 07345344[ \t]+stdw \.D1T1 a15:a14,\*\+\+a13\(16\)
+[0-9a-f]+[048c] <[^>]*> 09407544[ \t]+stdw \.D1T1 a19:a18,\*a16--\(24\)
+[0-9a-f]+[048c] <[^>]*> 0a4c9744[ \t]+stdw \.D1T1 a21:a20,\*a19\+\+\(32\)
+[0-9a-f]+[048c] <[^>]*> 0c5af944[ \t]+stdw \.D1T1 a25:a24,\*--a22\[a23\]
+[0-9a-f]+[048c] <[^>]*> 0d675b44[ \t]+stdw \.D1T1 a27:a26,\*\+\+a25\[a26\]
+[0-9a-f]+[048c] <[^>]*> 0f73bd44[ \t]+stdw \.D1T1 a31:a30,\*a28--\[a29\]
+[0-9a-f]+[048c] <[^>]*> 007c1f44[ \t]+stdw \.D1T1 a1:a0,\*a31\+\+\[a0\]
+[0-9a-f]+[048c] <[^>]*> 03940254[ \t]+sth \.D1T1 a7,\*\+a5\(0\)
+[0-9a-f]+[048c] <[^>]*> 65a43256[ \t]+\[b2\] sth \.D1T2 b11,\*\+\+a9\(2\)
+[0-9a-f]+[048c] <[^>]*> 07b430d4[ \t]+sth \.D2T1 a15,\*--b13\(2\)
+[0-9a-f]+[048c] <[^>]*> b9c436d6[ \t]+\[!a2\] sth \.D2T2 b19,\*b17\+\+\(2\)
+[0-9a-f]+[048c] <[^>]*> 0bd43454[ \t]+sth \.D1T1 a23,\*a21--\(2\)
+[0-9a-f]+[048c] <[^>]*> 7de7e0d6[ \t]+\[!b2\] sth \.D2T2 b27,\*-b25\(62\)
+[0-9a-f]+[048c] <[^>]*> 0ff40254[ \t]+sth \.D1T1 a31,\*\+a29\(0\)
+[0-9a-f]+[048c] <[^>]*> 0103e054[ \t]+sth \.D1T1 a2,\*-a0\(62\)
+[0-9a-f]+[048c] <[^>]*> 0310a854[ \t]+sth \.D1T1 a6,\*-a4\[a5\]
+[0-9a-f]+[048c] <[^>]*> 049d0a54[ \t]+sth \.D1T1 a9,\*\+a7\[a8\]
+[0-9a-f]+[048c] <[^>]*> 06297054[ \t]+sth \.D1T1 a12,\*--a10\(22\)
+[0-9a-f]+[048c] <[^>]*> 07b4f254[ \t]+sth \.D1T1 a15,\*\+\+a13\(14\)
+[0-9a-f]+[048c] <[^>]*> 09413454[ \t]+sth \.D1T1 a18,\*a16--\(18\)
+[0-9a-f]+[048c] <[^>]*> 0acd5654[ \t]+sth \.D1T1 a21,\*a19\+\+\(20\)
+[0-9a-f]+[048c] <[^>]*> 0c5af854[ \t]+sth \.D1T1 a24,\*--a22\[a23\]
+[0-9a-f]+[048c] <[^>]*> 0de75a54[ \t]+sth \.D1T1 a27,\*\+\+a25\[a26\]
+[0-9a-f]+[048c] <[^>]*> 0f73bc54[ \t]+sth \.D1T1 a30,\*a28--\[a29\]
+[0-9a-f]+[048c] <[^>]*> 00fc1e54[ \t]+sth \.D1T1 a1,\*a31\+\+\[a0\]
+[0-9a-f]+[048c] <[^>]*> c7ffff5c[ \t]+\[a0\] sth \.D2T1 a15,\*\+b14\(65534\)
+[0-9a-f]+[048c] <[^>]*> 087fffde[ \t]+sth \.D2T2 b16,\*\+b15\(65534\)
+[0-9a-f]+[048c] <[^>]*> 03140374[ \t]+stndw \.D1T1 a7:a6,\*\+a5\(0\)
+[0-9a-f]+[048c] <[^>]*> 65a43376[ \t]+\[b2\] stndw \.D1T2 b11:b10,\*\+\+a9\[1\]
+[0-9a-f]+[048c] <[^>]*> 07b431f4[ \t]+stndw \.D2T1 a15:a14,\*--b13\[1\]
+[0-9a-f]+[048c] <[^>]*> b9c437f6[ \t]+\[!a2\] stndw \.D2T2 b19:b18,\*b17\+\+\[1\]
+[0-9a-f]+[048c] <[^>]*> 0bd43574[ \t]+stndw \.D1T1 a23:a22,\*a21--\[1\]
+[0-9a-f]+[048c] <[^>]*> 7de7e1f6[ \t]+\[!b2\] stndw \.D2T2 b27:b26,\*-b25\[31\]
+[0-9a-f]+[048c] <[^>]*> 0ff40374[ \t]+stndw \.D1T1 a31:a30,\*\+a29\[0\]
+[0-9a-f]+[048c] <[^>]*> 0103e174[ \t]+stndw \.D1T1 a3:a2,\*-a0\(31\)
+[0-9a-f]+[048c] <[^>]*> 0390a974[ \t]+stndw \.D1T1 a7:a6,\*-a4\[a5\]
+[0-9a-f]+[048c] <[^>]*> 041d0b74[ \t]+stndw \.D1T1 a9:a8,\*\+a7\(a8\)
+[0-9a-f]+[048c] <[^>]*> 06a97174[ \t]+stndw \.D1T1 a13:a12,\*--a10\[11\]
+[0-9a-f]+[048c] <[^>]*> 07361374[ \t]+stndw \.D1T1 a15:a14,\*\+\+a13\(16\)
+[0-9a-f]+[048c] <[^>]*> 09431574[ \t]+stndw \.D1T1 a19:a18,\*a16--\(24\)
+[0-9a-f]+[048c] <[^>]*> 0a4fd774[ \t]+stndw \.D1T1 a21:a20,\*a19\+\+\(30\)
+[0-9a-f]+[048c] <[^>]*> 0cdaf974[ \t]+stndw \.D1T1 a25:a24,\*--a22\[a23\]
+[0-9a-f]+[048c] <[^>]*> 0d675b74[ \t]+stndw \.D1T1 a27:a26,\*\+\+a25\(a26\)
+[0-9a-f]+[048c] <[^>]*> 0ff3bd74[ \t]+stndw \.D1T1 a31:a30,\*a28--\[a29\]
+[0-9a-f]+[048c] <[^>]*> 007c1f74[ \t]+stndw \.D1T1 a1:a0,\*a31\+\+\(a0\)
+[0-9a-f]+[048c] <[^>]*> 03940354[ \t]+stnw \.D1T1 a7,\*\+a5\(0\)
+[0-9a-f]+[048c] <[^>]*> 65a43356[ \t]+\[b2\] stnw \.D1T2 b11,\*\+\+a9\(4\)
+[0-9a-f]+[048c] <[^>]*> 07b431d4[ \t]+stnw \.D2T1 a15,\*--b13\(4\)
+[0-9a-f]+[048c] <[^>]*> b9c437d6[ \t]+\[!a2\] stnw \.D2T2 b19,\*b17\+\+\(4\)
+[0-9a-f]+[048c] <[^>]*> 0bd43554[ \t]+stnw \.D1T1 a23,\*a21--\(4\)
+[0-9a-f]+[048c] <[^>]*> 7de7e1d6[ \t]+\[!b2\] stnw \.D2T2 b27,\*-b25\(124\)
+[0-9a-f]+[048c] <[^>]*> 0ff40354[ \t]+stnw \.D1T1 a31,\*\+a29\(0\)
+[0-9a-f]+[048c] <[^>]*> 0103e154[ \t]+stnw \.D1T1 a2,\*-a0\(124\)
+[0-9a-f]+[048c] <[^>]*> 0310a954[ \t]+stnw \.D1T1 a6,\*-a4\[a5\]
+[0-9a-f]+[048c] <[^>]*> 049d0b54[ \t]+stnw \.D1T1 a9,\*\+a7\[a8\]
+[0-9a-f]+[048c] <[^>]*> 06297154[ \t]+stnw \.D1T1 a12,\*--a10\(44\)
+[0-9a-f]+[048c] <[^>]*> 07b49354[ \t]+stnw \.D1T1 a15,\*\+\+a13\(16\)
+[0-9a-f]+[048c] <[^>]*> 0940b554[ \t]+stnw \.D1T1 a18,\*a16--\(20\)
+[0-9a-f]+[048c] <[^>]*> 0accd754[ \t]+stnw \.D1T1 a21,\*a19\+\+\(24\)
+[0-9a-f]+[048c] <[^>]*> 0c5af954[ \t]+stnw \.D1T1 a24,\*--a22\[a23\]
+[0-9a-f]+[048c] <[^>]*> 0de75b54[ \t]+stnw \.D1T1 a27,\*\+\+a25\[a26\]
+[0-9a-f]+[048c] <[^>]*> 0f73bd54[ \t]+stnw \.D1T1 a30,\*a28--\[a29\]
+[0-9a-f]+[048c] <[^>]*> 00fc1f54[ \t]+stnw \.D1T1 a1,\*a31\+\+\[a0\]
+[0-9a-f]+[048c] <[^>]*> 03940274[ \t]+stw \.D1T1 a7,\*\+a5\(0\)
+[0-9a-f]+[048c] <[^>]*> 65a43276[ \t]+\[b2\] stw \.D1T2 b11,\*\+\+a9\(4\)
+[0-9a-f]+[048c] <[^>]*> 07b430f4[ \t]+stw \.D2T1 a15,\*--b13\(4\)
+[0-9a-f]+[048c] <[^>]*> b9c436f6[ \t]+\[!a2\] stw \.D2T2 b19,\*b17\+\+\(4\)
+[0-9a-f]+[048c] <[^>]*> 0bd43474[ \t]+stw \.D1T1 a23,\*a21--\(4\)
+[0-9a-f]+[048c] <[^>]*> 7de7e0f6[ \t]+\[!b2\] stw \.D2T2 b27,\*-b25\(124\)
+[0-9a-f]+[048c] <[^>]*> 0ff40274[ \t]+stw \.D1T1 a31,\*\+a29\(0\)
+[0-9a-f]+[048c] <[^>]*> 0103e074[ \t]+stw \.D1T1 a2,\*-a0\(124\)
+[0-9a-f]+[048c] <[^>]*> 0310a874[ \t]+stw \.D1T1 a6,\*-a4\[a5\]
+[0-9a-f]+[048c] <[^>]*> 049d0a74[ \t]+stw \.D1T1 a9,\*\+a7\[a8\]
+[0-9a-f]+[048c] <[^>]*> 06297074[ \t]+stw \.D1T1 a12,\*--a10\(44\)
+[0-9a-f]+[048c] <[^>]*> 07b49274[ \t]+stw \.D1T1 a15,\*\+\+a13\(16\)
+[0-9a-f]+[048c] <[^>]*> 0940b474[ \t]+stw \.D1T1 a18,\*a16--\(20\)
+[0-9a-f]+[048c] <[^>]*> 0accd674[ \t]+stw \.D1T1 a21,\*a19\+\+\(24\)
+[0-9a-f]+[048c] <[^>]*> 0c5af874[ \t]+stw \.D1T1 a24,\*--a22\[a23\]
+[0-9a-f]+[048c] <[^>]*> 0de75a74[ \t]+stw \.D1T1 a27,\*\+\+a25\[a26\]
+[0-9a-f]+[048c] <[^>]*> 0f73bc74[ \t]+stw \.D1T1 a30,\*a28--\[a29\]
+[0-9a-f]+[048c] <[^>]*> 00fc1e74[ \t]+stw \.D1T1 a1,\*a31\+\+\[a0\]
+[0-9a-f]+[048c] <[^>]*> c7ffff7c[ \t]+\[a0\] stw \.D2T1 a15,\*\+b14\(131068\)
+[0-9a-f]+[048c] <[^>]*> 087ffffe[ \t]+stw \.D2T2 b16,\*\+b15\(131068\)
+[0-9a-f]+[048c] <[^>]*> 018820f8[ \t]+sub \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 231490f8[ \t]+\[b0\] sub \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> d4a0e0fa[ \t]+\[!a0\] sub \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d50fa[ \t]+sub \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 37b9b2f8[ \t]+\[!b0\] sub \.L1X b13,a14,a15
+[0-9a-f]+[048c] <[^>]*> 094612fa[ \t]+sub \.L2X a16,b17,b18
+[0-9a-f]+[048c] <[^>]*> 07b9a2f8[ \t]+sub \.L1 a13,a14,a15
+[0-9a-f]+[048c] <[^>]*> 8b5264f8[ \t]+\[a1\] sub \.L1 a19,a20,a23:a22
+[0-9a-f]+[048c] <[^>]*> 0d6714f8[ \t]+sub \.L1X a24,b25,a27:a26
+[0-9a-f]+[048c] <[^>]*> 0f7784fa[ \t]+sub \.L2 b28,b29,b31:b30
+[0-9a-f]+[048c] <[^>]*> 410414fa[ \t]+\[b1\] sub \.L2X b0,a1,b3:b2
+[0-9a-f]+[048c] <[^>]*> 031496f8[ \t]+sub \.L1X b4,a5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 952516fa[ \t]+\[!a1\] sub \.L2X a8,b9,b11:b10
+[0-9a-f]+[048c] <[^>]*> 031486f8[ \t]+sub \.L1 a4,a5,a7:a6
+[0-9a-f]+[048c] <[^>]*> 06b200d8[ \t]+sub \.L1 -16,a12,a13
+[0-9a-f]+[048c] <[^>]*> 57b9f0d8[ \t]+\[!b1\] sub \.L1X 15,b14,a15
+[0-9a-f]+[048c] <[^>]*> a8c0e0da[ \t]+\[a2\] sub \.L2 7,b16,b17
+[0-9a-f]+[048c] <[^>]*> 09caf0da[ \t]+sub \.L2X -9,a18,b19
+[0-9a-f]+[048c] <[^>]*> 0b520498[ \t]+sub \.L1 -16,a21:a20,a23:a22
+[0-9a-f]+[048c] <[^>]*> 6d61e49a[ \t]+\[b2\] sub \.L2 15,b25:b24,b27:b26
+[0-9a-f]+[048c] <[^>]*> 018825e0[ \t]+sub \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> b31495e0[ \t]+\[!a2\] sub \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 74a0e5e2[ \t]+\[!b2\] sub \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d55e2[ \t]+sub \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> c7b5dd70[ \t]+\[a0\] sub \.S1X b13,a14,a15
+[0-9a-f]+[048c] <[^>]*> 09423d72[ \t]+sub \.S2X a16,b17,b18
+[0-9a-f]+[048c] <[^>]*> 07b5cd70[ \t]+sub \.S1 a13,a14,a15
+[0-9a-f]+[048c] <[^>]*> 2a4e05a0[ \t]+\[b0\] sub \.S1 -16,a19,a20
+[0-9a-f]+[048c] <[^>]*> 0b55f5a0[ \t]+sub \.S1X 15,b21,a22
+[0-9a-f]+[048c] <[^>]*> 0c5da5a2[ \t]+sub \.S2 13,b23,b24
+[0-9a-f]+[048c] <[^>]*> dd66b5a2[ \t]+\[!a0\] sub \.S2X -11,a25,b26
+[0-9a-f]+[048c] <[^>]*> 0eef88c0[ \t]+sub \.D1 a27,a28,a29
+[0-9a-f]+[048c] <[^>]*> 307be8c2[ \t]+\[!b0\] sub \.D2 b30,b31,b0
+[0-9a-f]+[048c] <[^>]*> 810409c0[ \t]+\[a1\] sub \.D1 a1,0,a2
+[0-9a-f]+[048c] <[^>]*> 020fe9c2[ \t]+sub \.D2 b3,31,b4
+[0-9a-f]+[048c] <[^>]*> 0398bb30[ \t]+sub \.D1X a5,b6,a7
+[0-9a-f]+[048c] <[^>]*> 45251b32[ \t]+\[b1\] sub \.D2X b8,a9,b10
+[0-9a-f]+[048c] <[^>]*> 0398ab30[ \t]+sub \.D1 a5,a6,a7
+[0-9a-f]+[048c] <[^>]*> 03160058[ \t]+add \.L1 -16,a5,a6
+[0-9a-f]+[048c] <[^>]*> cf2df058[ \t]+\[a0\] add \.L1X 15,b11,a30
+[0-9a-f]+[048c] <[^>]*> 0526a05a[ \t]+add \.L2 -11,b9,b10
+[0-9a-f]+[048c] <[^>]*> 0395d05a[ \t]+add \.L2X 14,a5,b7
+[0-9a-f]+[048c] <[^>]*> 0308a418[ \t]+add \.L1 5,a3:a2,a7:a6
+[0-9a-f]+[048c] <[^>]*> 2e73241a[ \t]+\[b0\] add \.L2 -7,b29:b28,b29:b28
+[0-9a-f]+[048c] <[^>]*> 059201a0[ \t]+add \.S1 -16,a4,a11
+[0-9a-f]+[048c] <[^>]*> 0ba5b1a0[ \t]+add \.S1X 13,b9,a23
+[0-9a-f]+[048c] <[^>]*> 35e5e1a2[ \t]+\[!b0\] add \.S2 15,b25,b11
+[0-9a-f]+[048c] <[^>]*> 010791a2[ \t]+add \.S2X -4,a1,b2
+[0-9a-f]+[048c] <[^>]*> 018458c0[ \t]+subab \.D1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 9310b8c2[ \t]+\[!a1\] subab \.D2 b4,b5,b6
+[0-9a-f]+[048c] <[^>]*> 041c19c0[ \t]+subab \.D1 a7,0,a8
+[0-9a-f]+[048c] <[^>]*> 5527f9c2[ \t]+\[!b1\] subab \.D2 b9,31,b10
+[0-9a-f]+[048c] <[^>]*> 01882b58[ \t]+subabs4 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> a3149b58[ \t]+\[a2\] subabs4 \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 64a0eb5a[ \t]+\[b2\] subabs4 \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5b5a[ \t]+subabs4 \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01845ac0[ \t]+subah \.D1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> b310bac2[ \t]+\[!a2\] subah \.D2 b4,b5,b6
+[0-9a-f]+[048c] <[^>]*> 741c1bc0[ \t]+\[!b2\] subah \.D1 a7,0,a8
+[0-9a-f]+[048c] <[^>]*> 0527fbc2[ \t]+subah \.D2 b9,31,b10
+[0-9a-f]+[048c] <[^>]*> 01845cc0[ \t]+subaw \.D1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> c310bcc2[ \t]+\[a0\] subaw \.D2 b4,b5,b6
+[0-9a-f]+[048c] <[^>]*> 241c1dc0[ \t]+\[b0\] subaw \.D1 a7,0,a8
+[0-9a-f]+[048c] <[^>]*> 0527fdc2[ \t]+subaw \.D2 b9,31,b10
+[0-9a-f]+[048c] <[^>]*> d2906978[ \t]+\[!a0\] subc \.L1 a3,a4,a5
+[0-9a-f]+[048c] <[^>]*> 041cd978[ \t]+subc \.L1X a6,b7,a8
+[0-9a-f]+[048c] <[^>]*> 05a9297a[ \t]+subc \.L2 b9,b10,b11
+[0-9a-f]+[048c] <[^>]*> 3735997a[ \t]+\[!b0\] subc \.L2X b12,a13,b14
+[0-9a-f]+[048c] <[^>]*> 03104338[ \t]+subdp \.L1 a3:a2,a5:a4,a7:a6
+[0-9a-f]+[048c] <[^>]*> 86291338[ \t]+\[a1\] subdp \.L1X a9:a8,b11:b10,a13:a12
+[0-9a-f]+[048c] <[^>]*> 4941c33a[ \t]+\[b1\] subdp \.L2 b15:b14,b17:b16,b19:b18
+[0-9a-f]+[048c] <[^>]*> 0c5a933a[ \t]+subdp \.L2X b21:b20,a23:a22,b25:b24
+[0-9a-f]+[048c] <[^>]*> 9f7353b8[ \t]+\[!a1\] subdp \.L1X b27:b26,a29:a28,a31:a30
+[0-9a-f]+[048c] <[^>]*> 020813ba[ \t]+subdp \.L2X a1:a0,b3:b2,b5:b4
+[0-9a-f]+[048c] <[^>]*> 0f7343b8[ \t]+subdp \.L1 a27:a26,a29:a28,a31:a30
+[0-9a-f]+[048c] <[^>]*> 03104e78[ \t]+subdp \.S1 a3:a2,a5:a4,a7:a6
+[0-9a-f]+[048c] <[^>]*> 86291e78[ \t]+\[a1\] subdp \.S1X a9:a8,b11:b10,a13:a12
+[0-9a-f]+[048c] <[^>]*> 4941ce7a[ \t]+\[b1\] subdp \.S2 b15:b14,b17:b16,b19:b18
+[0-9a-f]+[048c] <[^>]*> 0c5a9e7a[ \t]+subdp \.S2X b21:b20,a23:a22,b25:b24
+[0-9a-f]+[048c] <[^>]*> 9f6b9ef8[ \t]+\[!a1\] subdp \.S1X b27:b26,a29:a28,a31:a30
+[0-9a-f]+[048c] <[^>]*> 02005efa[ \t]+subdp \.S2X a1:a0,b3:b2,b5:b4
+[0-9a-f]+[048c] <[^>]*> 0f6b8ef8[ \t]+subdp \.S1 a27:a26,a29:a28,a31:a30
+[0-9a-f]+[048c] <[^>]*> 03946238[ \t]+subsp \.L1 a3,a5,a7
+[0-9a-f]+[048c] <[^>]*> 86ad3238[ \t]+\[a1\] subsp \.L1X a9,b11,a13
+[0-9a-f]+[048c] <[^>]*> 49c5e23a[ \t]+\[b1\] subsp \.L2 b15,b17,b19
+[0-9a-f]+[048c] <[^>]*> 0cdeb23a[ \t]+subsp \.L2X b21,a23,b25
+[0-9a-f]+[048c] <[^>]*> 9ff772b8[ \t]+\[!a1\] subsp \.L1X b27,a29,a31
+[0-9a-f]+[048c] <[^>]*> 028c32ba[ \t]+subsp \.L2X a1,b3,b5
+[0-9a-f]+[048c] <[^>]*> 0ff762b8[ \t]+subsp \.L1 a27,a29,a31
+[0-9a-f]+[048c] <[^>]*> 03946e38[ \t]+subsp \.S1 a3,a5,a7
+[0-9a-f]+[048c] <[^>]*> 56ad3e38[ \t]+\[!b1\] subsp \.S1X a9,b11,a13
+[0-9a-f]+[048c] <[^>]*> a9c5ee3a[ \t]+\[a2\] subsp \.S2 b15,b17,b19
+[0-9a-f]+[048c] <[^>]*> 0cdebe3a[ \t]+subsp \.S2X b21,a23,b25
+[0-9a-f]+[048c] <[^>]*> 6fefbeb8[ \t]+\[b2\] subsp \.S1X b27,a29,a31
+[0-9a-f]+[048c] <[^>]*> 02847eba[ \t]+subsp \.S2X a1,b3,b5
+[0-9a-f]+[048c] <[^>]*> 0fefaeb8[ \t]+subsp \.S1 a27,a29,a31
+[0-9a-f]+[048c] <[^>]*> 020c45f8[ \t]+subu \.L1 a2,a3,a5:a4
+[0-9a-f]+[048c] <[^>]*> b41cd5f8[ \t]+\[!a2\] subu \.L1X a6,b7,a9:a8
+[0-9a-f]+[048c] <[^>]*> 762d45fa[ \t]+\[!b2\] subu \.L2 b10,b11,b13:b12
+[0-9a-f]+[048c] <[^>]*> 083dd5fa[ \t]+subu \.L2X b14,a15,b17:b16
+[0-9a-f]+[048c] <[^>]*> ca4e57f8[ \t]+\[a0\] subu \.L1X b18,a19,a21:a20
+[0-9a-f]+[048c] <[^>]*> 0c5ed7fa[ \t]+subu \.L2X a22,b23,b25:b24
+[0-9a-f]+[048c] <[^>]*> 0a4e47f8[ \t]+subu \.L1 a18,a19,a21:a20
+[0-9a-f]+[048c] <[^>]*> 01882098[ \t]+sub2 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 23149098[ \t]+\[b0\] sub2 \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> d4a0e09a[ \t]+\[!a0\] sub2 \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d509a[ \t]+sub2 \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01882460[ \t]+sub2 \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 33149460[ \t]+\[!b0\] sub2 \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 84a0e462[ \t]+\[a1\] sub2 \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5462[ \t]+sub2 \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01882970[ \t]+sub2 \.D1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 43149970[ \t]+\[b1\] sub2 \.D1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 94a0e972[ \t]+\[!a1\] sub2 \.D2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5972[ \t]+sub2 \.D2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 01882cd8[ \t]+sub4 \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 53149cd8[ \t]+\[!b1\] sub4 \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> a4a0ecda[ \t]+\[a2\] sub4 \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5cda[ \t]+sub4 \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 038c6378[ \t]+packlh2 \.L1 a3,a3,a7
+[0-9a-f]+[048c] <[^>]*> 65a5237a[ \t]+\[b2\] packlh2 \.L2 b9,b9,b11
+[0-9a-f]+[048c] <[^>]*> b7b5a420[ \t]+\[!a2\] packlh2 \.S1 a13,a13,a15
+[0-9a-f]+[048c] <[^>]*> 0edee422[ \t]+packlh2 \.S2 b23,b23,b29
+[0-9a-f]+[048c] <[^>]*> 71042358[ \t]+\[!b2\] swap4 \.L1 a1,a2
+[0-9a-f]+[048c] <[^>]*> 020c3358[ \t]+swap4 \.L1X b3,a4
+[0-9a-f]+[048c] <[^>]*> 0314235a[ \t]+swap4 \.L2 b5,b6
+[0-9a-f]+[048c] <[^>]*> c41c335a[ \t]+\[a0\] swap4 \.L2X a7,b8
+[0-9a-f]+[048c] <[^>]*> 10000000[ \t]+swe
+[0-9a-f]+[048c] <[^>]*> 10002000[ \t]+swenr
+[0-9a-f]+[048c] <[^>]*> 01046358[ \t]+unpkhu4 \.L1 a1,a2
+[0-9a-f]+[048c] <[^>]*> 220c7358[ \t]+\[b0\] unpkhu4 \.L1X b3,a4
+[0-9a-f]+[048c] <[^>]*> d314635a[ \t]+\[!a0\] unpkhu4 \.L2 b5,b6
+[0-9a-f]+[048c] <[^>]*> 041c735a[ \t]+unpkhu4 \.L2X a7,b8
+[0-9a-f]+[048c] <[^>]*> 01046f20[ \t]+unpkhu4 \.S1 a1,a2
+[0-9a-f]+[048c] <[^>]*> 320c7f20[ \t]+\[!b0\] unpkhu4 \.S1X b3,a4
+[0-9a-f]+[048c] <[^>]*> 83146f22[ \t]+\[a1\] unpkhu4 \.S2 b5,b6
+[0-9a-f]+[048c] <[^>]*> 041c7f22[ \t]+unpkhu4 \.S2X a7,b8
+[0-9a-f]+[048c] <[^>]*> 01044358[ \t]+unpklu4 \.L1 a1,a2
+[0-9a-f]+[048c] <[^>]*> 420c5358[ \t]+\[b1\] unpklu4 \.L1X b3,a4
+[0-9a-f]+[048c] <[^>]*> 9314435a[ \t]+\[!a1\] unpklu4 \.L2 b5,b6
+[0-9a-f]+[048c] <[^>]*> 041c535a[ \t]+unpklu4 \.L2X a7,b8
+[0-9a-f]+[048c] <[^>]*> 01044f20[ \t]+unpklu4 \.S1 a1,a2
+[0-9a-f]+[048c] <[^>]*> 520c5f20[ \t]+\[!b1\] unpklu4 \.S1X b3,a4
+[0-9a-f]+[048c] <[^>]*> a3144f22[ \t]+\[a2\] unpklu4 \.S2 b5,b6
+[0-9a-f]+[048c] <[^>]*> 041c5f22[ \t]+unpklu4 \.S2X a7,b8
+[0-9a-f]+[048c] <[^>]*> 01882df8[ \t]+xor \.L1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 63149df8[ \t]+\[b2\] xor \.L1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> b4a0edfa[ \t]+\[!a2\] xor \.L2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5dfa[ \t]+xor \.L2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 77360dd8[ \t]+\[!b2\] xor \.L1 -16,a13,a14
+[0-9a-f]+[048c] <[^>]*> 083dfdd8[ \t]+xor \.L1X 15,b15,a16
+[0-9a-f]+[048c] <[^>]*> 09446dda[ \t]+xor \.L2 3,b17,b18
+[0-9a-f]+[048c] <[^>]*> ca4e9dda[ \t]+\[a0\] xor \.L2X -12,a19,b20
+[0-9a-f]+[048c] <[^>]*> 018822e0[ \t]+xor \.S1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 231492e0[ \t]+\[b0\] xor \.S1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> d4a0e2e2[ \t]+\[!a0\] xor \.S2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d52e2[ \t]+xor \.S2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 373602a0[ \t]+\[!b0\] xor \.S1 -16,a13,a14
+[0-9a-f]+[048c] <[^>]*> 083df2a0[ \t]+xor \.S1X 15,b15,a16
+[0-9a-f]+[048c] <[^>]*> 094462a2[ \t]+xor \.S2 3,b17,b18
+[0-9a-f]+[048c] <[^>]*> 8a4e92a2[ \t]+\[a1\] xor \.S2X -12,a19,b20
+[0-9a-f]+[048c] <[^>]*> 01882bb0[ \t]+xor \.D1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 23149bb0[ \t]+\[b0\] xor \.D1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> d4a0ebb2[ \t]+\[!a0\] xor \.D2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 062d5bb2[ \t]+xor \.D2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 37360bf0[ \t]+\[!b0\] xor \.D1 -16,a13,a14
+[0-9a-f]+[048c] <[^>]*> 083dfbf0[ \t]+xor \.D1X 15,b15,a16
+[0-9a-f]+[048c] <[^>]*> 09446bf2[ \t]+xor \.D2 3,b17,b18
+[0-9a-f]+[048c] <[^>]*> 8a4e9bf2[ \t]+\[a1\] xor \.D2X -12,a19,b20
+[0-9a-f]+[048c] <[^>]*> 118826f0[ \t]+xormpy \.M1 a1,a2,a3
+[0-9a-f]+[048c] <[^>]*> 131496f0[ \t]+xormpy \.M1X a4,b5,a6
+[0-9a-f]+[048c] <[^>]*> 14a0e6f2[ \t]+xormpy \.M2 b7,b8,b9
+[0-9a-f]+[048c] <[^>]*> 162d56f2[ \t]+xormpy \.M2X b10,a11,b12
+[0-9a-f]+[048c] <[^>]*> 073720f0[ \t]+xpnd2 \.M1 a13,a14
+[0-9a-f]+[048c] <[^>]*> 483f30f0[ \t]+\[b1\] xpnd2 \.M1X b15,a16
+[0-9a-f]+[048c] <[^>]*> 994720f2[ \t]+\[!a1\] xpnd2 \.M2 b17,b18
+[0-9a-f]+[048c] <[^>]*> 0a4f30f2[ \t]+xpnd2 \.M2X a19,b20
+[0-9a-f]+[048c] <[^>]*> 073700f0[ \t]+xpnd4 \.M1 a13,a14
+[0-9a-f]+[048c] <[^>]*> 583f10f0[ \t]+\[!b1\] xpnd4 \.M1X b15,a16
+[0-9a-f]+[048c] <[^>]*> a94700f2[ \t]+\[a2\] xpnd4 \.M2 b17,b18
+[0-9a-f]+[048c] <[^>]*> 0a4f10f2[ \t]+xpnd4 \.M2X a19,b20
+[0-9a-f]+[048c] <[^>]*> 0080a358[ \t]+mvk \.L1 0,a1
+[0-9a-f]+[048c] <[^>]*> 6100a35a[ \t]+\[b2\] mvk \.L2 0,b2
+[0-9a-f]+[048c] <[^>]*> b20004f8[ \t]+\[!a2\] sub \.L1 a0,a0,a5:a4
+[0-9a-f]+[048c] <[^>]*> 030004fa[ \t]+sub \.L2 b0,b0,b7:b6
+[0-9a-f]+[048c] <[^>]*> 04000040[ \t]+mvk \.D1 0,a8
+[0-9a-f]+[048c] <[^>]*> 74800042[ \t]+\[!b2\] mvk \.D2 0,b9
+[0-9a-f]+[048c] <[^>]*> c5000028[ \t]+\[a0\] mvk \.S1 0,a10
+[0-9a-f]+[048c] <[^>]*> 0580002a[ \t]+mvk \.S2 0,b11
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
--- /dev/null
+# Test C674x instructions.
+.text
+.nocmp
+.globl f
+f:
+ abs .L1 a5,a7
+ abs .L1X b11,a14
+ [a1] abs .L2 b16,b19
+ [!b2] abs .L2X a7,b31
+ [b1] abs .L1 a11:a10,a19:a18
+ abs .L2 b13:b12,b1:b0
+ abs2 .L1 a9,a10
+ [a2] abs2 .L1X b23,a5
+ abs2 .L2 b3,b14
+ abs2 .L2X a28,b25
+ absdp .S1 a7:a6,a25:a24
+ [a0] absdp .S2 b3:b2,b5:b4
+ abssp .S1 a9,a8
+ abssp .S1X b18,a16
+ [b0] abssp .S2 b0,b7
+ [!a1] abssp .S2X a1,b26
+ add .L1 a5,a10,a20
+ [!a2] add .L1X a3,b11,a4
+ [!b1] add .L2 b9,b8,b7
+ add .L2X b30,a20,b10
+ add .L1 a10,a11,a21:a20
+ add .L1X a13,b26,a15:a14
+ [!a0] add .L2 b29,b28,b27:b26
+ add .L2X b25,a24,b23:b22
+ [!b0] add .L1 a1,a3:a2,a5:a4
+ add .L1X b20,a17:a16,a15:a14
+ add .L2 b24,b23:b22,b21:b20
+ [b2] add .L2X a6,b17:b16,b15:b14
+ add .L1 -16,a5,a6
+ [a0] add .L1X 15,b11,a30
+ add .L2 -11,b9,b10
+ add .L2X 14,a5,b7
+ add .L1 5,a3:a2,a7:a6
+ [b0] add .L2 -7,b29:b28,b29:b28
+ [!a0] add .S1 a11,a12,a13
+ add .S1X a14,b15,a16
+ add .S2 b17,b18,b19
+ add .S2X b20,a30,b25
+ add .S1 -16,a4,a11
+ add .S1X 13,b9,a23
+ [!b0] add .S2 15,b25,b11
+ add .S2X -4,a1,b2
+ add .D1 a5,a9,a2
+ [a1] add .D2 b16,b17,b18
+ [b1] add .D1 a5,31,a6
+ add .D2 b22,0,b21
+ .word 0x01042840
+ [!a1] add .D1X a1,b2,a3
+ add .D2X b7,a8,b9
+ .word 0x00842af0
+ add .D2 b4,-5,b21
+ [!b1] add .D1X b5,-16,a4
+ add .D2X a2,15,b9
+ addab .D1 a5,a10,a15
+ [a2] addab .D2 b24,b23,b22
+ [b2] addab .D1 a25,31,a28
+ addab .D2 b4,0,b7
+ addab .D1X b14,32767,a5
+ addab .D2 b15,32,b29
+ addad .D1 a4,a7,a11
+ [!a2] addad .D2 b5,b8,b13
+ [!b2] addad .D1 a13,31,a4
+ addad .D2 b21,0,b5
+ addah .D1 a5,a10,a15
+ [a0] addah .D2 b24,b23,b22
+ [b0] addah .D1 a25,31,a28
+ addah .D2 b4,0,b7
+ addah .D1X b14,32767,a5
+ addah .D2 b15,32,b29
+ addaw .D1 a5,a10,a15
+ [!a0] addaw .D2 b24,b23,b22
+ [!b0] addaw .D1 a25,31,a28
+ addaw .D2 b4,0,b7
+ addaw .D1X b14,32767,a5
+ addaw .D2 b15,32,b29
+ adddp .L1 a3:a2,a15:a14,a19:a18
+ [b1] adddp .L1X a9:a8,b7:b6,a21:a20
+ adddp .L2 b3:b2,b15:b14,b19:b18
+ [b1] adddp .L2X b9:b8,a7:a6,b21:b20
+ [a1] adddp .S1 a13:a12,a25:a24,a29:a28
+ adddp .S1X a19:a18,b17:b16,a31:a30
+ [a1] adddp .S2 b13:b12,b25:b24,b29:b28
+ adddp .S2X b19:b18,a17:a16,b31:b30
+ addk .S1 -32768,a5
+ [!a1] addk .S2 32767,b4
+ addsp .L1 a5,a6,a7
+ [!b1] addsp .L1X a5,b10,a20
+ [a2] addsp .L2 b25,b24,b23
+ addsp .L2X b30,a20,b10
+ addsp .S1 a5,a6,a7
+ [b2] addsp .S1X a5,b10,a20
+ [!a2] addsp .S2 b25,b24,b23
+ addsp .S2X b30,a20,b10
+ addsub .L1 a22,a21,a25:a24
+ addsub .L1X a20,b19,a17:a16
+ addsub .L2 b4,b7,b17:b16
+ addsub .L2X b4,a8,b1:b0
+ addsub2 .L1 a22,a21,a25:a24
+ addsub2 .L1X a20,b19,a17:a16
+ addsub2 .L2 b4,b7,b17:b16
+ addsub2 .L2X b4,a8,b1:b0
+ [!b2] addu .L1 a4,a5,a7:a6
+ addu .L1X a20,b19,a29:a28
+ [a0] addu .L2 b11,b10,b9:b8
+ addu .L2X b4,a7,b3:b2
+ addu .L1 a11,a9:a8,a7:a6
+ [b0] addu .L1X b20,a21:a20,a23:a22
+ [!a0] addu .L2 b23,b21:b20,b27:b26
+ addu .L2X a14,b17:b16,b19:b18
+ add2 .S1 a7,a6,a5
+ [!b0] add2 .S1X a10,b9,a8
+ add2 .S2 b18,b17,b16
+ [b1] add2 .S2X b22,a29,b21
+ add2 .L1 a7,a6,a5
+ [a1] add2 .L1X a10,b9,a8
+ add2 .L2 b18,b17,b16
+ [!a1] add2 .L2X b22,a29,b21
+ add2 .D1 a7,a6,a5
+ [!b1] add2 .D1X a10,b9,a8
+ add2 .D2 b18,b17,b16
+ [a2] add2 .D2X b22,a29,b21
+ [b2] add4 .L1 a30,a27,a24
+ add4 .L1X a23,b24,a25
+ add4 .L2 b24,b26,b27
+ [!a2] add4 .L2X b14,a17,b20
+ [!b2] and .L1 a1,a2,a3
+ and .L1X a10,b3,a11
+ [a0] and .L2 b19,b23,b29
+ and .L2X b7,a8,b9
+ and .L1 -16,a4,a5
+ [b0] and .L1X 15,b6,a7
+ [!a0] and .L2 -3,b20,b18
+ and .L2X 9,a20,b18
+ [!b0] and .S1 a1,a2,a3
+ and .S1X a10,b3,a11
+ [a1] and .S2 b19,b23,b29
+ and .S2X b7,a8,b9
+ and .S1 -16,a4,a5
+ [b1] and .S1X 15,b6,a7
+ [!a1] and .S2 12,b20,b18
+ and .S2X -8,a20,b18
+ [!b1] and .D1 a1,a2,a3
+ and .D1X a10,b3,a11
+ [a2] and .D2 b19,b23,b29
+ and .D2X b7,a8,b9
+ and .D1 -16,a4,a5
+ [b2] and .D1X 15,b6,a7
+ [!a2] and .D2 -14,b20,b18
+ and .D2X 13,a20,b18
+ andn .L1 a20,a18,a17
+ [!b2] andn .L1X a16,b15,a14
+ [a0] andn .L2 b23,b25,b27
+ andn .L2X b4,a5,b8
+ andn .S1 a20,a18,a17
+ [b0] andn .S1X a16,b15,a14
+ [!a0] andn .S2 b23,b25,b27
+ andn .S2X b4,a5,b8
+ andn .D1 a20,a18,a17
+ [!b0] andn .D1X a16,b15,a14
+ [a1] andn .D2 b23,b25,b27
+ andn .D2X b4,a5,b8
+ avg2 .M1 a8,a11,a14
+ [b1] avg2 .M1X a17,b20,a23
+ avg2 .M2 b26,b29,b0
+ [!a1] avg2 .M2X b3,a6,b9
+ avgu4 .M1 a8,a11,a14
+ [!b1] avgu4 .M1X a17,b20,a23
+ avgu4 .M2 b26,b29,b0
+ [a2] avgu4 .M2X b3,a6,b9
+ b .S2 b4
+ [b2] b .S2X a4
+ [!a2] call .S2 b4
+ call .S2X a4
+ callret .S2 b4
+ [!b2] callret .S2X a4
+ ret .S2 b4
+ [a0] ret .S2X a4
+ [b0] b .S2 irp
+ [!a0] b .S2 nrp
+ call .S2 irp
+ [a0] call .S2 nrp
+ [b0] callret .S2 irp
+ callret .S2 nrp
+ [b0] ret .S2 irp
+ ret .S2 nrp
+ bitc4 .M1 a4,a14
+ [!b0] bitc4 .M1X b5,a15
+ bitc4 .M2 b16,b26
+ [b1] bitc4 .M2X a1,b31
+ bitr .M1 a4,a14
+ [a1] bitr .M1X b5,a15
+ bitr .M2 b16,b26
+ [!a1] bitr .M2X a1,b31
+ bnop .S2 B5,0
+ [!b1] bnop .S2X A20,7
+ callnop .S2 B5,0
+ [a2] callnop .S2X A20,7
+ clr .S1 a5,0,31,a10
+ [b2] clr .S2 b10,31,0,b5
+ [!a2] clr .S1 a7,a14,a21
+ clr .S1X b9,a18,a27
+ clr .S2 b20,b18,b16
+ [!b2] clr .S2X a4,b16,b31
+ cmpeq .L1 a1,a3,a3
+ [a0] cmpeq .L1X a1,b4,a7
+ [b0] cmpeq .L2 b10,b11,b12
+ cmpeq .L2X b13,a14,b15
+ [!a0] cmpeq .L1 -16,a16,a17
+ cmpeq .L1X 15,b18,a19
+ cmpeq .L2 3,b20,b22
+ [!b0] cmpeq .L2X 4,a23,b25
+ cmpeq .L1 a4,a7:a6,a18
+ [a1] cmpeq .L1X b9,a11:a10,a20
+ cmpeq .L2 b21,b23:b22,b25
+ [b1] cmpeq .L2X a19,b25:b24,b27
+ [!a1] cmpeq .L1 -16,a15:a14,a22
+ [!b1] cmpeq .L2 15,b19:b18,b17
+ cmpeq2 .S1 a11,a9,a10
+ [a2] cmpeq2 .S1X a12,b14,a15
+ cmpeq2 .S2 b16,b20,b24
+ [b2] cmpeq2 .S2X b19,a23,b22
+ [!a2] cmpeq4 .S1 a20,a23,a26
+ cmpeq4 .S1X a31,b4,a15
+ [!b2] cmpeq4 .S2 b9,b26,b5
+ cmpeq4 .S2X b3,a5,b8
+ cmpeqdp .S1 a9:a8,a7:a6,a5
+ [a0] cmpeqdp .S1X a3:a2,b1:b0,a31
+ [b0] cmpeqdp .S2 b21:b20,b17:b16,b25
+ cmpeqdp .S2X b5:b4,a7:a6,b9
+ cmpeqsp .S1 a20,a21,a22
+ [!b0] cmpeqsp .S1X a23,b24,a25
+ [!a0] cmpeqsp .S2 b26,b27,b28
+ cmpeqsp .S2X b29,a30,b31
+ cmpgt .L1 a1,a3,a3
+ [a1] cmpgt .L1X a1,b4,a7
+ [b1] cmpgt .L2 b10,b11,b12
+ cmpgt .L2X b13,a14,b15
+ [!a1] cmpgt .L1 -16,a16,a17
+ cmpgt .L1X 15,b18,a19
+ cmpgt .L2 3,b20,b22
+ [!b1] cmpgt .L2X 4,a23,b25
+ cmpgt .L1 a4,a7:a6,a18
+ [a2] cmpgt .L1X b9,a11:a10,a20
+ cmpgt .L2 b21,b23:b22,b25
+ [b2] cmpgt .L2X a19,b25:b24,b27
+ [!a2] cmpgt .L1 -16,a15:a14,a22
+ [!b2] cmpgt .L2 15,b19:b18,b17
+ [a1] cmpgt .L1X b4,a1,a7
+ cmpgt .L2X a14,b13,b15
+ [!a1] cmpgt .L1 a16,-16,a17
+ cmpgt .L1X b18,15,a19
+ cmpgt .L2 b20,3,b22
+ [!b1] cmpgt .L2X a23,4,b25
+ cmpgt .L1 a7:a6,a4,a18
+ [a2] cmpgt .L1X a11:a10,b9,a20
+ cmpgt .L2 b23:b22,b21,b25
+ [b2] cmpgt .L2X b25:b24,a19,b27
+ [!a2] cmpgt .L1 a15:a14,-16,a22
+ [!b2] cmpgt .L2 b19:b18,15,b17
+ cmpgt2 .S1 a16,a15,a14
+ [a0] cmpgt2 .S1X a13,b12,a11
+ cmpgt2 .S2 b10,b9,b8
+ [b0] cmpgt2 .S2X b7,a6,b5
+ [!a0] cmpgtdp .S1 a3:a2,a1:a0,a31
+ cmpgtdp .S1X a29:a28,b27:b26,a25
+ cmpgtdp .S2 b23:b22,b21:b20,b19
+ [!b0] cmpgtdp .S2X b17:b16,a15:a14,b13
+ [a1] cmpgtsp .S1 a3,a1,a31
+ cmpgtsp .S1X a29,b27,a25
+ cmpgtsp .S2 b23,b21,b19
+ [b1] cmpgtsp .S2X b17,a15,b13
+ cmpgtu .L1 a1,a3,a3
+ [a1] cmpgtu .L1X a1,b4,a7
+ [b1] cmpgtu .L2 b10,b11,b12
+ cmpgtu .L2X b13,a14,b15
+ [!a1] cmpgtu .L1 0,a16,a17
+ cmpgtu .L1X 31,b18,a19
+ cmpgtu .L2 3,b20,b22
+ [!b1] cmpgtu .L2X 4,a23,b25
+ cmpgtu .L1 a4,a7:a6,a18
+ [a2] cmpgtu .L1X b9,a11:a10,a20
+ cmpgtu .L2 b21,b23:b22,b25
+ [b2] cmpgtu .L2X a19,b25:b24,b27
+ [!a2] cmpgtu .L1 0,a15:a14,a22
+ [!b2] cmpgtu .L2 31,b19:b18,b17
+ cmpgtu4 .S1 a25,a27,a23
+ [a0] cmpgtu4 .S1X a21,b20,a17
+ cmpgtu4 .S2 b11,b13,b17
+ [b0] cmpgtu4 .S2X b19,a23,b29
+ cmplt .L1 a1,a3,a3
+ [a1] cmplt .L1X a1,b4,a7
+ [b1] cmplt .L2 b10,b11,b12
+ cmplt .L2X b13,a14,b15
+ [!a1] cmplt .L1 -16,a16,a17
+ cmplt .L1X 15,b18,a19
+ cmplt .L2 3,b20,b22
+ [!b1] cmplt .L2X 4,a23,b25
+ cmplt .L1 a4,a7:a6,a18
+ [a2] cmplt .L1X b9,a11:a10,a20
+ cmplt .L2 b21,b23:b22,b25
+ [b2] cmplt .L2X a19,b25:b24,b27
+ [!a2] cmplt .L1 -16,a15:a14,a22
+ [!b2] cmplt .L2 15,b19:b18,b17
+ [a1] cmplt .L1X b4,a1,a7
+ cmplt .L2X a14,b13,b15
+ [!a1] cmplt .L1 a16,-16,a17
+ cmplt .L1X b18,15,a19
+ cmplt .L2 b20,3,b22
+ [!b1] cmplt .L2X a23,4,b25
+ cmplt .L1 a7:a6,a4,a18
+ [a2] cmplt .L1X a11:a10,b9,a20
+ cmplt .L2 b23:b22,b21,b25
+ [b2] cmplt .L2X b25:b24,a19,b27
+ [!a2] cmplt .L1 a15:a14,-16,a22
+ [!b2] cmplt .L2 b19:b18,15,b17
+ cmplt2 .S1 a16,a15,a14
+ [a0] cmplt2 .S1X b12,a13,a11
+ cmplt2 .S2 b10,b9,b8
+ [b0] cmplt2 .S2X a6,b7,b5
+ [!a0] cmpltdp .S1 a3:a2,a1:a0,a31
+ cmpltdp .S1X a29:a28,b27:b26,a25
+ cmpltdp .S2 b23:b22,b21:b20,b19
+ [!b0] cmpltdp .S2X b17:b16,a15:a14,b13
+ [a1] cmpltsp .S1 a3,a1,a31
+ cmpltsp .S1X a29,b27,a25
+ cmpltsp .S2 b23,b21,b19
+ [b1] cmpltsp .S2X b17,a15,b13
+ cmpltu .L1 a1,a3,a3
+ [a1] cmpltu .L1X a1,b4,a7
+ [b1] cmpltu .L2 b10,b11,b12
+ cmpltu .L2X b13,a14,b15
+ [!a1] cmpltu .L1 0,a16,a17
+ cmpltu .L1X 31,b18,a19
+ cmpltu .L2 3,b20,b22
+ [!b1] cmpltu .L2X 4,a23,b25
+ cmpltu .L1 a4,a7:a6,a18
+ [a2] cmpltu .L1X b9,a11:a10,a20
+ cmpltu .L2 b21,b23:b22,b25
+ [b2] cmpltu .L2X a19,b25:b24,b27
+ [!a2] cmpltu .L1 0,a15:a14,a22
+ [!b2] cmpltu .L2 31,b19:b18,b17
+ cmpltu4 .S1 a25,a27,a23
+ [a0] cmpltu4 .S1X b20,a21,a17
+ cmpltu4 .S2 b11,b13,b17
+ [b0] cmpltu4 .S2X a23,b19,b29
+ cmpy .M1 a1,a2,a5:a4
+ cmpy .M1X a4,b5,a7:a6
+ cmpy .M2 b8,b9,b11:b10
+ cmpy .M2X b11,a12,b13:b12
+ cmpyr .M1 a1,a2,a5
+ cmpyr .M1X a4,b5,a7
+ cmpyr .M2 b8,b9,b11
+ cmpyr .M2X b11,a12,b13
+ cmpyr1 .M1 a1,a2,a5
+ cmpyr1 .M1X a4,b5,a7
+ cmpyr1 .M2 b8,b9,b11
+ cmpyr1 .M2X b11,a12,b13
+ ddotp4 .M1 a1,a2,a5:a4
+ ddotp4 .M1X a4,b5,a7:a6
+ ddotp4 .M2 b8,b9,b11:b10
+ ddotp4 .M2X b11,a12,b13:b12
+ ddotph2 .M1 a1:a0,a2,a5:a4
+ ddotph2 .M1X a3:a2,b5,a7:a6
+ ddotph2 .M2 b7:b6,b9,b11:b10
+ ddotph2 .M2X b11:b10,a12,b13:b12
+ ddotph2r .M1 a1:a0,a2,a5
+ ddotph2r .M1X a3:a2,b5,a7
+ ddotph2r .M2 b7:b6,b9,b11
+ ddotph2r .M2X b11:b10,a12,b13
+ ddotpl2 .M1 a1:a0,a2,a5:a4
+ ddotpl2 .M1X a3:a2,b5,a7:a6
+ ddotpl2 .M2 b7:b6,b9,b11:b10
+ ddotpl2 .M2X b11:b10,a12,b13:b12
+ ddotpl2r .M1 a1:a0,a2,a5
+ ddotpl2r .M1X a3:a2,b5,a7
+ ddotpl2r .M2 b7:b6,b9,b11
+ ddotpl2r .M2X b11:b10,a12,b13
+ deal .M1 a8,a9
+ [!a0] deal .M1X b10,a11
+ [!b0] deal .M2 b12,b13
+ deal .M2X a14,b15
+ dint
+ [a1] dmv .S1 a4,a5,a7:a6
+ dmv .S1X a8,b9,a11:a10
+ dmv .S2 b12,b13,b15:b14
+ [b1] dmv .S2X b16,a17,b19:b18
+ dotp2 .M1 a20,a15,a10
+ [!a1] dotp2 .M1X a10,b5,a0
+ dotp2 .M2 b7,b14,b21
+ [!b1] dotp2 .M2X b23,a20,b17
+ dotp2 .M1 a20,a15,a11:a10
+ [a2] dotp2 .M1X a10,b5,a1:a0
+ [b2] dotp2 .M2 b7,b14,b21:b20
+ dotp2 .M2X b23,a20,b17:b16
+ dotpn2 .M1 a20,a15,a10
+ [!a2] dotpn2 .M1X a10,b5,a0
+ dotpn2 .M2 b7,b14,b21
+ [!b2] dotpn2 .M2X b23,a20,b17
+ dotpnrsu2 .M1 a20,a15,a10
+ [a0] dotpnrsu2 .M1X a10,b5,a0
+ dotpnrsu2 .M2 b7,b14,b21
+ [b0] dotpnrsu2 .M2X b23,a20,b17
+ [!a0] dotpnrus2 .M1 a20,a15,a10
+ dotpnrus2 .M1X b5,a10,a0
+ dotpnrus2 .M2 b7,b14,b21
+ [!b0] dotpnrus2 .M2X a20,b23,b17
+ dotprsu2 .M1 a20,a15,a10
+ [a1] dotprsu2 .M1X a10,b5,a0
+ dotprsu2 .M2 b7,b14,b21
+ [b1] dotprsu2 .M2X b23,a20,b17
+ [!a1] dotprus2 .M1 a20,a15,a10
+ dotprus2 .M1X b5,a10,a0
+ dotprus2 .M2 b7,b14,b21
+ [!b1] dotprus2 .M2X a20,b23,b17
+ dotpsu4 .M1 a20,a15,a10
+ [a2] dotpsu4 .M1X a10,b5,a0
+ dotpsu4 .M2 b7,b14,b21
+ [b2] dotpsu4 .M2X b23,a20,b17
+ dotpus4 .M1 a20,a15,a10
+ [!a2] dotpus4 .M1X b5,a10,a0
+ dotpus4 .M2 b7,b14,b21
+ [!b2] dotpus4 .M2X a20,b23,b17
+ dotpu4 .M1 a20,a15,a10
+ [a0] dotpu4 .M1X a10,b5,a0
+ dotpu4 .M2 b7,b14,b21
+ [b0] dotpu4 .M2X b23,a20,b17
+ dpack2 .L1 a30,a27,a25:a24
+ dpack2 .L1X a21,b18,a15:a14
+ dpack2 .L2 b12,b9,b7:b6
+ dpack2 .L2X b3,a0,b29:b28
+ dpackx2 .L1 a30,a27,a25:a24
+ dpackx2 .L1X a21,b18,a15:a14
+ dpackx2 .L2 b12,b9,b7:b6
+ dpackx2 .L2X b3,a0,b29:b28
+ dpint .L1 a5:a4,a3
+ [!a0] dpint .L2 b5:b4,b3
+ dpsp .L1 a5:a4,a3
+ [!b0] dpsp .L2 b5:b4,b3
+ [a1] dptrunc .L1 a5:a4,a3
+ dptrunc .L2 b5:b4,b3
+ ext .S1 a5,0,31,a10
+ [b1] ext .S2 b10,31,0,b5
+ [!a1] ext .S1 a7,a14,a21
+ ext .S1X b9,a18,a27
+ ext .S2 b20,b18,b16
+ [!b1] ext .S2X a4,b16,b31
+ extu .S1 a5,0,31,a10
+ [a2] extu .S2 b10,31,0,b5
+ [b2] extu .S1 a7,a14,a21
+ extu .S1X b9,a18,a27
+ extu .S2 b20,b18,b16
+ [!a2] extu .S2X a4,b16,b31
+ gmpy .M1 a25,a16,a9
+ gmpy .M2 b5,b12,b13
+ [!b2] gmpy4 .M1 a2,a3,a5
+ gmpy4 .M1X a7,b11,a13
+ gmpy4 .M2 b17,b19,b23
+ [a0] gmpy4 .M2X b29,a31,b5
+ idle
+ intdp .L1 a1,a3:a2
+ [b0] intdp .L1X b5,a7:a6
+ [!a0] intdp .L2 b9,b11:b10
+ intdp .L2X a5,b13:b12
+ intdpu .L1 a1,a3:a2
+ [!b0] intdpu .L1X b5,a7:a6
+ [a1] intdpu .L2 b9,b11:b10
+ intdpu .L2X a5,b13:b12
+ intsp .L1 a1,a3
+ [b1] intsp .L1X b5,a7
+ [!a1] intsp .L2 b9,b11
+ intsp .L2X a5,b13
+ intspu .L1 a1,a3
+ [!b1] intspu .L1X b5,a7
+ [a2] intspu .L2 b9,b11
+ intspu .L2X a5,b13
+ ldb .D1T1 *a5,a7
+ [b2] ldb .D1T2 *++a9,b11
+ ldb .D2T1 *--b13,a15
+ [!a2] ldb .D2T2 *b17++,b19
+ ldb .D1T1 *a21--,a23
+ [!b2] ldb .D2T2 *-b25[31],b27
+ ldb .D1T1 *+a29[0],a31
+ ldb .D1T1 *-a0(2),a2
+ ldb .D1T1 *-a4[a5],a6
+ ldb .D1T1 *+a7[a8],a9
+ ldb .D1T1 *--a10[11],a12
+ ldb .D1T1 *++a13(14),a15
+ ldb .D1T1 *a16--(17),a18
+ ldb .D1T1 *a19++(20),a21
+ ldb .D1T1 *--a22[a23],a24
+ ldb .D1T1 *++a25[a26],a27
+ ldb .D1T1 *a28--[a29],a30
+ ldb .D1T1 *a31++[a0],a1
+ [a0] ldb .D2T1 *+b14(32767),a15
+ ldb .D2T2 *+b15[32767],b16
+ ldbu .D1T1 *a5,a7
+ [b2] ldbu .D1T2 *++a9,b11
+ ldbu .D2T1 *--b13,a15
+ [!a2] ldbu .D2T2 *b17++,b19
+ ldbu .D1T1 *a21--,a23
+ [!b2] ldbu .D2T2 *-b25[31],b27
+ ldbu .D1T1 *+a29[0],a31
+ ldbu .D1T1 *-a0(2),a2
+ ldbu .D1T1 *-a4[a5],a6
+ ldbu .D1T1 *+a7[a8],a9
+ ldbu .D1T1 *--a10[11],a12
+ ldbu .D1T1 *++a13(14),a15
+ ldbu .D1T1 *a16--(17),a18
+ ldbu .D1T1 *a19++(20),a21
+ ldbu .D1T1 *--a22[a23],a24
+ ldbu .D1T1 *++a25[a26],a27
+ ldbu .D1T1 *a28--[a29],a30
+ ldbu .D1T1 *a31++[a0],a1
+ [a0] ldbu .D2T1 *+b14(32767),a15
+ ldbu .D2T2 *+b15[32767],b16
+ lddw .D1T1 *a5,a7:a6
+ [b2] lddw .D1T2 *++a9,b11:b10
+ lddw .D2T1 *--b13,a15:a14
+ [!a2] lddw .D2T2 *b17++,b19:b18
+ lddw .D1T1 *a21--,a23:a22
+ [!b2] lddw .D2T2 *-b25[31],b27:b26
+ lddw .D1T1 *+a29[0],a31:a30
+ lddw .D1T1 *-a0(248),a3:a2
+ lddw .D1T1 *-a4[a5],a7:a6
+ lddw .D1T1 *+a7[a8],a9:a8
+ lddw .D1T1 *--a10[11],a13:a12
+ lddw .D1T1 *++a13(16),a15:a14
+ lddw .D1T1 *a16--(24),a19:a18
+ lddw .D1T1 *a19++(32),a21:a20
+ lddw .D1T1 *--a22[a23],a25:a24
+ lddw .D1T1 *++a25[a26],a27:a26
+ lddw .D1T1 *a28--[a29],a31:a30
+ lddw .D1T1 *a31++[a0],a1:a0
+ ldh .D1T1 *a5,a7
+ [b2] ldh .D1T2 *++a9,b11
+ ldh .D2T1 *--b13,a15
+ [!a2] ldh .D2T2 *b17++,b19
+ ldh .D1T1 *a21--,a23
+ [!b2] ldh .D2T2 *-b25[31],b27
+ ldh .D1T1 *+a29[0],a31
+ ldh .D1T1 *-a0(62),a2
+ ldh .D1T1 *-a4[a5],a6
+ ldh .D1T1 *+a7[a8],a9
+ ldh .D1T1 *--a10[11],a12
+ ldh .D1T1 *++a13(14),a15
+ ldh .D1T1 *a16--(18),a18
+ ldh .D1T1 *a19++(20),a21
+ ldh .D1T1 *--a22[a23],a24
+ ldh .D1T1 *++a25[a26],a27
+ ldh .D1T1 *a28--[a29],a30
+ ldh .D1T1 *a31++[a0],a1
+ [a0] ldh .D2T1 *+b14(65534),a15
+ ldh .D2T2 *+b15[32767],b16
+ ldhu .D1T1 *a5,a7
+ [b2] ldhu .D1T2 *++a9,b11
+ ldhu .D2T1 *--b13,a15
+ [!a2] ldhu .D2T2 *b17++,b19
+ ldhu .D1T1 *a21--,a23
+ [!b2] ldhu .D2T2 *-b25[31],b27
+ ldhu .D1T1 *+a29[0],a31
+ ldhu .D1T1 *-a0(62),a2
+ ldhu .D1T1 *-a4[a5],a6
+ ldhu .D1T1 *+a7[a8],a9
+ ldhu .D1T1 *--a10[11],a12
+ ldhu .D1T1 *++a13(14),a15
+ ldhu .D1T1 *a16--(18),a18
+ ldhu .D1T1 *a19++(20),a21
+ ldhu .D1T1 *--a22[a23],a24
+ ldhu .D1T1 *++a25[a26],a27
+ ldhu .D1T1 *a28--[a29],a30
+ ldhu .D1T1 *a31++[a0],a1
+ [a0] ldhu .D2T1 *+b14(65534),a15
+ ldhu .D2T2 *+b15[32767],b16
+ ldndw .D1T1 *a5,a7:a6
+ [b2] ldndw .D1T2 *++a9,b11:b10
+ ldndw .D2T1 *--b13,a15:a14
+ [!a2] ldndw .D2T2 *b17++,b19:b18
+ ldndw .D1T1 *a21--,a23:a22
+ [!b2] ldndw .D2T2 *-b25[31],b27:b26
+ ldndw .D1T1 *+a29[0],a31:a30
+ ldndw .D1T1 *-a0(31),a3:a2
+ ldndw .D1T1 *-a4[a5],a7:a6
+ ldndw .D1T1 *+a7(a8),a9:a8
+ ldndw .D1T1 *--a10[11],a13:a12
+ ldndw .D1T1 *++a13(16),a15:a14
+ ldndw .D1T1 *a16--(24),a19:a18
+ ldndw .D1T1 *a19++(30),a21:a20
+ ldndw .D1T1 *--a22[a23],a25:a24
+ ldndw .D1T1 *++a25(a26),a27:a26
+ ldndw .D1T1 *a28--[a29],a31:a30
+ ldndw .D1T1 *a31++(a0),a1:a0
+ ldnw .D1T1 *a5,a7
+ [b2] ldnw .D1T2 *++a9,b11
+ ldnw .D2T1 *--b13,a15
+ [!a2] ldnw .D2T2 *b17++,b19
+ ldnw .D1T1 *a21--,a23
+ [!b2] ldnw .D2T2 *-b25[31],b27
+ ldnw .D1T1 *+a29[0],a31
+ ldnw .D1T1 *-a0(124),a2
+ ldnw .D1T1 *-a4[a5],a6
+ ldnw .D1T1 *+a7[a8],a9
+ ldnw .D1T1 *--a10[11],a12
+ ldnw .D1T1 *++a13(16),a15
+ ldnw .D1T1 *a16--(20),a18
+ ldnw .D1T1 *a19++(24),a21
+ ldnw .D1T1 *--a22[a23],a24
+ ldnw .D1T1 *++a25[a26],a27
+ ldnw .D1T1 *a28--[a29],a30
+ ldnw .D1T1 *a31++[a0],a1
+ ldw .D1T1 *a5,a7
+ [b2] ldw .D1T2 *++a9,b11
+ ldw .D2T1 *--b13,a15
+ [!a2] ldw .D2T2 *b17++,b19
+ ldw .D1T1 *a21--,a23
+ [!b2] ldw .D2T2 *-b25[31],b27
+ ldw .D1T1 *+a29[0],a31
+ ldw .D1T1 *-a0(124),a2
+ ldw .D1T1 *-a4[a5],a6
+ ldw .D1T1 *+a7[a8],a9
+ ldw .D1T1 *--a10[11],a12
+ ldw .D1T1 *++a13(16),a15
+ ldw .D1T1 *a16--(20),a18
+ ldw .D1T1 *a19++(24),a21
+ ldw .D1T1 *--a22[a23],a24
+ ldw .D1T1 *++a25[a26],a27
+ ldw .D1T1 *a28--[a29],a30
+ ldw .D1T1 *a31++[a0],a1
+ [a0] ldw .D2T1 *+b14(131068),a15
+ ldw .D2T2 *+b15[32767],b16
+ lmbd .L1 a5,a8,a13
+ [b0] lmbd .L1X a21,b2,a23
+ [!a0] lmbd .L2 b25,b16,b9
+ lmbd .L2X b1,a2,b3
+ lmbd .L1 0,a8,a13
+ [!b0] lmbd .L1X 1,b2,a23
+ [a1] lmbd .L2 15,b16,b9
+ lmbd .L2X -16,a2,b3
+ max2 .L1 a1,a2,a3
+ [b1] max2 .L1X a4,b5,a6
+ [!a1] max2 .L2 b7,b8,b9
+ max2 .L2X b10,a11,b12
+ max2 .S1 a1,a2,a3
+ [!b1] max2 .S1X a4,b5,a6
+ max2 .S2 b7,b8,b9
+ [a2] max2 .S2X b10,a11,b12
+ [b2] maxu4 .L1 a13,a14,a15
+ maxu4 .L1X a16,b17,a18
+ maxu4 .L2 b19,b20,b21
+ [!a2] maxu4 .L2X b22,a23,b24
+ min2 .L1 a1,a2,a3
+ [!b2] min2 .L1X a4,b5,a6
+ [a0] min2 .L2 b7,b8,b9
+ min2 .L2X b10,a11,b12
+ min2 .S1 a1,a2,a3
+ [b0] min2 .S1X a4,b5,a6
+ min2 .S2 b7,b8,b9
+ [!a0] min2 .S2X b10,a11,b12
+ [!b0] minu4 .L1 a13,a14,a15
+ minu4 .L1X a16,b17,a18
+ minu4 .L2 b19,b20,b21
+ [a1] minu4 .L2X b22,a23,b24
+ mpy .M1 a25,a26,a27
+ [b1] mpy .M1X a28,b29,a30
+ [!a1] mpy .M2 b31,b0,b1
+ mpy .M2X b2,a3,b4
+ [!b1] mpy .M1 -16,a5,a6
+ mpy .M1X 15,b7,a8
+ mpy .M2 5,b9,b10
+ [a2] mpy .M2X -4,a11,b12
+ mpydp .M1 a1:a0,a3:a2,a5:a4
+ [b2] mpydp .M2 b7:b6,b9:b8,b11:b10
+ mpyh .M1 a0,a1,a2
+ [!a2] mpyh .M1X a3,b4,a5
+ [!b2] mpyh .M2 b6,b7,b8
+ mpyh .M2X b9,a10,b11
+ mpyhi .M1 a0,a1,a3:a2
+ [a0] mpyhi .M1X a3,b4,a5:a4
+ [b0] mpyhi .M2 b6,b7,b9:b8
+ mpyhi .M2X b9,a10,b11:b10
+ mpyhir .M1 a0,a1,a2
+ [!a0] mpyhir .M1X a3,b4,a5
+ [!b0] mpyhir .M2 b6,b7,b8
+ mpyhir .M2X b9,a10,b11
+ mpyhl .M1 a0,a1,a2
+ [a1] mpyhl .M1X a3,b4,a5
+ [b1] mpyhl .M2 b6,b7,b8
+ mpyhl .M2X b9,a10,b11
+ mpyhlu .M1 a0,a1,a2
+ [!a1] mpyhlu .M1X a3,b4,a5
+ [!b1] mpyhlu .M2 b6,b7,b8
+ mpyhlu .M2X b9,a10,b11
+ mpyhslu .M1 a0,a1,a2
+ [a2] mpyhslu .M1X a3,b4,a5
+ [b2] mpyhslu .M2 b6,b7,b8
+ mpyhslu .M2X b9,a10,b11
+ mpyhsu .M1 a0,a1,a2
+ [!a2] mpyhsu .M1X a3,b4,a5
+ [!b2] mpyhsu .M2 b6,b7,b8
+ mpyhsu .M2X b9,a10,b11
+ mpyhu .M1 a0,a1,a2
+ [a0] mpyhu .M1X a3,b4,a5
+ [b0] mpyhu .M2 b6,b7,b8
+ mpyhu .M2X b9,a10,b11
+ mpyhuls .M1 a0,a1,a2
+ [!a0] mpyhuls .M1X a3,b4,a5
+ [!b0] mpyhuls .M2 b6,b7,b8
+ mpyhuls .M2X b9,a10,b11
+ mpyhus .M1 a0,a1,a2
+ [a1] mpyhus .M1X a3,b4,a5
+ [b1] mpyhus .M2 b6,b7,b8
+ mpyhus .M2X b9,a10,b11
+ [!a1] mpyi .M1 a0,a1,a2
+ mpyi .M1X a3,b4,a5
+ [!b1] mpyi .M2 b6,b7,b8
+ mpyi .M2X b9,a10,b11
+ [a2] mpyi .M1 -16,a1,a2
+ mpyi .M1X 15,b4,a5
+ [b2] mpyi .M2 7,b7,b8
+ mpyi .M2X -6,a10,b11
+ mpyid .M1 a0,a1,a3:a2
+ [!a2] mpyid .M1X a3,b4,a5:a4
+ [!b2] mpyid .M2 b6,b7,b9:b8
+ mpyid .M2X b9,a10,b11:b10
+ mpyid .M1 -16,a1,a3:a2
+ [a0] mpyid .M1X 2,b4,a5:a4
+ mpyid .M2 15,b7,b9:b8
+ [b0] mpyid .M2X -7,a10,b11:b10
+ mpyih .M1 a0,a1,a3:a2
+ [!a0] mpyih .M1X b4,a3,a5:a4
+ [!b0] mpyih .M2 b6,b7,b9:b8
+ mpyih .M2X a10,b9,b11:b10
+ [a1] mpyihr .M1 a0,a1,a2
+ mpyihr .M1X b4,a3,a5
+ [b1] mpyihr .M2 b6,b7,b8
+ mpyihr .M2X a10,b9,b11
+ mpyil .M1 a0,a1,a3:a2
+ [!a1] mpyil .M1X b4,a3,a5:a4
+ mpyil .M2 b6,b7,b9:b8
+ [!b1] mpyil .M2X a10,b9,b11:b10
+ [a2] mpyilr .M1 a0,a1,a2
+ mpyilr .M1X b4,a3,a5
+ mpyilr .M2 b6,b7,b8
+ [b2] mpyilr .M2X a10,b9,b11
+ mpylh .M1 a0,a1,a2
+ [!a2] mpylh .M1X a3,b4,a5
+ [!b2] mpylh .M2 b6,b7,b8
+ mpylh .M2X b9,a10,b11
+ mpylhu .M1 a0,a1,a2
+ [a0] mpylhu .M1X a3,b4,a5
+ [b0] mpylhu .M2 b6,b7,b8
+ mpylhu .M2X b9,a10,b11
+ mpyli .M1 a0,a1,a3:a2
+ [!a0] mpyli .M1X a3,b4,a5:a4
+ [!b0] mpyli .M2 b6,b7,b9:b8
+ mpyli .M2X b9,a10,b11:b10
+ mpylir .M1 a0,a1,a2
+ [a1] mpylir .M1X a3,b4,a5
+ mpylir .M2 b6,b7,b8
+ [b1] mpylir .M2X b9,a10,b11
+ [!a1] mpylshu .M1 a0,a1,a2
+ mpylshu .M1X a3,b4,a5
+ mpylshu .M2 b6,b7,b8
+ [!b1] mpylshu .M2X b9,a10,b11
+ mpyluhs .M1 a0,a1,a2
+ [a2] mpyluhs .M1X a3,b4,a5
+ mpyluhs .M2 b6,b7,b8
+ [b2] mpyluhs .M2X b9,a10,b11
+ mpysp .M1 a0,a1,a2
+ [!a2] mpysp .M1X a3,b4,a5
+ mpysp .M2 b6,b7,b8
+ [!b2] mpysp .M2X b9,a10,b11
+ [a0] mpyspdp .M1 a12,a15:a14,a17:a16
+ mpyspdp .M1X a18,b19:b18,a21:a20
+ mpyspdp .M2 b22,b25:b24,b27:b26
+ [b0] mpyspdp .M2X b29,a31:a30,b1:b0
+ mpysp2dp .M1 a0,a1,a3:a2
+ [!a0] mpysp2dp .M1X a3,b4,a5:a4
+ [!b0] mpysp2dp .M2 b6,b7,b9:b8
+ mpysp2dp .M2X b9,a10,b11:b10
+ [a1] mpysu .M1 a0,a1,a2
+ mpysu .M1X a3,b4,a5
+ [b1] mpysu .M2 b6,b7,b8
+ mpysu .M2X b9,a10,b11
+ [!a1] mpysu .M1 -16,a1,a2
+ mpysu .M1X 15,b4,a5
+ mpysu .M2 3,b7,b8
+ [!b1] mpysu .M2X -9,a10,b11
+ mpysu4 .M1 a0,a1,a3:a2
+ [!a0] mpysu4 .M1X a3,b4,a5:a4
+ [!b0] mpysu4 .M2 b6,b7,b9:b8
+ mpysu4 .M2X b9,a10,b11:b10
+ [a1] mpyu .M1 a0,a1,a2
+ mpyu .M1X a3,b4,a5
+ mpyu .M2 b6,b7,b8
+ [b1] mpyu .M2X b9,a10,b11
+ mpyu4 .M1 a0,a1,a3:a2
+ [!a1] mpyu4 .M1X a3,b4,a5:a4
+ [!b1] mpyu4 .M2 b6,b7,b9:b8
+ mpyu4 .M2X b9,a10,b11:b10
+ [a2] mpyus .M1 a0,a1,a2
+ mpyus .M1X a3,b4,a5
+ mpyus .M2 b6,b7,b8
+ [b2] mpyus .M2X b9,a10,b11
+ mpyus4 .M1 a0,a1,a3:a2
+ [!a2] mpyus4 .M1X b4,a3,a5:a4
+ [!b2] mpyus4 .M2 b6,b7,b9:b8
+ mpyus4 .M2X a10,b9,b11:b10
+ mpy2 .M1 a0,a1,a3:a2
+ [a0] mpy2 .M1X a3,b4,a5:a4
+ [b0] mpy2 .M2 b6,b7,b9:b8
+ mpy2 .M2X b9,a10,b11:b10
+ mpy2ir .M1 a0,a1,a3:a2
+ mpy2ir .M1X a3,b4,a5:a4
+ mpy2ir .M2 b6,b7,b9:b8
+ mpy2ir .M2X b9,a10,b11:b10
+ [!a0] mpy32 .M1 a0,a1,a2
+ mpy32 .M1X a3,b4,a5
+ mpy32 .M2 b6,b7,b8
+ [!b0] mpy32 .M2X b9,a10,b11
+ mpy32 .M1 a0,a1,a3:a2
+ [a1] mpy32 .M1X a3,b4,a5:a4
+ [b1] mpy32 .M2 b6,b7,b9:b8
+ mpy32 .M2X b9,a10,b11:b10
+ mpy32su .M1 a0,a1,a3:a2
+ [!a1] mpy32su .M1X a3,b4,a5:a4
+ [!b1] mpy32su .M2 b6,b7,b9:b8
+ mpy32su .M2X b9,a10,b11:b10
+ mpy32u .M1 a0,a1,a3:a2
+ [a2] mpy32u .M1X a3,b4,a5:a4
+ [b2] mpy32u .M2 b6,b7,b9:b8
+ mpy32u .M2X b9,a10,b11:b10
+ mpy32us .M1 a0,a1,a3:a2
+ [!a2] mpy32us .M1X a3,b4,a5:a4
+ [!b2] mpy32us .M2 b6,b7,b9:b8
+ mpy32us .M2X b9,a10,b11:b10
+ [a0] mv .L1 a5,a7
+ mv .L1X b8,a13
+ [b0] mv .L2 b12,b15
+ mv .L2X a17,b19
+ [!a0] mv .S1 a5,a7
+ mv .S1X b8,a13
+ mv .S2 b12,b15
+ [!b0] mv .S2X a17,b19
+ [a1] mv .D1 a5,a7
+ mv .D1X b8,a13
+ [b1] mv .D2 b12,b15
+ mv .D2X a17,b19
+ [a0] mvc .S2 amr,b5
+ mvc .S2 b6,amr
+ [b0] mvc .S2X a7,amr
+ mvc .S2 csr,b8
+ mvc .S2 b8,csr
+ mvc .S2 dnum,b9
+ mvc .S2 b10,ecr
+ mvc .S2 efr,b11
+ mvc .S2 fadcr,b12
+ mvc .S2 b13,fadcr
+ mvc .S2 faucr,b14
+ mvc .S2 b15,faucr
+ mvc .S2 fmcr,b16
+ mvc .S2 b17,fmcr
+ mvc .S2 gfpgfr,b18
+ mvc .S2 b19,gfpgfr
+ mvc .S2 gplya,b20
+ mvc .S2 b21,gplya
+ mvc .S2 gplyb,b22
+ mvc .S2 b23,gplyb
+ mvc .S2 b24,icr
+ mvc .S2 ier,b25
+ mvc .S2 b26,ier
+ mvc .S2 ierr,b27
+ mvc .S2 b28,ierr
+ mvc .S2 ifr,b29
+ mvc .S2 ilc,b30
+ mvc .S2 b31,ilc
+ mvc .S2 irp,b0
+ mvc .S2 b1,irp
+ mvc .S2 b2,isr
+ mvc .S2 istp,b3
+ mvc .S2 b4,istp
+ mvc .S2 itsr,b5
+ mvc .S2 b6,itsr
+ mvc .S2 nrp,b7
+ mvc .S2 b8,nrp
+ mvc .S2 ntsr,b9
+ mvc .S2 b10,ntsr
+ mvc .S2 pce1,b11
+ mvc .S2 rep,b12
+ mvc .S2 b13,rep
+ mvc .S2 rilc,b14
+ mvc .S2 b15,rilc
+ mvc .S2 ssr,b16
+ mvc .S2 b17,ssr
+ mvc .S2 tsch,b18
+ mvc .S2 tscl,b19
+ mvc .S2 tsr,b20
+ mvc .S2 b21,tsr
+ .word 0x0001e3e2
+ .word 0x0005e3e2
+ .word 0x0181e3a2
+ .word 0x0201e3a2
+ .word 0x0301e3a2
+ .word 0x0101e3a2
+ .word 0x0281e3a2
+ .word 0x0381e3a2
+ .word 0x004203e2
+ mvd .M1 a4,a5
+ [!a0] mvd .M1X b6,a7
+ [!b0] mvd .M2 b8,b9
+ mvd .M2X a10,b11
+ [!b1] mvk .S1 -32768,a5
+ mvk .S2 32767,b4
+ mvk .L1 -16,a4
+ [a1] mvk .L2 15,b4
+ [b1] mvk .D1 6,a4
+ mvk .D2 -9,b12
+ mvkh .S1 0x12345678,a6
+ [a2] mvkh .S2 0xfedcba98,b7
+ [b2] mvklh .S1 0x12345678,a6
+ mvklh .S2 0xfedcba98,b7
+ mvkl .S1 0x12345678,a6
+ [!a2] mvkl .S2 0xfedcba98,b7
+ neg .S1 a5,a6
+ [a0] neg .S1X b7,a8
+ [b0] neg .S2 b9,b10
+ neg .S2X a11,b12
+ [!a0] neg .L1 a13,a14
+ neg .L1X b15,a16
+ neg .L2 b17,b18
+ [!b0] neg .L2X a19,b20
+ [b1] neg .L1 a21:a20,a23:a22
+ neg .L2 b25:b24,b27:b26
+ nop 1
+ nop 2
+ nop
+ nop 3
+ nop 4
+ nop 5
+ nop 6
+ nop 7
+ nop 8
+ nop 9
+ [!b2] norm .L1 a4,a5
+ norm .L1X b6,a7
+ norm .L2 b8,b9
+ [a0] norm .L2X a10,b11
+ norm .L1 a5:a4,a6
+ [b0] norm .L2 b9:b8,b10
+ not .L1 a1,a2
+ [b2] not .L1X b3,a4
+ [!a2] not .L2 b5,b6
+ not .L2X a7,b8
+ [!b2] not .S1 a1,a2
+ not .S1X b3,a4
+ not .S2 b5,b6
+ [a0] not .S2X a7,b8
+ [b0] not .D1 a1,a2
+ not .D1X b3,a4
+ not .D2 b5,b6
+ [!a0] not .D2X a7,b8
+ [!a0] or .D1 a1,a2,a3
+ or .D1X a4,b5,a6
+ or .D2 b7,b8,b9
+ [!b0] or .D2X b10,a11,b12
+ or .D1 -16,a2,a3
+ [a1] or .D1X 11,b5,a6
+ [b1] or .D2 15,b8,b9
+ or .D2X -13,a11,b12
+ [!a1] or .L1 a1,a2,a3
+ or .L1X a4,b5,a6
+ or .L2 b7,b8,b9
+ [!b1] or .L2X b10,a11,b12
+ or .L1 -16,a2,a3
+ [a2] or .L1X 11,b5,a6
+ [b2] or .L2 15,b8,b9
+ or .L2X -13,a11,b12
+ [!a2] or .S1 a1,a2,a3
+ or .S1X a4,b5,a6
+ or .S2 b7,b8,b9
+ [!b2] or .S2X b10,a11,b12
+ or .S1 -16,a2,a3
+ [a0] or .S1X 11,b5,a6
+ [b0] or .S2 15,b8,b9
+ or .S2X -13,a11,b12
+ [!a0] pack2 .L1 a1,a2,a3
+ pack2 .L1X a5,b8,a13
+ pack2 .L2 b21,b2,b23
+ [!b0] pack2 .L2X b25,a16,b9
+ [a1] pack2 .S1 a1,a2,a3
+ pack2 .S1X a5,b8,a13
+ pack2 .S2 b21,b2,b23
+ [b1] pack2 .S2X b25,a16,b9
+ [!a1] packh2 .L1 a1,a2,a3
+ packh2 .L1X a5,b8,a13
+ packh2 .L2 b21,b2,b23
+ [!b1] packh2 .L2X b25,a16,b9
+ [a2] packh2 .S1 a1,a2,a3
+ packh2 .S1X a5,b8,a13
+ packh2 .S2 b21,b2,b23
+ [b2] packh2 .S2X b25,a16,b9
+ [!a2] packh4 .L1 a1,a2,a3
+ packh4 .L1X a5,b8,a13
+ packh4 .L2 b21,b2,b23
+ [!b2] packh4 .L2X b25,a16,b9
+ [a0] packhl2 .L1 a1,a2,a3
+ packhl2 .L1X a5,b8,a13
+ packhl2 .L2 b21,b2,b23
+ [b0] packhl2 .L2X b25,a16,b9
+ packhl2 .S1 a1,a2,a3
+ [!a0] packhl2 .S1X a5,b8,a13
+ [!b0] packhl2 .S2 b21,b2,b23
+ packhl2 .S2X b25,a16,b9
+ [a1] packlh2 .L1 a1,a2,a3
+ packlh2 .L1X a5,b8,a13
+ packlh2 .L2 b21,b2,b23
+ [b1] packlh2 .L2X b25,a16,b9
+ packlh2 .S1 a1,a2,a3
+ [!a1] packlh2 .S1X a5,b8,a13
+ [!b1] packlh2 .S2 b21,b2,b23
+ packlh2 .S2X b25,a16,b9
+ [a2] packl4 .L1 a1,a2,a3
+ packl4 .L1X a5,b8,a13
+ packl4 .L2 b21,b2,b23
+ [b2] packl4 .L2X b25,a16,b9
+ rcpdp .S1 a5:a4,a7:a6
+ [!a2] rcpdp .S2 b9:b8,b11:b10
+ rcpsp .S1 a0,a1
+ [!b2] rcpsp .S1X b2,a3
+ [a0] rcpsp .S2 b4,b5
+ rcpsp .S2X a6,b7
+ rint
+ [b0] rotl .M1 a0,a1,a2
+ rotl .M1X b3,a4,a5
+ rotl .M2 b6,b7,b8
+ [!a0] rotl .M2X a9,b10,b11
+ rotl .M1 a12,0,a13
+ [!b0] rotl .M1X b14,31,a15
+ [a1] rotl .M2 b16,17,b17
+ rotl .M2X a18,25,b19
+ rpack2 .S1 a1,a2,a3
+ rpack2 .S1X a4,b5,a6
+ rpack2 .S2 b7,b8,b9
+ rpack2 .S2X b10,a11,b12
+ rsqrdp .S1 a5:a4,a7:a6
+ [b1] rsqrdp .S2 b9:b8,b11:b10
+ rsqrsp .S1 a0,a1
+ [!a1] rsqrsp .S1X b2,a3
+ [!b1] rsqrsp .S2 b4,b5
+ rsqrsp .S2X a6,b7
+ sadd .L1 a1,a2,a3
+ [a2] sadd .L1X a4,b5,a6
+ [b2] sadd .L2 b7,b8,b9
+ sadd .L2X b10,a11,b12
+ [!a2] sadd .L1 a13,a15:a14,a17:a16
+ sadd .L1X b18,a21:a20,a23:a22
+ sadd .L2 b24,b27:b26,b29:b28
+ [!b2] sadd .L2X a30,b1:b0,b3:b2
+ sadd .L1 -16,a4,a5
+ [a0] sadd .L1X 15,b6,a7
+ [b0] sadd .L2 12,b8,b9
+ sadd .L2X -11,a10,b11
+ sadd .L1 -16,a13:a12,a15:a14
+ [!a0] sadd .L2 15,b21:b20,b23:b22
+ [!b0] sadd .S1 a28,a29,a30
+ sadd .S1X a31,b0,a1
+ sadd .S2 b2,b3,b4
+ [a1] sadd .S2X b5,a6,b7
+ sadd2 .S1 a1,a2,a3
+ [b1] sadd2 .S1X a4,b5,a6
+ [!a1] sadd2 .S2 b7,b8,b9
+ sadd2 .S2X b10,a11,b12
+ saddsub .L1 a0,a1,a3:a2
+ saddsub .L1X a4,b5,a7:a6
+ saddsub .L2 b8,b9,b11:b10
+ saddsub .L2X b12,a13,b15:b14
+ saddsub2 .L1 a0,a1,a3:a2
+ saddsub2 .L1X a4,b5,a7:a6
+ saddsub2 .L2 b8,b9,b11:b10
+ saddsub2 .L2X b12,a13,b15:b14
+ [!b1] saddsu2 .S1 a16,a17,a18
+ saddsu2 .S1X b19,a20,a21
+ saddsu2 .S2 b22,b23,b24
+ [a2] saddsu2 .S2X a25,b26,b27
+ saddus2 .S1 a28,a29,a30
+ [b2] saddus2 .S1X a31,b0,a1
+ [!a2] saddus2 .S2 b2,b3,b4
+ saddus2 .S2X b5,a6,b7
+ saddu4 .S1 a28,a29,a30
+ [!b2] saddu4 .S1X a31,b0,a1
+ [a0] saddu4 .S2 b2,b3,b4
+ saddu4 .S2X b5,a6,b7
+ [b0] sat .L1 a3:a2,a20
+ sat .L2 b7:b6,b15
+ set .S1 a1,31,0,a2
+ [!a0] set .S2 b3,0,31,b4
+ set .S1 a5,a6,a7
+ [!b0] set .S1X b8,a9,a10
+ [a1] set .S2 b11,b12,b13
+ set .S2X a14,b15,b16
+ shfl .M1 a17,a18
+ [b1] shfl .M1X b19,a20
+ [!a1] shfl .M2 b21,b22
+ shfl .M2X a23,b24
+ shfl3 .L1 a0,a1,a3:a2
+ shfl3 .L1X a4,b5,a7:a6
+ shfl3 .L2 b8,b9,b11:b10
+ shfl3 .L2X b12,a13,b15:b14
+ shl .S1 a1,a2,a3
+ [!b1] shl .S1X b4,a5,a6
+ [a2] shl .S2 b7,b8,b9
+ shl .S2X a10,b11,b12
+ [b2] shl .S1 a15:a14,a16,a19:a18
+ shl .S2 b21:b20,b22,b25:b24
+ [!a2] shl .S1 a26,a27,a29:a28
+ shl .S1X b30,a31,a1:a0
+ shl .S2 b2,b3,b5:b4
+ [!b2] shl .S2X a6,b7,b9:b8
+ shl .S1 a1,0,a3
+ [a0] shl .S1X b4,31,a6
+ [b0] shl .S2 b7,17,b9
+ shl .S2X a10,12,b12
+ [!a0] shl .S1 a15:a14,0,a19:a18
+ shl .S2 b21:b20,31,b25:b24
+ [!b0] shl .S1 a26,31,a29:a28
+ shl .S1X b30,0,a1:a0
+ shl .S2 b2,5,b5:b4
+ [a1] shl .S2X a6,9,b9:b8
+ shlmb .L1 a1,a2,a3
+ [b1] shlmb .L1X a4,b5,a6
+ [!a1] shlmb .L2 b7,b8,b9
+ shlmb .L2X b10,a11,b12
+ shlmb .S1 a1,a2,a3
+ [!b1] shlmb .S1X a4,b5,a6
+ [a2] shlmb .S2 b7,b8,b9
+ shlmb .S2X b10,a11,b12
+ shr .S1 a1,a2,a3
+ [b2] shr .S1X b4,a5,a6
+ [!a2] shr .S2 b7,b8,b9
+ shr .S2X a10,b11,b12
+ [!b2] shr .S1 a15:a14,a16,a19:a18
+ shr .S2 b21:b20,b22,b25:b24
+ shr .S1 a1,0,a3
+ [a0] shr .S1X b4,31,a6
+ [b0] shr .S2 b7,17,b9
+ shr .S2X a10,12,b12
+ [!a0] shr .S1 a15:a14,0,a19:a18
+ shr .S2 b21:b20,31,b25:b24
+ shr2 .S1 a1,a2,a3
+ [!b0] shr2 .S1X b4,a5,a6
+ [a1] shr2 .S2 b7,b8,b9
+ shr2 .S2X a10,b11,b12
+ shr2 .S1 a1,31,a3
+ [b1] shr2 .S1X b4,0,a6
+ [!a1] shr2 .S2 b7,5,b9
+ shr2 .S2X a10,25,b12
+ shrmb .S1 a1,a2,a3
+ [!b1] shrmb .S1X a4,b5,a6
+ [a2] shrmb .S2 b7,b8,b9
+ shrmb .S2X b10,a11,b12
+ shru .S1 a1,a2,a3
+ [b2] shru .S1X b4,a5,a6
+ [!a2] shru .S2 b7,b8,b9
+ shru .S2X a10,b11,b12
+ [!b2] shru .S1 a15:a14,a16,a19:a18
+ shru .S2 b21:b20,b22,b25:b24
+ shru .S1 a1,0,a3
+ [a0] shru .S1X b4,31,a6
+ [b0] shru .S2 b7,17,b9
+ shru .S2X a10,12,b12
+ [!a0] shru .S1 a15:a14,0,a19:a18
+ shru .S2 b21:b20,31,b25:b24
+ shru2 .S1 a1,a2,a3
+ [!b0] shru2 .S1X b4,a5,a6
+ [a1] shru2 .S2 b7,b8,b9
+ shru2 .S2X a10,b11,b12
+ shru2 .S1 a1,31,a3
+ [b1] shru2 .S1X b4,0,a6
+ [!a1] shru2 .S2 b7,5,b9
+ shru2 .S2X a10,25,b12
+ smpy .M1 a5,a6,a7
+ [!b1] smpy .M1X a8,b9,a10
+ [a2] smpy .M2 b11,b12,b13
+ smpy .M2X b14,a15,b16
+ smpyh .M1 a5,a6,a7
+ [b2] smpyh .M1X a8,b9,a10
+ [!a2] smpyh .M2 b11,b12,b13
+ smpyh .M2X b14,a15,b16
+ smpyhl .M1 a5,a6,a7
+ [!b2] smpyhl .M1X a8,b9,a10
+ [a0] smpyhl .M2 b11,b12,b13
+ smpyhl .M2X b14,a15,b16
+ smpylh .M1 a5,a6,a7
+ [b0] smpylh .M1X a8,b9,a10
+ [!a0] smpylh .M2 b11,b12,b13
+ smpylh .M2X b14,a15,b16
+ [!b0] smpy2 .M1 a17,a18,a21:a20
+ smpy2 .M1X a22,b23,a25:a24
+ smpy2 .M2 b26,b27,b29:b28
+ [a1] smpy2 .M2X b30,a31,b1:b0
+ smpy32 .M1 a17,a18,a21
+ smpy32 .M1X a22,b23,a25
+ smpy32 .M2 b26,b27,b29
+ smpy32 .M2X b30,a31,b1
+ spack2 .S1 a1,a2,a3
+ [b1] spack2 .S1X a4,b5,a6
+ [!a1] spack2 .S2 b7,b8,b9
+ spack2 .S2X b10,a11,b12
+ spacku4 .S1 a1,a2,a3
+ [!b1] spacku4 .S1X a4,b5,a6
+ [a2] spacku4 .S2 b7,b8,b9
+ spacku4 .S2X b10,a11,b12
+ [b2] spdp .S1 a13,a15:a14
+ spdp .S1X b15,a17:a16
+ spdp .S2 b18,b21:b20
+ [!a2] spdp .S2X a21,b23:b22
+ [!b2] spint .L1 a13,a15
+ spint .L1X b15,a17
+ spint .L2 b18,b21
+ [a0] spint .L2X a21,b23
+ [b0] sptrunc .L1 a13,a15
+ sptrunc .L1X b15,a17
+ sptrunc .L2 b18,b21
+ [!a0] sptrunc .L2X a21,b23
+ sshl .S1 a1,a2,a3
+ [!b0] sshl .S1X b4,a5,a6
+ [a1] sshl .S2 b7,b8,b9
+ sshl .S2X a10,b11,b12
+ sshl .S1 a13,31,a14
+ [b1] sshl .S1X b15,0,a16
+ [!a1] sshl .S2 b17,25,b18
+ sshl .S2X a19,7,b20
+ sshvl .M1 a1,a2,a3
+ [!b1] sshvl .M1X b4,a5,a6
+ [a2] sshvl .M2 b7,b8,b9
+ sshvl .M2X a10,b11,b12
+ sshvr .M1 a1,a2,a3
+ [!b1] sshvr .M1X b4,a5,a6
+ [a2] sshvr .M2 b7,b8,b9
+ sshvr .M2X a10,b11,b12
+ [b2] ssub .L1 a1,a2,a3
+ ssub .L1X a4,b5,a6
+ ssub .L2 b7,b8,b9
+ [!a2] ssub .L2X b10,a11,b12
+ ssub .L1X b13,a14,a15
+ [!b2] ssub .L2X a16,b17,b18
+ .word 0x000003f8
+ ssub .L1 -16,a19,a20
+ [a0] ssub .L1X 15,b21,a22
+ [b0] ssub .L2 7,b23,b24
+ ssub .L2X -9,a25,b26
+ ssub .L1 -16,a29:a28,a31:a30
+ [!a0] ssub .L2 15,b1:b0,b3:b2
+ ssub2 .L1 a1,a2,a3
+ [!b0] ssub2 .L1X a4,b5,a6
+ [a1] ssub2 .L2 b7,b8,b9
+ ssub2 .L2X b10,a11,b12
+ stb .D1T1 a7,*a5
+ [b2] stb .D1T2 b11,*++a9
+ stb .D2T1 a15,*--b13
+ [!a2] stb .D2T2 b19,*b17++
+ stb .D1T1 a23,*a21--
+ [!b2] stb .D2T2 b27,*-b25[31]
+ stb .D1T1 a31,*+a29[0]
+ stb .D1T1 a2,*-a0(2)
+ stb .D1T1 a6,*-a4[a5]
+ stb .D1T1 a9,*+a7[a8]
+ stb .D1T1 a12,*--a10[11]
+ stb .D1T1 a15,*++a13(14)
+ stb .D1T1 a18,*a16--(17)
+ stb .D1T1 a21,*a19++(20)
+ stb .D1T1 a24,*--a22[a23]
+ stb .D1T1 a27,*++a25[a26]
+ stb .D1T1 a30,*a28--[a29]
+ stb .D1T1 a1,*a31++[a0]
+ [a0] stb .D2T1 a15,*+b14(32767)
+ stb .D2T2 b16,*+b15[32767]
+ stdw .D1T1 a7:a6,*a5
+ [b2] stdw .D1T2 b11:b10,*++a9
+ stdw .D2T1 a15:a14,*--b13
+ [!a2] stdw .D2T2 b19:b18,*b17++
+ stdw .D1T1 a23:a22,*a21--
+ [!b2] stdw .D2T2 b27:b26,*-b25[31]
+ stdw .D1T1 a31:a30,*+a29[0]
+ stdw .D1T1 a3:a2,*-a0(248)
+ stdw .D1T1 a7:a6,*-a4[a5]
+ stdw .D1T1 a9:a8,*+a7[a8]
+ stdw .D1T1 a13:a12,*--a10[11]
+ stdw .D1T1 a15:a14,*++a13(16)
+ stdw .D1T1 a19:a18,*a16--(24)
+ stdw .D1T1 a21:a20,*a19++(32)
+ stdw .D1T1 a25:a24,*--a22[a23]
+ stdw .D1T1 a27:a26,*++a25[a26]
+ stdw .D1T1 a31:a30,*a28--[a29]
+ stdw .D1T1 a1:a0,*a31++[a0]
+ sth .D1T1 a7,*a5
+ [b2] sth .D1T2 b11,*++a9
+ sth .D2T1 a15,*--b13
+ [!a2] sth .D2T2 b19,*b17++
+ sth .D1T1 a23,*a21--
+ [!b2] sth .D2T2 b27,*-b25[31]
+ sth .D1T1 a31,*+a29[0]
+ sth .D1T1 a2,*-a0(62)
+ sth .D1T1 a6,*-a4[a5]
+ sth .D1T1 a9,*+a7[a8]
+ sth .D1T1 a12,*--a10[11]
+ sth .D1T1 a15,*++a13(14)
+ sth .D1T1 a18,*a16--(18)
+ sth .D1T1 a21,*a19++(20)
+ sth .D1T1 a24,*--a22[a23]
+ sth .D1T1 a27,*++a25[a26]
+ sth .D1T1 a30,*a28--[a29]
+ sth .D1T1 a1,*a31++[a0]
+ [a0] sth .D2T1 a15,*+b14(65534)
+ sth .D2T2 b16,*+b15[32767]
+ stndw .D1T1 a7:a6,*a5
+ [b2] stndw .D1T2 b11:b10,*++a9
+ stndw .D2T1 a15:a14,*--b13
+ [!a2] stndw .D2T2 b19:b18,*b17++
+ stndw .D1T1 a23:a22,*a21--
+ [!b2] stndw .D2T2 b27:b26,*-b25[31]
+ stndw .D1T1 a31:a30,*+a29[0]
+ stndw .D1T1 a3:a2,*-a0(31)
+ stndw .D1T1 a7:a6,*-a4[a5]
+ stndw .D1T1 a9:a8,*+a7(a8)
+ stndw .D1T1 a13:a12,*--a10[11]
+ stndw .D1T1 a15:a14,*++a13(16)
+ stndw .D1T1 a19:a18,*a16--(24)
+ stndw .D1T1 a21:a20,*a19++(30)
+ stndw .D1T1 a25:a24,*--a22[a23]
+ stndw .D1T1 a27:a26,*++a25(a26)
+ stndw .D1T1 a31:a30,*a28--[a29]
+ stndw .D1T1 a1:a0,*a31++(a0)
+ stnw .D1T1 a7,*a5
+ [b2] stnw .D1T2 b11,*++a9
+ stnw .D2T1 a15,*--b13
+ [!a2] stnw .D2T2 b19,*b17++
+ stnw .D1T1 a23,*a21--
+ [!b2] stnw .D2T2 b27,*-b25[31]
+ stnw .D1T1 a31,*+a29[0]
+ stnw .D1T1 a2,*-a0(124)
+ stnw .D1T1 a6,*-a4[a5]
+ stnw .D1T1 a9,*+a7[a8]
+ stnw .D1T1 a12,*--a10[11]
+ stnw .D1T1 a15,*++a13(16)
+ stnw .D1T1 a18,*a16--(20)
+ stnw .D1T1 a21,*a19++(24)
+ stnw .D1T1 a24,*--a22[a23]
+ stnw .D1T1 a27,*++a25[a26]
+ stnw .D1T1 a30,*a28--[a29]
+ stnw .D1T1 a1,*a31++[a0]
+ stw .D1T1 a7,*a5
+ [b2] stw .D1T2 b11,*++a9
+ stw .D2T1 a15,*--b13
+ [!a2] stw .D2T2 b19,*b17++
+ stw .D1T1 a23,*a21--
+ [!b2] stw .D2T2 b27,*-b25[31]
+ stw .D1T1 a31,*+a29[0]
+ stw .D1T1 a2,*-a0(124)
+ stw .D1T1 a6,*-a4[a5]
+ stw .D1T1 a9,*+a7[a8]
+ stw .D1T1 a12,*--a10[11]
+ stw .D1T1 a15,*++a13(16)
+ stw .D1T1 a18,*a16--(20)
+ stw .D1T1 a21,*a19++(24)
+ stw .D1T1 a24,*--a22[a23]
+ stw .D1T1 a27,*++a25[a26]
+ stw .D1T1 a30,*a28--[a29]
+ stw .D1T1 a1,*a31++[a0]
+ [a0] stw .D2T1 a15,*+b14(131068)
+ stw .D2T2 b16,*+b15[32767]
+ sub .L1 a1,a2,a3
+ [b0] sub .L1X a4,b5,a6
+ [!a0] sub .L2 b7,b8,b9
+ sub .L2X b10,a11,b12
+ [!b0] sub .L1X b13,a14,a15
+ sub .L2X a16,b17,b18
+ .word 0x07b9a2f8
+ [a1] sub .L1 a19,a20,a23:a22
+ sub .L1X a24,b25,a27:a26
+ sub .L2 b28,b29,b31:b30
+ [b1] sub .L2X b0,a1,b3:b2
+ sub .L1X b4,a5,a7:a6
+ [!a1] sub .L2X a8,b9,b11:b10
+ .word 0x031486f8
+ sub .L1 -16,a12,a13
+ [!b1] sub .L1X 15,b14,a15
+ [a2] sub .L2 7,b16,b17
+ sub .L2X -9,a18,b19
+ sub .L1 -16,a21:a20,a23:a22
+ [b2] sub .L2 15,b25:b24,b27:b26
+ sub .S1 a1,a2,a3
+ [!a2] sub .S1X a4,b5,a6
+ [!b2] sub .S2 b7,b8,b9
+ sub .S2X b10,a11,b12
+ [a0] sub .S1X b13,a14,a15
+ sub .S2X a16,b17,b18
+ .word 0x07b5cd70
+ [b0] sub .S1 -16,a19,a20
+ sub .S1X 15,b21,a22
+ sub .S2 13,b23,b24
+ [!a0] sub .S2X -11,a25,b26
+ sub .D1 a27,a28,a29
+ [!b0] sub .D2 b30,b31,b0
+ [a1] sub .D1 a1,0,a2
+ sub .D2 b3,31,b4
+ sub .D1X a5,b6,a7
+ [b1] sub .D2X b8,a9,b10
+ .word 0x0398ab30
+ sub .L1 a5,16,a6
+ [a0] sub .L1X b11,-15,a30
+ sub .L2 b9,11,b10
+ sub .L2X a5,-14,b7
+ sub .L1 a3:a2,-5,a7:a6
+ [b0] sub .L2 b29:b28,7,b29:b28
+ sub .S1 a4,16,a11
+ sub .S1X b9,-13,a23
+ [!b0] sub .S2 b25,-15,b11
+ sub .S2X a1,4,b2
+ subab .D1 a1,a2,a3
+ [!a1] subab .D2 b4,b5,b6
+ subab .D1 a7,0,a8
+ [!b1] subab .D2 b9,31,b10
+ subabs4 .L1 a1,a2,a3
+ [a2] subabs4 .L1X a4,b5,a6
+ [b2] subabs4 .L2 b7,b8,b9
+ subabs4 .L2X b10,a11,b12
+ subah .D1 a1,a2,a3
+ [!a2] subah .D2 b4,b5,b6
+ [!b2] subah .D1 a7,0,a8
+ subah .D2 b9,31,b10
+ subaw .D1 a1,a2,a3
+ [a0] subaw .D2 b4,b5,b6
+ [b0] subaw .D1 a7,0,a8
+ subaw .D2 b9,31,b10
+ [!a0] subc .L1 a3,a4,a5
+ subc .L1X a6,b7,a8
+ subc .L2 b9,b10,b11
+ [!b0] subc .L2X b12,a13,b14
+ subdp .L1 a3:a2,a5:a4,a7:a6
+ [a1] subdp .L1X a9:a8,b11:b10,a13:a12
+ [b1] subdp .L2 b15:b14,b17:b16,b19:b18
+ subdp .L2X b21:b20,a23:a22,b25:b24
+ [!a1] subdp .L1X b27:b26,a29:a28,a31:a30
+ subdp .L2X a1:a0,b3:b2,b5:b4
+ .word 0x0f7343b8
+ subdp .S1 a3:a2,a5:a4,a7:a6
+ [a1] subdp .S1X a9:a8,b11:b10,a13:a12
+ [b1] subdp .S2 b15:b14,b17:b16,b19:b18
+ subdp .S2X b21:b20,a23:a22,b25:b24
+ [!a1] subdp .S1X b27:b26,a29:a28,a31:a30
+ subdp .S2X a1:a0,b3:b2,b5:b4
+ .word 0x0f6b8ef8
+ subsp .L1 a3,a5,a7
+ [a1] subsp .L1X a9,b11,a13
+ [b1] subsp .L2 b15,b17,b19
+ subsp .L2X b21,a23,b25
+ [!a1] subsp .L1X b27,a29,a31
+ subsp .L2X a1,b3,b5
+ .word 0x0ff762b8
+ subsp .S1 a3,a5,a7
+ [!b1] subsp .S1X a9,b11,a13
+ [a2] subsp .S2 b15,b17,b19
+ subsp .S2X b21,a23,b25
+ [b2] subsp .S1X b27,a29,a31
+ subsp .S2X a1,b3,b5
+ .word 0x0fefaeb8
+ subu .L1 a2,a3,a5:a4
+ [!a2] subu .L1X a6,b7,a9:a8
+ [!b2] subu .L2 b10,b11,b13:b12
+ subu .L2X b14,a15,b17:b16
+ [a0] subu .L1X b18,a19,a21:a20
+ subu .L2X a22,b23,b25:b24
+ .word 0x0a4e47f8
+ sub2 .L1 a1,a2,a3
+ [b0] sub2 .L1X a4,b5,a6
+ [!a0] sub2 .L2 b7,b8,b9
+ sub2 .L2X b10,a11,b12
+ sub2 .S1 a1,a2,a3
+ [!b0] sub2 .S1X a4,b5,a6
+ [a1] sub2 .S2 b7,b8,b9
+ sub2 .S2X b10,a11,b12
+ sub2 .D1 a1,a2,a3
+ [b1] sub2 .D1X a4,b5,a6
+ [!a1] sub2 .D2 b7,b8,b9
+ sub2 .D2X b10,a11,b12
+ sub4 .L1 a1,a2,a3
+ [!b1] sub4 .L1X a4,b5,a6
+ [a2] sub4 .L2 b7,b8,b9
+ sub4 .L2X b10,a11,b12
+ swap2 .L1 a3,a7
+ [b2] swap2 .L2 b9,b11
+ [!a2] swap2 .S1 a13,a15
+ swap2 .S2 b23,b29
+ [!b2] swap4 .L1 a1,a2
+ swap4 .L1X b3,a4
+ swap4 .L2 b5,b6
+ [a0] swap4 .L2X a7,b8
+ swe
+ swenr
+ unpkhu4 .L1 a1,a2
+ [b0] unpkhu4 .L1X b3,a4
+ [!a0] unpkhu4 .L2 b5,b6
+ unpkhu4 .L2X a7,b8
+ unpkhu4 .S1 a1,a2
+ [!b0] unpkhu4 .S1X b3,a4
+ [a1] unpkhu4 .S2 b5,b6
+ unpkhu4 .S2X a7,b8
+ unpklu4 .L1 a1,a2
+ [b1] unpklu4 .L1X b3,a4
+ [!a1] unpklu4 .L2 b5,b6
+ unpklu4 .L2X a7,b8
+ unpklu4 .S1 a1,a2
+ [!b1] unpklu4 .S1X b3,a4
+ [a2] unpklu4 .S2 b5,b6
+ unpklu4 .S2X a7,b8
+ xor .L1 a1,a2,a3
+ [b2] xor .L1X a4,b5,a6
+ [!a2] xor .L2 b7,b8,b9
+ xor .L2X b10,a11,b12
+ [!b2] xor .L1 -16,a13,a14
+ xor .L1X 15,b15,a16
+ xor .L2 3,b17,b18
+ [a0] xor .L2X -12,a19,b20
+ xor .S1 a1,a2,a3
+ [b0] xor .S1X a4,b5,a6
+ [!a0] xor .S2 b7,b8,b9
+ xor .S2X b10,a11,b12
+ [!b0] xor .S1 -16,a13,a14
+ xor .S1X 15,b15,a16
+ xor .S2 3,b17,b18
+ [a1] xor .S2X -12,a19,b20
+ xor .D1 a1,a2,a3
+ [b0] xor .D1X a4,b5,a6
+ [!a0] xor .D2 b7,b8,b9
+ xor .D2X b10,a11,b12
+ [!b0] xor .D1 -16,a13,a14
+ xor .D1X 15,b15,a16
+ xor .D2 3,b17,b18
+ [a1] xor .D2X -12,a19,b20
+ xormpy .M1 a1,a2,a3
+ xormpy .M1X a4,b5,a6
+ xormpy .M2 b7,b8,b9
+ xormpy .M2X b10,a11,b12
+ xpnd2 .M1 a13,a14
+ [b1] xpnd2 .M1X b15,a16
+ [!a1] xpnd2 .M2 b17,b18
+ xpnd2 .M2X a19,b20
+ xpnd4 .M1 a13,a14
+ [!b1] xpnd4 .M1X b15,a16
+ [a2] xpnd4 .M2 b17,b18
+ xpnd4 .M2X a19,b20
+ zero .L1 a1
+ [b2] zero .L2 b2
+ [!a2] zero .L1 a5:a4
+ zero .L2 b7:b6
+ zero .D1 a8
+ [!b2] zero .D2 b9
+ [a0] zero .S1 a10
+ zero .S2 b11
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X parallel instructions, big-endian
+#as: -march=c674x -mbig-endian
+#source: insns-parallel.s
+
+.*: *file format elf32-tic6x-be
+
+
+Disassembly of section \.text:
+0+00 <[^>]*> 00008001[ \t]+nop 5
+0+04 <[^>]*> 00000000[ \t]+\|\| nop 1
+0+08 <[^>]*> 00006001[ \t]+nop 4
+0+0c <[^>]*> 00006001[ \t]+\|\| nop 4
+0+10 <[^>]*> 00006000[ \t]+\|\| nop 4
+[ \t]*\.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X parallel instructions, little-endian
+#as: -march=c674x -mlittle-endian
+#source: insns-parallel.s
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+0+00 <[^>]*> 00008001[ \t]+nop 5
+0+04 <[^>]*> 00000000[ \t]+\|\| nop 1
+0+08 <[^>]*> 00006001[ \t]+nop 4
+0+0c <[^>]*> 00006001[ \t]+\|\| nop 4
+0+10 <[^>]*> 00006000[ \t]+\|\| nop 4
+[ \t]*\.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X parallel instructions, multiple sections
+#as: -march=c674x -mlittle-endian
+#source: insns-parallel-multi.s
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text\.f1:
+0+00 <[^>]*> 00008001[ \t]+nop 5
+0+04 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+08 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+0c <[^>]*> 00000001[ \t]+\|\| nop 1
+0+10 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+14 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+18 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+1c <[^>]*> 00000000[ \t]+\|\| nop 1
+
+Disassembly of section \.text\.f2:
+0+00 <[^>]*> 00006001[ \t]+nop 4
+0+04 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+08 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+0c <[^>]*> 00000001[ \t]+\|\| nop 1
+0+10 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+14 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+18 <[^>]*> 00000001[ \t]+\|\| nop 1
+0+1c <[^>]*> 00000000[ \t]+\|\| nop 1
--- /dev/null
+# Test parallel instructions and section switching.
+.nocmp
+.section .text.f1,"ax",%progbits
+.globl f1
+f1:
+ nop 5
+.section .text.f2,"ax",%progbits
+.globl f2
+f2:
+ nop 4
+.section .text.f1,"ax",%progbits
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+.section .text.f2,"ax",%progbits
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+.section .text.f1,"ax",%progbits
+|| nop
+.section .text.f2,"ax",%progbits
+|| nop
--- /dev/null
+# Test parallel instructions.
+.text
+.nocmp
+.globl f
+f:
+ nop 5
+|| nop
+ nop 4
+|| nop 4
+|| nop 4
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X predicates
+#as: -march=c674x -mlittle-endian
+#source: insns-predicate.s
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+0+00 <[^>]*> c1880359[ \t]+\[a0\] abs \.L1 a2,a3
+0+04 <[^>]*> c290035a[ \t]+\|\| \[a0\] abs \.L2 b4,b5
+0+08 <[^>]*> d3980358[ \t]+\[!a0\] abs \.L1 a6,a7
+0+0c <[^>]*> d4a0035a[ \t]+\[!a0\] abs \.L2 b8,b9
+0+10 <[^>]*> 25a80358[ \t]+\[b0\] abs \.L1 a10,a11
+0+14 <[^>]*> 26b0035a[ \t]+\[b0\] abs \.L2 b12,b13
+0+18 <[^>]*> 37b80358[ \t]+\[!b0\] abs \.L1 a14,a15
+0+1c <[^>]*> 38c0035a[ \t]+\[!b0\] abs \.L2 b16,b17
+0+20 <[^>]*> 89c80358[ \t]+\[a1\] abs \.L1 a18,a19
+0+24 <[^>]*> 9ad0035a[ \t]+\[!a1\] abs \.L2 b20,b21
+0+28 <[^>]*> abd80358[ \t]+\[a2\] abs \.L1 a22,a23
+0+2c <[^>]*> bce0035a[ \t]+\[!a2\] abs \.L2 b24,b25
+0+30 <[^>]*> 4de80358[ \t]+\[b1\] abs \.L1 a26,a27
+0+34 <[^>]*> 5ef0035a[ \t]+\[!b1\] abs \.L2 b28,b29
+0+38 <[^>]*> 6ff80358[ \t]+\[b2\] abs \.L1 a30,a31
+0+3c <[^>]*> 738c035a[ \t]+\[!b2\] abs \.L2 b3,b7
--- /dev/null
+# Test predicates.
+.text
+.nocmp
+.globl f
+f:
+ [a0] abs .L1 a2,a3
+|| [A0] abs .L2 b4,b5
+ [!a0] abs .L1 a6,a7
+ [!A0] abs .L2 b8,b9
+ [b0] abs .L1 a10,a11
+ [B0] abs .L2 b12,b13
+ [!b0] abs .L1 a14,a15
+ [!B0] abs .L2 b16,b17
+ [a1] abs .L1 a18,a19
+ [!A1] abs .L2 b20,b21
+ [A2] abs .L1 a22,a23
+ [!a2] abs .L2 b24,b25
+ [b1] abs .L1 a26,a27
+ [!B1] abs .L2 b28,b29
+ [B2] abs .L1 a30,a31
+ [!b2] abs .L2 b3,b7
--- /dev/null
+#name: C6X bad parallel syntax
+#error-output: parallel-bad-1.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:6: Error: '||' not followed by instruction
+[^:]*:8: Error: '||' not followed by instruction
+[^:]*:10: Error: multiple '||' on same line
+[^:]*:12: Error: '||' not followed by instruction
+[^:]*:14: Error: '||' not followed by instruction
+[^:]*:16: Error: multiple '||' on same line
+[^:]*:16: Error: '||^' without previous SPMASK
+[^:]*:18: Error: multiple '||' on same line
+[^:]*:18: Error: '||^' without previous SPMASK
+[^:]*:20: Error: multiple '||' on same line
+[^:]*:20: Error: '||^' without previous SPMASK
+[^:]*:22: Error: label after '||'
+[^:]*:24: Error: label after '||'
+[^:]*:26: Error: '||' after predicate
+[^:]*:26: Error: instruction 'nop' cannot be predicated
+[^:]*:28: Error: '||' after predicate
+[^:]*:28: Error: instruction 'nop' cannot be predicated
+[^:]*:32: Error: '||' not followed by instruction
--- /dev/null
+# Test bad syntax for parallel operations.
+.text
+.globl f
+f:
+ nop
+ || ; no instruction
+ nop
+ || .word 0
+ nop
+ || || nop
+ nop
+ ||^ ; no instruction
+ nop
+ ||^ .word 0
+ nop
+ ||^ || nop
+ nop
+ || ||^ nop
+ nop
+ ||^ ||^ nop
+ nop
+ || label:
+ nop
+ ||^ label2:
+ nop
+ [A1] || nop
+ nop
+ [B1] ||^ nop
+ nop
+# End with this one, to be sure errors detected at new-line are
+# detected at end-of-file.
+ || .word 0
--- /dev/null
+#name: C6X bad parallel positioning
+#error-output: parallel-bad-2.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: parallel instruction not following another instruction
+[^:]*:8: Error: parallel instruction not following another instruction
+[^:]*:11: Error: label not at start of execute packet
--- /dev/null
+# Test bad positions for parallel operations.
+.text
+.globl f
+f:
+ || nop
+ nop
+ .word 0
+ || nop
+ nop
+label:
+ || nop
--- /dev/null
+#name: C6X too many parallel instructions
+#error-output: parallel-bad-3.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:13: Error: too many instructions in execute packet
--- /dev/null
+# Test too many instructions in execute packet.
+.text
+.globl f
+f:
+ nop
+ || nop
+ || nop
+ || nop
+ || nop
+ || nop
+ || nop
+ || nop
+ || nop
--- /dev/null
+#name: C6X too many parallel instructions, multiple sections
+#error-output: parallel-bad-4.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:28: Error: too many instructions in execute packet
+[^:]*:30: Error: too many instructions in execute packet
--- /dev/null
+# Test too many instructions in execute packet, with section switching.
+.nocmp
+.section .text.f1,"ax",%progbits
+.globl f1
+f1:
+ nop 5
+.section .text.f2,"ax",%progbits
+.globl f2
+f2:
+ nop 4
+.section .text.f1,"ax",%progbits
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+.section .text.f2,"ax",%progbits
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+|| nop
+.section .text.f1,"ax",%progbits
+|| nop
+.section .text.f2,"ax",%progbits
+|| nop
--- /dev/null
+#name: C6X bad predicate syntax
+#error-output: predicate-bad-1.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: junk at end of line, first unrecognized character is `\['
+[^:]*:6: Error: predicate not followed by instruction
+[^:]*:7: Error: bad predicate '\[unknown\]'
+[^:]*:8: Error: bad predicate '\[a3\]'
+[^:]*:9: Error: bad predicate '\[b500\]'
+[^:]*:10: Error: bad predicate '\[\]'
+[^:]*:11: Error: bad predicate '\[!\]'
+[^:]*:12: Error: bad predicate '\[!a\]'
+[^:]*:13: Error: bad predicate '\[!A\]'
+[^:]*:14: Error: bad predicate '\[!b\]'
+[^:]*:15: Error: bad predicate '\[!B\]'
+[^:]*:16: Error: bad predicate '\[!x\]'
+[^:]*:17: Error: bad predicate '\[a\]'
+[^:]*:18: Error: bad predicate '\[B\]'
+[^:]*:19: Error: multiple predicates on same line
+[^:]*:19: Error: instruction 'nop' cannot be predicated
+[^:]*:20: Error: predicate not followed by instruction
+[^:]*:21: Error: label after predicate
+[^:]*:22: Error: predicate not followed by instruction
--- /dev/null
+# Test bad syntax for predicates.
+.text
+.globl f
+f:
+ [not a predicate
+ [A1] ; no instruction
+ [unknown] nop
+ [a3] nop
+ [b500] nop
+ [] nop
+ [!] nop
+ [!a] nop
+ [!A] nop
+ [!b] nop
+ [!B] nop
+ [!x] nop
+ [a] nop
+ [B] nop
+ [a1] [!B1] nop
+ [A2] .word 0
+ [!B2] label:
+ [!A1] .word 1
--- /dev/null
+#name: C6X bad predicates for architecture
+#as: -march=c62x
+#error-output: predicate-bad-2.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: predication on A0 not supported on this architecture
+[^:]*:5: Error: instruction 'nop' cannot be predicated
+[^:]*:6: Error: instruction 'nop' cannot be predicated
+[^:]*:7: Error: instruction 'nop' cannot be predicated
+[^:]*:8: Error: instruction 'nop' cannot be predicated
+[^:]*:9: Error: instruction 'nop' cannot be predicated
+[^:]*:10: Error: instruction 'nop' cannot be predicated
+[^:]*:11: Error: predication on A0 not supported on this architecture
+[^:]*:11: Error: instruction 'nop' cannot be predicated
+[^:]*:12: Error: instruction 'nop' cannot be predicated
+[^:]*:13: Error: instruction 'nop' cannot be predicated
+[^:]*:14: Error: instruction 'nop' cannot be predicated
+[^:]*:15: Error: instruction 'nop' cannot be predicated
+[^:]*:16: Error: instruction 'nop' cannot be predicated
+[^:]*:18: Error: instruction 'nop' cannot be predicated
+[^:]*:19: Error: instruction 'nop' cannot be predicated
+[^:]*:20: Error: instruction 'nop' cannot be predicated
+[^:]*:21: Error: instruction 'nop' cannot be predicated
+[^:]*:22: Error: instruction 'nop' cannot be predicated
+[^:]*:23: Error: instruction 'nop' cannot be predicated
+[^:]*:24: Error: instruction 'nop' cannot be predicated
+[^:]*:25: Error: instruction 'nop' cannot be predicated
+[^:]*:26: Error: instruction 'nop' cannot be predicated
+[^:]*:27: Error: instruction 'nop' cannot be predicated
+[^:]*:28: Error: instruction 'nop' cannot be predicated
+[^:]*:29: Error: instruction 'nop' cannot be predicated
+[^:]*:31: Error: instruction 'nop' cannot be predicated
+[^:]*:32: Error: instruction 'nop' cannot be predicated
+[^:]*:33: Error: instruction 'nop' cannot be predicated
+[^:]*:34: Error: instruction 'nop' cannot be predicated
+[^:]*:35: Error: instruction 'nop' cannot be predicated
+[^:]*:36: Error: instruction 'nop' cannot be predicated
+[^:]*:37: Error: instruction 'nop' cannot be predicated
+[^:]*:38: Error: instruction 'nop' cannot be predicated
+[^:]*:39: Error: instruction 'nop' cannot be predicated
+[^:]*:40: Error: instruction 'nop' cannot be predicated
+[^:]*:41: Error: instruction 'nop' cannot be predicated
+[^:]*:42: Error: instruction 'nop' cannot be predicated
+[^:]*:44: Error: predication on A0 not supported on this architecture
+[^:]*:44: Error: instruction 'nop' cannot be predicated
+[^:]*:45: Error: instruction 'nop' cannot be predicated
+[^:]*:46: Error: instruction 'nop' cannot be predicated
+[^:]*:47: Error: instruction 'nop' cannot be predicated
+[^:]*:48: Error: instruction 'nop' cannot be predicated
+[^:]*:49: Error: instruction 'nop' cannot be predicated
+[^:]*:50: Error: predication on A0 not supported on this architecture
+[^:]*:50: Error: instruction 'nop' cannot be predicated
+[^:]*:51: Error: instruction 'nop' cannot be predicated
+[^:]*:52: Error: instruction 'nop' cannot be predicated
+[^:]*:53: Error: instruction 'nop' cannot be predicated
+[^:]*:54: Error: instruction 'nop' cannot be predicated
+[^:]*:55: Error: instruction 'nop' cannot be predicated
+[^:]*:57: Error: predication on A0 not supported on this architecture
+[^:]*:57: Error: instruction 'nop' cannot be predicated
+[^:]*:58: Error: instruction 'nop' cannot be predicated
+[^:]*:59: Error: instruction 'nop' cannot be predicated
+[^:]*:60: Error: instruction 'nop' cannot be predicated
+[^:]*:61: Error: instruction 'nop' cannot be predicated
+[^:]*:62: Error: instruction 'nop' cannot be predicated
+[^:]*:63: Error: predication on A0 not supported on this architecture
+[^:]*:63: Error: instruction 'nop' cannot be predicated
+[^:]*:64: Error: instruction 'nop' cannot be predicated
+[^:]*:65: Error: instruction 'nop' cannot be predicated
+[^:]*:66: Error: instruction 'nop' cannot be predicated
+[^:]*:67: Error: instruction 'nop' cannot be predicated
+[^:]*:68: Error: instruction 'nop' cannot be predicated
+[^:]*:70: Error: instruction 'nop' cannot be predicated
+[^:]*:71: Error: instruction 'nop' cannot be predicated
+[^:]*:72: Error: instruction 'nop' cannot be predicated
+[^:]*:73: Error: instruction 'nop' cannot be predicated
+[^:]*:74: Error: instruction 'nop' cannot be predicated
+[^:]*:75: Error: instruction 'nop' cannot be predicated
+[^:]*:76: Error: instruction 'nop' cannot be predicated
+[^:]*:77: Error: instruction 'nop' cannot be predicated
+[^:]*:78: Error: instruction 'nop' cannot be predicated
+[^:]*:79: Error: instruction 'nop' cannot be predicated
+[^:]*:80: Error: instruction 'nop' cannot be predicated
+[^:]*:81: Error: instruction 'nop' cannot be predicated
+[^:]*:83: Error: predication on A0 not supported on this architecture
+[^:]*:83: Error: instruction 'nop' cannot be predicated
+[^:]*:84: Error: instruction 'nop' cannot be predicated
+[^:]*:85: Error: instruction 'nop' cannot be predicated
+[^:]*:86: Error: instruction 'nop' cannot be predicated
+[^:]*:87: Error: instruction 'nop' cannot be predicated
+[^:]*:88: Error: instruction 'nop' cannot be predicated
+[^:]*:89: Error: predication on A0 not supported on this architecture
+[^:]*:89: Error: instruction 'nop' cannot be predicated
+[^:]*:90: Error: instruction 'nop' cannot be predicated
+[^:]*:91: Error: instruction 'nop' cannot be predicated
+[^:]*:92: Error: instruction 'nop' cannot be predicated
+[^:]*:93: Error: instruction 'nop' cannot be predicated
+[^:]*:94: Error: instruction 'nop' cannot be predicated
--- /dev/null
+# Test predicates allowed or disallowed depending on the architecture.
+.text
+.globl f
+f:
+ [A0] nop
+ [A1] nop
+ [A2] nop
+ [B0] nop
+ [B1] nop
+ [B2] nop
+ [!A0] nop
+ [!A1] nop
+ [!A2] nop
+ [!B0] nop
+ [!B1] nop
+ [!B2] nop
+.arch c64x
+ [A0] nop
+ [A1] nop
+ [A2] nop
+ [B0] nop
+ [B1] nop
+ [B2] nop
+ [!A0] nop
+ [!A1] nop
+ [!A2] nop
+ [!B0] nop
+ [!B1] nop
+ [!B2] nop
+.arch c64x+
+ [A0] nop
+ [A1] nop
+ [A2] nop
+ [B0] nop
+ [B1] nop
+ [B2] nop
+ [!A0] nop
+ [!A1] nop
+ [!A2] nop
+ [!B0] nop
+ [!B1] nop
+ [!B2] nop
+.arch c67x
+ [A0] nop
+ [A1] nop
+ [A2] nop
+ [B0] nop
+ [B1] nop
+ [B2] nop
+ [!A0] nop
+ [!A1] nop
+ [!A2] nop
+ [!B0] nop
+ [!B1] nop
+ [!B2] nop
+.arch c67x+
+ [A0] nop
+ [A1] nop
+ [A2] nop
+ [B0] nop
+ [B1] nop
+ [B2] nop
+ [!A0] nop
+ [!A1] nop
+ [!A2] nop
+ [!B0] nop
+ [!B1] nop
+ [!B2] nop
+.arch c674x
+ [A0] nop
+ [A1] nop
+ [A2] nop
+ [B0] nop
+ [B1] nop
+ [B2] nop
+ [!A0] nop
+ [!A1] nop
+ [!A2] nop
+ [!B0] nop
+ [!B1] nop
+ [!B2] nop
+.arch c62x
+ [A0] nop
+ [A1] nop
+ [A2] nop
+ [B0] nop
+ [B1] nop
+ [B2] nop
+ [!A0] nop
+ [!A1] nop
+ [!A2] nop
+ [!B0] nop
+ [!B1] nop
+ [!B2] nop
--- /dev/null
+#name: C6X bad predicates for instructions
+#as: -march=c674x
+#error-output: predicate-bad-3.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: instruction 'nop' cannot be predicated
+[^:]*:6: Error: instruction 'nop' cannot be predicated
+[^:]*:7: Error: instruction 'addab' cannot be predicated
+[^:]*:8: Error: instruction 'addah' cannot be predicated
+[^:]*:9: Error: instruction 'addaw' cannot be predicated
+[^:]*:10: Error: instruction 'callp' cannot be predicated
+[^:]*:11: Error: instruction 'addsub' cannot be predicated
+[^:]*:12: Error: instruction 'addsub2' cannot be predicated
+[^:]*:13: Error: instruction 'cmpy' cannot be predicated
+[^:]*:14: Error: instruction 'cmpyr' cannot be predicated
+[^:]*:15: Error: instruction 'cmpyr1' cannot be predicated
+[^:]*:16: Error: instruction 'ddotp4' cannot be predicated
+[^:]*:17: Error: instruction 'ddotph2' cannot be predicated
+[^:]*:18: Error: instruction 'ddotph2r' cannot be predicated
+[^:]*:19: Error: instruction 'ddotpl2' cannot be predicated
+[^:]*:20: Error: instruction 'ddotpl2r' cannot be predicated
+[^:]*:21: Error: instruction 'dint' cannot be predicated
+[^:]*:22: Error: instruction 'dpack2' cannot be predicated
+[^:]*:23: Error: instruction 'dpackx2' cannot be predicated
+[^:]*:24: Error: instruction 'gmpy' cannot be predicated
+[^:]*:25: Error: instruction 'idle' cannot be predicated
+[^:]*:26: Error: instruction 'mpy2ir' cannot be predicated
+[^:]*:27: Error: instruction 'rint' cannot be predicated
+[^:]*:28: Error: instruction 'rpack2' cannot be predicated
+[^:]*:29: Error: instruction 'saddsub' cannot be predicated
+[^:]*:30: Error: instruction 'saddsub2' cannot be predicated
+[^:]*:31: Error: instruction 'shfl3' cannot be predicated
+[^:]*:32: Error: instruction 'smpy32' cannot be predicated
+[^:]*:33: Error: instruction 'swe' cannot be predicated
+[^:]*:34: Error: instruction 'swenr' cannot be predicated
+[^:]*:35: Error: instruction 'xormpy' cannot be predicated
+[^:]*:36: Error: instruction 'spmask' cannot be predicated
+[^:]*:37: Error: instruction 'spmaskr' cannot be predicated
+[^:]*:39: Error: instruction 'spkernel' cannot be predicated
+[^:]*:40: Error: instruction 'spkernelr' cannot be predicated
--- /dev/null
+# Test instructions that cannot be predicated.
+.text
+.globl f
+f:
+ [A1] nop
+ [!B1] nop 2
+ [a2] addab .D2 b14,32,b29
+ [b0] addah .D1X b14,32,a5
+ [!b0] addaw .D2 b14,32,b7
+ [a1] callp .S1 f,a3
+ [b1] addsub .L1 a1,a2,a5:a4
+ [b2] addsub2 .L2 b1,b2,b5:b4
+ [!a2] cmpy .M1 a1,a2,a5:a4
+ [!b2] cmpyr .M1 a1,a2,a5
+ [!a1] cmpyr1 .M1 a1,a2,a5
+ [!b1] ddotp4 .M2 b0,b1,b3:b2
+ [!a0] ddotph2 .M2 b1:b0,b2,b5:b4
+ [!a0] ddotph2r .M2 b1:b0,b2,b5
+ [!a0] ddotpl2 .M2 b1:b0,b2,b5:b4
+ [!a0] ddotpl2r .M2 b1:b0,b2,b5
+ [!b0] dint
+ [a0] dpack2 .L1 a0,a1,a3:a2
+ [b0] dpackx2 .L1 a0,a1,a3:a2
+ [b1] gmpy .M1 a1,a2,a3
+ [a1] idle
+ [b2] mpy2ir .M1 a1,a2,a5:a4
+ [a0] rint
+ [b0] rpack2 .S1 a0,a1,a2
+ [!b1] saddsub .L1 a0,a0,a1:a0
+ [!b2] saddsub2 .L1 a0,a0,a1:a0
+ [a0] shfl3 .L1 a0,a0,a1:a0
+ [b1] smpy32 .M1 a0,a0,a0
+ [a1] swe
+ [!a2] swenr
+ [b0] xormpy .M1 a0,a1,a2
+ [a1] spmask
+ [b1] spmaskr
+ sploop 1
+ [a0] spkernel
+ [b0] spkernelr
--- /dev/null
+#name: C6X bad relocations 1
+#error-output: reloc-bad-1.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:8: Error: can't resolve `a' \{\*UND\* section\} - `b' \{\*UND\* section\}
--- /dev/null
+# Test expressions not representable by relocations.
+# Just one test so the resolution-time error isn't suppressed by other
+# errors.
+.globl a
+.globl b
+.data
+d:
+ .word a-b
--- /dev/null
+#name: C6X bad relocations 2
+#error-output: reloc-bad-2.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:6: Error: \$DSBT_INDEX not supported in this context
+[^:]*:7: Error: \$GOT not supported in this context
+[^:]*:8: Error: \$DPR_GOT not supported in this context
+[^:]*:9: Error: \$DPR_BYTE not supported in this context
+[^:]*:10: Error: \$DPR_HWORD not supported in this context
+[^:]*:11: Error: \$DPR_WORD not supported in this context
+[^:]*:16: Error: \$DSBT_INDEX not supported in this context
+[^:]*:17: Error: \$GOT not supported in this context
+[^:]*:18: Error: \$DPR_GOT not supported in this context
+[^:]*:19: Error: \$DPR_BYTE not supported in this context
+[^:]*:20: Error: \$DPR_HWORD not supported in this context
+[^:]*:21: Error: \$DPR_WORD not supported in this context
+[^:]*:22: Error: \$DSBT_INDEX not supported in this context
+[^:]*:23: Error: \$GOT not supported in this context
+[^:]*:24: Error: \$DPR_GOT not supported in this context
+[^:]*:25: Error: \$DPR_BYTE not supported in this context
+[^:]*:26: Error: \$DPR_HWORD not supported in this context
+[^:]*:27: Error: \$DPR_WORD not supported in this context
+[^:]*:28: Error: \$DPR_GOT not supported in this context
+[^:]*:29: Error: \$DPR_BYTE not supported in this context
+[^:]*:30: Error: \$DPR_HWORD not supported in this context
+[^:]*:31: Error: \$DPR_WORD not supported in this context
+[^:]*:32: Error: \$DSBT_INDEX not supported in this context
+[^:]*:33: Error: \$GOT not supported in this context
+[^:]*:34: Error: \$DPR_GOT not supported in this context
+[^:]*:35: Error: \$DPR_HWORD not supported in this context
+[^:]*:36: Error: \$DPR_WORD not supported in this context
+[^:]*:37: Error: \$DSBT_INDEX not supported in this context
+[^:]*:38: Error: \$GOT not supported in this context
+[^:]*:39: Error: \$DPR_GOT not supported in this context
+[^:]*:40: Error: \$DPR_HWORD not supported in this context
+[^:]*:41: Error: \$DPR_WORD not supported in this context
+[^:]*:42: Error: \$DSBT_INDEX not supported in this context
+[^:]*:43: Error: \$GOT not supported in this context
+[^:]*:44: Error: \$DSBT_INDEX not supported in this context
+[^:]*:45: Error: \$GOT not supported in this context
+[^:]*:46: Error: \$DSBT_INDEX not supported in this context
+[^:]*:47: Error: \$GOT not supported in this context
+[^:]*:48: Error: \$DSBT_INDEX not supported in this context
+[^:]*:49: Error: \$GOT not supported in this context
+[^:]*:50: Error: \$DPR_GOT not supported in this context
+[^:]*:51: Error: \$DPR_BYTE not supported in this context
+[^:]*:52: Error: \$DPR_HWORD not supported in this context
+[^:]*:53: Error: \$DPR_WORD not supported in this context
+[^:]*:54: Error: \$DSBT_INDEX not supported in this context
+[^:]*:55: Error: \$GOT not supported in this context
+[^:]*:56: Error: \$DPR_GOT not supported in this context
+[^:]*:57: Error: \$DPR_BYTE not supported in this context
+[^:]*:58: Error: \$DPR_HWORD not supported in this context
+[^:]*:59: Error: \$DPR_WORD not supported in this context
+[^:]*:60: Error: \$DSBT_INDEX not supported in this context
+[^:]*:61: Error: \$GOT not supported in this context
+[^:]*:62: Error: \$DPR_GOT not supported in this context
+[^:]*:63: Error: \$DPR_BYTE not supported in this context
+[^:]*:64: Error: \$DPR_HWORD not supported in this context
+[^:]*:65: Error: \$DPR_WORD not supported in this context
+[^:]*:66: Error: \$DSBT_INDEX not supported in this context
+[^:]*:67: Error: \$GOT not supported in this context
+[^:]*:68: Error: \$DPR_GOT not supported in this context
+[^:]*:69: Error: \$DPR_BYTE not supported in this context
+[^:]*:70: Error: \$DPR_HWORD not supported in this context
+[^:]*:71: Error: \$DPR_WORD not supported in this context
+[^:]*:72: Error: \$DSBT_INDEX not supported in this context
+[^:]*:73: Error: \$GOT not supported in this context
+[^:]*:74: Error: \$DPR_GOT not supported in this context
+[^:]*:75: Error: \$DPR_BYTE not supported in this context
+[^:]*:76: Error: \$DPR_HWORD not supported in this context
+[^:]*:77: Error: \$DPR_WORD not supported in this context
+[^:]*:78: Error: \$DSBT_INDEX not supported in this context
+[^:]*:79: Error: \$GOT not supported in this context
+[^:]*:80: Error: \$DPR_GOT not supported in this context
+[^:]*:81: Error: \$DPR_BYTE not supported in this context
+[^:]*:82: Error: \$DPR_HWORD not supported in this context
+[^:]*:83: Error: \$DPR_WORD not supported in this context
+[^:]*:84: Error: \$DSBT_INDEX not supported in this context
+[^:]*:85: Error: \$GOT not supported in this context
+[^:]*:86: Error: \$DPR_GOT not supported in this context
+[^:]*:87: Error: \$DPR_BYTE not supported in this context
+[^:]*:88: Error: \$DPR_HWORD not supported in this context
+[^:]*:89: Error: \$DPR_WORD not supported in this context
+[^:]*:90: Error: \$DSBT_INDEX not supported in this context
+[^:]*:91: Error: \$GOT not supported in this context
+[^:]*:92: Error: \$DPR_GOT not supported in this context
+[^:]*:93: Error: \$DPR_BYTE not supported in this context
+[^:]*:94: Error: \$DPR_HWORD not supported in this context
+[^:]*:95: Error: \$DPR_WORD not supported in this context
+[^:]*:96: Error: \$DSBT_INDEX not supported in this context
+[^:]*:97: Error: \$GOT not supported in this context
+[^:]*:98: Error: \$DPR_GOT not supported in this context
+[^:]*:99: Error: \$DPR_BYTE not supported in this context
+[^:]*:100: Error: \$DPR_HWORD not supported in this context
+[^:]*:101: Error: \$DPR_WORD not supported in this context
+[^:]*:102: Error: \$DSBT_INDEX not supported in this context
+[^:]*:103: Error: \$GOT not supported in this context
+[^:]*:104: Error: \$DPR_GOT not supported in this context
+[^:]*:105: Error: \$DPR_BYTE not supported in this context
+[^:]*:106: Error: \$DPR_HWORD not supported in this context
+[^:]*:107: Error: \$DPR_WORD not supported in this context
+[^:]*:108: Error: \$DSBT_INDEX not supported in this context
+[^:]*:109: Error: \$GOT not supported in this context
+[^:]*:110: Error: \$DPR_GOT not supported in this context
+[^:]*:111: Error: \$DPR_BYTE not supported in this context
+[^:]*:112: Error: \$DPR_HWORD not supported in this context
+[^:]*:113: Error: \$DPR_WORD not supported in this context
+[^:]*:114: Error: \$DSBT_INDEX not supported in this context
+[^:]*:115: Error: \$GOT not supported in this context
+[^:]*:116: Error: \$DPR_GOT not supported in this context
+[^:]*:117: Error: \$DPR_BYTE not supported in this context
+[^:]*:118: Error: \$DPR_HWORD not supported in this context
+[^:]*:119: Error: \$DPR_WORD not supported in this context
+[^:]*:120: Error: \$DSBT_INDEX not supported in this context
+[^:]*:121: Error: \$GOT not supported in this context
+[^:]*:122: Error: \$DPR_GOT not supported in this context
+[^:]*:123: Error: \$DPR_BYTE not supported in this context
+[^:]*:124: Error: \$DPR_HWORD not supported in this context
+[^:]*:125: Error: \$DPR_WORD not supported in this context
+[^:]*:126: Error: \$DSBT_INDEX not supported in this context
+[^:]*:127: Error: \$GOT not supported in this context
+[^:]*:128: Error: \$DPR_GOT not supported in this context
+[^:]*:129: Error: \$DPR_BYTE not supported in this context
+[^:]*:130: Error: \$DPR_HWORD not supported in this context
+[^:]*:131: Error: \$DPR_WORD not supported in this context
+[^:]*:132: Error: \$DSBT_INDEX not supported in this context
+[^:]*:133: Error: \$GOT not supported in this context
+[^:]*:134: Error: \$DPR_GOT not supported in this context
+[^:]*:135: Error: \$DPR_BYTE not supported in this context
+[^:]*:136: Error: \$DPR_HWORD not supported in this context
+[^:]*:137: Error: \$DPR_WORD not supported in this context
+[^:]*:138: Error: \$DPR_GOT not supported in this context
+[^:]*:139: Error: \$DPR_BYTE not supported in this context
+[^:]*:140: Error: \$DPR_HWORD not supported in this context
+[^:]*:141: Error: \$DPR_WORD not supported in this context
+[^:]*:142: Error: \$DSBT_INDEX not supported in this context
+[^:]*:143: Error: \$GOT not supported in this context
+[^:]*:144: Error: \$DPR_GOT not supported in this context
+[^:]*:145: Error: \$DPR_BYTE not supported in this context
+[^:]*:146: Error: \$DPR_HWORD not supported in this context
+[^:]*:147: Error: \$DPR_WORD not supported in this context
+[^:]*:148: Error: \$DSBT_INDEX not supported in this context
+[^:]*:149: Error: \$GOT not supported in this context
+[^:]*:150: Error: \$DPR_GOT not supported in this context
+[^:]*:151: Error: \$DPR_BYTE not supported in this context
+[^:]*:152: Error: \$DPR_HWORD not supported in this context
+[^:]*:153: Error: \$DPR_WORD not supported in this context
+[^:]*:154: Error: \$DPR_GOT not supported in this context
+[^:]*:155: Error: \$DPR_BYTE not supported in this context
+[^:]*:156: Error: \$DPR_HWORD not supported in this context
+[^:]*:157: Error: \$DPR_WORD not supported in this context
--- /dev/null
+# Test expressions not representable by relocations.
+.globl a
+.globl b
+.data
+d:
+ .word $DSBT_INDEX(__c6xabi_DSBT_BASE)
+ .word $got(b)
+ .word $dpr_got(a)
+ .word $dpr_byte(b)
+ .word $dpr_hword(a)
+ .word $dpr_word(b)
+.text
+.nocmp
+.globl f
+f:
+ addab .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE),a5
+ addab .D1X b14,$GOT(b),a5
+ addab .D1X b14,$DPR_GOT(b),a5
+ addab .D1X b14,$DPR_BYTE(b),a5
+ addab .D1X b14,$DPR_HWORD(b),a5
+ addab .D1X b14,$DPR_WORD(b),a5
+ addah .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE),a5
+ addah .D1X b14,$GOT(b),a5
+ addah .D1X b14,$DPR_GOT(b),a5
+ addah .D1X b14,$DPR_BYTE(b),a5
+ addah .D1X b14,$DPR_HWORD(b),a5
+ addah .D1X b14,$DPR_WORD(b),a5
+ addaw .D1X b14,$DPR_GOT(b),a5
+ addaw .D1X b14,$DPR_BYTE(b),a5
+ addaw .D1X b14,$DPR_HWORD(b),a5
+ addaw .D1X b14,$DPR_WORD(b),a5
+ addk .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
+ addk .S1 $got(b),a7
+ addk .S1 $dpr_got(b),a7
+ addk .S1 $dpr_hword(b),a7
+ addk .S1 $dpr_word(b),a7
+ mvk .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
+ mvk .S1 $got(b),a7
+ mvk .S1 $dpr_got(b),a7
+ mvk .S1 $dpr_hword(b),a7
+ mvk .S1 $dpr_word(b),a7
+ mvkh .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
+ mvkh .S1 $got(b),a7
+ mvklh .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
+ mvklh .S1 $got(b),a7
+ mvkl .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
+ mvkl .S1 $got(b),a7
+ addkpc .S2 $dsbt_index(__c6xabi_DSBT_BASE),b3,0
+ addkpc .S2 $GOT(b),b3,0
+ addkpc .S2 $DPR_GOT(b),b3,0
+ addkpc .S2 $DPR_BYTE(b),b3,0
+ addkpc .S2 $DPR_HWORD(b),b3,0
+ addkpc .S2 $DPR_WORD(b),b3,0
+ b .S1 $dsbt_index(__c6xabi_DSBT_BASE)
+ b .S1 $GOT(b)
+ b .S1 $DPR_GOT(b)
+ b .S1 $DPR_BYTE(b)
+ b .S1 $DPR_HWORD(b)
+ b .S1 $DPR_WORD(b)
+ call .S1 $dsbt_index(__c6xabi_DSBT_BASE)
+ call .S1 $GOT(b)
+ call .S1 $DPR_GOT(b)
+ call .S1 $DPR_BYTE(b)
+ call .S1 $DPR_HWORD(b)
+ call .S1 $DPR_WORD(b)
+ bdec .S1 $dsbt_index(__c6xabi_DSBT_BASE),a1
+ bdec .S1 $GOT(b),a1
+ bdec .S1 $DPR_GOT(b),a1
+ bdec .S1 $DPR_BYTE(b),a1
+ bdec .S1 $DPR_HWORD(b),a1
+ bdec .S1 $DPR_WORD(b),a1
+ bpos .S2 $dsbt_index(__c6xabi_DSBT_BASE),b1
+ bpos .S2 $GOT(b),b1
+ bpos .S2 $DPR_GOT(b),b1
+ bpos .S2 $DPR_BYTE(b),b1
+ bpos .S2 $DPR_HWORD(b),b1
+ bpos .S2 $DPR_WORD(b),b1
+ bnop .S1 $dsbt_index(__c6xabi_DSBT_BASE),1
+ bnop .S1 $GOT(b),1
+ bnop .S1 $DPR_GOT(b),1
+ bnop .S1 $DPR_BYTE(b),1
+ bnop .S1 $DPR_HWORD(b),1
+ bnop .S1 $DPR_WORD(b),1
+ callnop $dsbt_index(__c6xabi_DSBT_BASE),1
+ callnop $GOT(b),1
+ callnop $DPR_GOT(b),1
+ callnop $DPR_BYTE(b),1
+ callnop $DPR_HWORD(b),1
+ callnop $DPR_WORD(b),1
+ callp .S1 $dsbt_index(__c6xabi_DSBT_BASE),a3
+ callp .S1 $GOT(b),a3
+ callp .S1 $DPR_GOT(b),a3
+ callp .S1 $DPR_BYTE(b),a3
+ callp .S1 $DPR_HWORD(b),a3
+ callp .S1 $DPR_WORD(b),a3
+ callret .S1 $dsbt_index(__c6xabi_DSBT_BASE)
+ callret .S1 $GOT(b)
+ callret .S1 $DPR_GOT(b)
+ callret .S1 $DPR_BYTE(b)
+ callret .S1 $DPR_HWORD(b)
+ callret .S1 $DPR_WORD(b)
+ ret .S1 $dsbt_index(__c6xabi_DSBT_BASE)
+ ret .S1 $GOT(b)
+ ret .S1 $DPR_GOT(b)
+ ret .S1 $DPR_BYTE(b)
+ ret .S1 $DPR_HWORD(b)
+ ret .S1 $DPR_WORD(b)
+ retp .S1 $dsbt_index(__c6xabi_DSBT_BASE),a3
+ retp .S1 $GOT(b),a3
+ retp .S1 $DPR_GOT(b),a3
+ retp .S1 $DPR_BYTE(b),a3
+ retp .S1 $DPR_HWORD(b),a3
+ retp .S1 $DPR_WORD(b),a3
+ ldb .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
+ ldb .D2T2 *+b14($GOT(b)),b1
+ ldb .D2T2 *+b14($DPR_GOT(b)),b1
+ ldb .D2T2 *+b14($DPR_BYTE(b)),b1
+ ldb .D2T2 *+b14($DPR_HWORD(b)),b1
+ ldb .D2T2 *+b14($DPR_WORD(b)),b1
+ ldbu .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
+ ldbu .D2T2 *+b14($GOT(b)),b1
+ ldbu .D2T2 *+b14($DPR_GOT(b)),b1
+ ldbu .D2T2 *+b14($DPR_BYTE(b)),b1
+ ldbu .D2T2 *+b14($DPR_HWORD(b)),b1
+ ldbu .D2T2 *+b14($DPR_WORD(b)),b1
+ ldh .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
+ ldh .D2T2 *+b14($GOT(b)),b1
+ ldh .D2T2 *+b14($DPR_GOT(b)),b1
+ ldh .D2T2 *+b14($DPR_BYTE(b)),b1
+ ldh .D2T2 *+b14($DPR_HWORD(b)),b1
+ ldh .D2T2 *+b14($DPR_WORD(b)),b1
+ ldhu .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
+ ldhu .D2T2 *+b14($GOT(b)),b1
+ ldhu .D2T2 *+b14($DPR_GOT(b)),b1
+ ldhu .D2T2 *+b14($DPR_BYTE(b)),b1
+ ldhu .D2T2 *+b14($DPR_HWORD(b)),b1
+ ldhu .D2T2 *+b14($DPR_WORD(b)),b1
+ ldw .D2T2 *+b14($DPR_GOT(b)),b1
+ ldw .D2T2 *+b14($DPR_BYTE(b)),b1
+ ldw .D2T2 *+b14($DPR_HWORD(b)),b1
+ ldw .D2T2 *+b14($DPR_WORD(b)),b1
+ stb .D2T2 b1,*+b14($dsbt_index(__c6xabi_DSBT_BASE))
+ stb .D2T2 b1,*+b14($GOT(b))
+ stb .D2T2 b1,*+b14($DPR_GOT(b))
+ stb .D2T2 b1,*+b14($DPR_BYTE(b))
+ stb .D2T2 b1,*+b14($DPR_HWORD(b))
+ stb .D2T2 b1,*+b14($DPR_WORD(b))
+ sth .D2T2 b1,*+b14($dsbt_index(__c6xabi_DSBT_BASE))
+ sth .D2T2 b1,*+b14($GOT(b))
+ sth .D2T2 b1,*+b14($DPR_GOT(b))
+ sth .D2T2 b1,*+b14($DPR_BYTE(b))
+ sth .D2T2 b1,*+b14($DPR_HWORD(b))
+ sth .D2T2 b1,*+b14($DPR_WORD(b))
+ stw .D2T2 b1,*+b14($DPR_GOT(b))
+ stw .D2T2 b1,*+b14($DPR_BYTE(b))
+ stw .D2T2 b1,*+b14($DPR_HWORD(b))
+ stw .D2T2 b1,*+b14($DPR_WORD(b))
--- /dev/null
+#name: C6X bad relocations 3
+#error-output: reloc-bad-3.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:21: Error: immediate offset out of range
+[^:]*:22: Error: immediate offset out of range
+[^:]*:24: Error: immediate offset out of range
+[^:]*:25: Error: immediate offset out of range
+[^:]*:27: Error: immediate offset out of range
+[^:]*:28: Error: immediate offset out of range
+[^:]*:31: Error: immediate offset out of range
+[^:]*:32: Error: immediate offset out of range
+[^:]*:35: Error: immediate offset out of range
+[^:]*:36: Error: immediate offset out of range
+[^:]*:38: Error: immediate offset out of range
+[^:]*:39: Error: immediate offset out of range
+[^:]*:41: Error: immediate offset out of range
+[^:]*:42: Error: immediate offset out of range
+[^:]*:44: Error: immediate offset out of range
+[^:]*:45: Error: immediate offset out of range
+[^:]*:46: Error: immediate offset not 2-byte-aligned
+[^:]*:48: Error: immediate offset out of range
+[^:]*:49: Error: immediate offset out of range
+[^:]*:50: Error: immediate offset not 2-byte-aligned
+[^:]*:52: Error: immediate offset out of range
+[^:]*:53: Error: immediate offset out of range
+[^:]*:54: Error: immediate offset not 4-byte-aligned
+[^:]*:56: Error: immediate offset out of range
+[^:]*:57: Error: immediate offset out of range
+[^:]*:59: Error: immediate offset out of range
+[^:]*:60: Error: immediate offset out of range
+[^:]*:61: Error: immediate offset not 2-byte-aligned
+[^:]*:63: Error: immediate offset out of range
+[^:]*:64: Error: immediate offset out of range
+[^:]*:65: Error: immediate offset not 4-byte-aligned
+[^:]*:9: Error: value too large for 2-byte field
+[^:]*:11: Error: value too large for 2-byte field
+[^:]*:13: Error: value too large for 1-byte field
+[^:]*:15: Error: value too large for 1-byte field
--- /dev/null
+# Test relocation overflow and insufficiently divisible values. Note
+# that divisibility checks for constant values are only applicable to
+# load and store offsets, not ADDA, because constant values are
+# encoded literally for ADDA, and divisbility checks for offsets from
+# symbols are only applicable with REL relocations.
+.data
+t0:
+ .short b65535-b0
+ .short b65536-b0
+ .short b0-b32768
+ .short b32767-b65536
+ .byte b255-b0
+ .byte b256-b0
+ .byte b0-b128
+ .byte b127-b256
+.text
+.nocmp
+.globl f
+f:
+ addab .D1X b14,b32767-b0,a5
+ addab .D1X b14,b32768-b0,a5
+ addab .D1X b14,b127-b128,a5
+ addah .D1X b14,b32767-b0,a5
+ addah .D1X b14,b32768-b0,a5
+ addah .D1X b14,b127-b128,a5
+ addaw .D1X b14,b32767-b0,a5
+ addaw .D1X b14,b32768-b0,a5
+ addaw .D1X b14,b127-b128,a5
+ addk .S1 b32767-b0,a9
+ addk .S1 b0-b32768,a9
+ addk .S1 b32768-b0,a9
+ addk .S1 b32767-b65536,a9
+ mvk .S1 b32767-b0,a9
+ mvk .S1 b0-b32768,a9
+ mvk .S1 b32768-b0,a9
+ mvk .S1 b32767-b65536,a9
+ ldb .D2T2 *+b14(b32767-b0),b1
+ ldb .D2T2 *+b14(b32768-b0),b1
+ ldb .D2T2 *+b14(b32767-b32768),b1
+ ldbu .D2T2 *+b14(b32767-b0),b1
+ ldbu .D2T2 *+b14(b32768-b0),b1
+ ldbu .D2T2 *+b14(b32767-b32768),b1
+ ldh .D2T2 *+b14(h32767-h0),b1
+ ldh .D2T2 *+b14(h32768-h0),b1
+ ldh .D2T2 *+b14(h32767-h32768),b1
+ ldh .D2T2 *+b14(b32768-b32767),b1
+ ldhu .D2T2 *+b14(h32767-h0),b1
+ ldhu .D2T2 *+b14(h32768-h0),b1
+ ldhu .D2T2 *+b14(h32767-h32768),b1
+ ldhu .D2T2 *+b14(b32768-b32767),b1
+ ldw .D2T2 *+b14(w32767-w0),b1
+ ldw .D2T2 *+b14(w32768-w0),b1
+ ldw .D2T2 *+b14(w32767-w32768),b1
+ ldw .D2T2 *+b14(h32768-h32767),b1
+ stb .D2T2 b1,*+b14(b32767-b0)
+ stb .D2T2 b1,*+b14(b32768-b0)
+ stb .D2T2 b1,*+b14(b32767-b32768)
+ sth .D2T2 b1,*+b14(h32767-h0)
+ sth .D2T2 b1,*+b14(h32768-h0)
+ sth .D2T2 b1,*+b14(h32767-h32768)
+ sth .D2T2 b1,*+b14(b32768-b32767)
+ stw .D2T2 b1,*+b14(w32767-w0)
+ stw .D2T2 b1,*+b14(w32768-w0)
+ stw .D2T2 b1,*+b14(w32767-w32768)
+ stw .D2T2 b1,*+b14(h32768-h32767)
+b0:
+ .space 127
+b127:
+ .space 1
+b128:
+ .space 127
+b255:
+ .space 1
+b256:
+ .space 32511
+b32767:
+ .space 1
+b32768:
+ .space 32767
+b65535:
+ .space 1
+b65536:
+ .word 0
+h0:
+ .space 65534
+h32767:
+ .space 2
+h32768:
+ .word 0
+w0:
+ .space 131068
+w32767:
+ .space 4
+w32768:
+ .word 0
--- /dev/null
+#name: C6X bad relocations 4
+#error-output: reloc-bad-4.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:7: Error: \$DSBT_INDEX must be used with __c6xabi_DSBT_BASE
--- /dev/null
+# Test bad uses of $DSBT_INDEX. Use with a bad symbol
+.globl a
+.text
+.nocmp
+.globl f
+f:
+ addaw .D1X b14,$dsbt_index(a),a5
--- /dev/null
+#name: C6X bad relocations 5
+#error-output: reloc-bad-5.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:8: Error: addend used with \$DSBT_INDEX
--- /dev/null
+# Test bad uses of $DSBT_INDEX. Uses with addend.
+.text
+.nocmp
+.globl f
+f:
+ addaw .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE),a5
+ addaw .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE)+0,a5
+ addaw .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE)+4,a5
--- /dev/null
+#name: C6X bad relocations 6
+#error-output: reloc-bad-6.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:19: Error: PC-relative offset out of range
+[^:]*:21: Error: PC-relative offset out of range
+[^:]*:22: Error: PC-relative offset out of range
+[^:]*:24: Error: PC-relative offset not 4-byte-aligned
+[^:]*:53: Error: PC-relative offset out of range
+[^:]*:55: Error: PC-relative offset out of range
+[^:]*:56: Error: PC-relative offset out of range
+[^:]*:58: Error: PC-relative offset not 4-byte-aligned
+[^:]*:87: Error: PC-relative offset out of range
+[^:]*:89: Error: PC-relative offset out of range
+[^:]*:90: Error: PC-relative offset out of range
+[^:]*:92: Error: PC-relative offset not 4-byte-aligned
+[^:]*:121: Error: PC-relative offset out of range
+[^:]*:123: Error: PC-relative offset out of range
+[^:]*:124: Error: PC-relative offset out of range
+[^:]*:126: Error: PC-relative offset not 4-byte-aligned
+[^:]*:155: Error: PC-relative offset out of range
+[^:]*:157: Error: PC-relative offset out of range
+[^:]*:158: Error: PC-relative offset out of range
+[^:]*:160: Error: PC-relative offset not 4-byte-aligned
+[^:]*:189: Error: PC-relative offset out of range
+[^:]*:191: Error: PC-relative offset out of range
+[^:]*:192: Error: PC-relative offset out of range
+[^:]*:194: Error: PC-relative offset not 4-byte-aligned
+[^:]*:223: Error: PC-relative offset out of range
+[^:]*:225: Error: PC-relative offset out of range
+[^:]*:226: Error: PC-relative offset out of range
+[^:]*:228: Error: PC-relative offset not 4-byte-aligned
+[^:]*:257: Error: PC-relative offset out of range
+[^:]*:259: Error: PC-relative offset out of range
+[^:]*:260: Error: PC-relative offset out of range
+[^:]*:262: Error: PC-relative offset not 4-byte-aligned
+[^:]*:291: Error: PC-relative offset out of range
+[^:]*:293: Error: PC-relative offset out of range
+[^:]*:294: Error: PC-relative offset out of range
+[^:]*:296: Error: PC-relative offset not 4-byte-aligned
+[^:]*:325: Error: PC-relative offset out of range
+[^:]*:327: Error: PC-relative offset out of range
+[^:]*:328: Error: PC-relative offset out of range
+[^:]*:330: Error: PC-relative offset not 4-byte-aligned
+[^:]*:359: Error: PC-relative offset out of range
+[^:]*:361: Error: PC-relative offset out of range
+[^:]*:362: Error: PC-relative offset out of range
+[^:]*:364: Error: PC-relative offset not 4-byte-aligned
--- /dev/null
+# Test relocation overflow and insufficiently divisible values for
+# PC-relative operands.
+.text
+.nocmp
+f7_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+f7_28:
+ nop
+f7_32:
+ .space 256
+f7_288:
+ addkpc .S2 f7_32,b1,0
+ addkpc .S2 f7_28,b1,0
+ addkpc .S2 f7_32,b1,0
+ addkpc .S2 f7_0,b1,0
+ addkpc .S2 f7_544,b1,0
+ addkpc .S2 f7_540,b1,0
+ addkpc .S2 f7_288+1,b1,0
+ nop
+f7_320:
+ .space 220
+f7_540:
+ nop
+f7_544:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+f10_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+f10_28:
+ nop
+f10_32:
+ .space 2048
+f10_2080:
+ bdec .S1 f10_32,a1
+ bdec .S1 f10_28,a1
+ bdec .S1 f10_32,a1
+ bdec .S1 f10_0,a1
+ bdec .S1 f10_4128,a1
+ bdec .S1 f10_4124,a1
+ bdec .S1 f10_2080+1,a1
+ nop
+f10_2112:
+ .space 2012
+f10_4124:
+ nop
+f10_4128:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+g10_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+g10_28:
+ nop
+g10_32:
+ .space 2048
+g10_2080:
+ bpos .S1 g10_32,a1
+ bpos .S1 g10_28,a1
+ bpos .S1 g10_32,a1
+ bpos .S1 g10_0,a1
+ bpos .S1 g10_4128,a1
+ bpos .S1 g10_4124,a1
+ bpos .S1 g10_2080+1,a1
+ nop
+g10_2112:
+ .space 2012
+g10_4124:
+ nop
+g10_4128:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+f12_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+f12_28:
+ nop
+f12_32:
+ .space 8192
+f12_8224:
+ bnop f12_32,2
+ bnop f12_28,2
+ bnop f12_32,2
+ bnop f12_0,2
+ bnop f12_16416,2
+ bnop f12_16412,2
+ bnop f12_8224+1,2
+ nop
+f12_8256:
+ .space 8156
+f12_16412:
+ nop
+f12_16416:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+g12_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+g12_28:
+ nop
+g12_32:
+ .space 8192
+g12_8224:
+ callnop g12_32,2
+ callnop g12_28,2
+ callnop g12_32,2
+ callnop g12_0,2
+ callnop g12_16416,2
+ callnop g12_16412,2
+ callnop g12_8224+1,2
+ nop
+g12_8256:
+ .space 8156
+g12_16412:
+ nop
+g12_16416:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+f21_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+f21_28:
+ nop
+f21_32:
+ .space 4194304
+f21_4194336:
+ b .S1 f21_32
+ b .S1 f21_28
+ b .S1 f21_32
+ b .S1 f21_0
+ b .S1 f21_8388640
+ b .S1 f21_8388636
+ b .S1 f21_4194336+1
+ nop
+f21_4194368:
+ .space 4194268
+f21_8388636:
+ nop
+f21_8388640:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+g21_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+g21_28:
+ nop
+g21_32:
+ .space 4194304
+g21_4194336:
+ call .S1 g21_32
+ call .S1 g21_28
+ call .S1 g21_32
+ call .S1 g21_0
+ call .S1 g21_8388640
+ call .S1 g21_8388636
+ call .S1 g21_4194336+1
+ nop
+g21_4194368:
+ .space 4194268
+g21_8388636:
+ nop
+g21_8388640:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+h21_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+h21_28:
+ nop
+h21_32:
+ .space 4194304
+h21_4194336:
+ callp .S2 h21_32,b3
+ callp .S2 h21_28,b3
+ callp .S2 h21_32,b3
+ callp .S2 h21_0,b3
+ callp .S2 h21_8388640,b3
+ callp .S2 h21_8388636,b3
+ callp .S2 h21_4194336+1,b3
+ nop
+h21_4194368:
+ .space 4194268
+h21_8388636:
+ nop
+h21_8388640:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+i21_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+i21_28:
+ nop
+i21_32:
+ .space 4194304
+i21_4194336:
+ callret .S1 i21_32
+ callret .S1 i21_28
+ callret .S1 i21_32
+ callret .S1 i21_0
+ callret .S1 i21_8388640
+ callret .S1 i21_8388636
+ callret .S1 i21_4194336+1
+ nop
+i21_4194368:
+ .space 4194268
+i21_8388636:
+ nop
+i21_8388640:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+j21_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+j21_28:
+ nop
+j21_32:
+ .space 4194304
+j21_4194336:
+ ret .S1 j21_32
+ ret .S1 j21_28
+ ret .S1 j21_32
+ ret .S1 j21_0
+ ret .S1 j21_8388640
+ ret .S1 j21_8388636
+ ret .S1 j21_4194336+1
+ nop
+j21_4194368:
+ .space 4194268
+j21_8388636:
+ nop
+j21_8388640:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+k21_0:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+k21_28:
+ nop
+k21_32:
+ .space 4194304
+k21_4194336:
+ retp .S1 k21_32,a3
+ retp .S1 k21_28,a3
+ retp .S1 k21_32,a3
+ retp .S1 k21_0,a3
+ retp .S1 k21_8388640,a3
+ retp .S1 k21_8388636,a3
+ retp .S1 k21_4194336+1,a3
+ nop
+k21_4194368:
+ .space 4194268
+k21_8388636:
+ nop
+k21_8388640:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
--- /dev/null
+#name: C6X bad SPLOOP instructions 1
+#error-output: sploop-bad-1.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: too many operands to 'spkernel'
+[^:]*:6: Error: 'spkernel' instruction not supported on this functional unit
+[^:]*:7: Error: 'spkernelr' instruction not supported on this functional unit
+[^:]*:8: Error: too many operands to 'spkernelr'
+[^:]*:9: Error: 'sploop' instruction not supported on this functional unit
+[^:]*:10: Error: bad number of operands to 'sploop'
+[^:]*:11: Error: operand 1 of 'sploop' out of range
+[^:]*:12: Error: operand 1 of 'sploop' out of range
+[^:]*:13: Error: 'sploopd' instruction not supported on this functional unit
+[^:]*:14: Error: bad number of operands to 'sploopd'
+[^:]*:15: Error: operand 1 of 'sploopd' out of range
+[^:]*:16: Error: operand 1 of 'sploopd' out of range
+[^:]*:17: Error: 'sploopw' instruction not supported on this functional unit
+[^:]*:18: Error: bad number of operands to 'sploopw'
+[^:]*:19: Error: operand 1 of 'sploopw' out of range
+[^:]*:20: Error: operand 1 of 'sploopw' out of range
+[^:]*:21: Error: 'spmask' instruction not supported on this functional unit
+[^:]*:22: Error: bad functional unit for operand 1 of 'spmask'
+[^:]*:23: Error: too many operands to 'spmask'
+[^:]*:24: Error: 'spmaskr' instruction not supported on this functional unit
+[^:]*:25: Error: bad functional unit for operand 1 of 'spmaskr'
+[^:]*:26: Error: too many operands to 'spmaskr'
--- /dev/null
+# Test bad SPLOOP instructions and operands. Bad operands (generic errors).
+.text
+.globl f
+f:
+ spkernel 1,2,3
+ spkernel .L1
+ spkernelr .S1
+ spkernelr 1
+ sploop .D1
+ sploop
+ sploop 0
+ sploop 15
+ sploopd .S1
+ sploopd
+ sploopd 0
+ sploopd 15
+ sploopw .L1
+ sploopw
+ sploopw 0
+ sploopw 15
+ spmask .M1
+ spmask X1
+ spmask L1,L1,L1,L1,L1,L1,L1,L1,L1
+ spmaskr .M1
+ spmaskr X1
+ spmaskr L1,L1,L1,L1,L1,L1,L1,L1,L1
--- /dev/null
+#name: C6X bad SPLOOP instructions 2
+#error-output: sploop-bad-2.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:7: Error: 'sploop' instruction not at start of execute packet
+[^:]*:11: Error: 'sploopd' instruction not at start of execute packet
+[^:]*:15: Error: 'sploopw' instruction not at start of execute packet
+[^:]*:20: Error: 'spkernel' instruction not at start of execute packet
+[^:]*:23: Error: 'spkernel' instruction not at start of execute packet
+[^:]*:26: Error: 'spkernelr' instruction not at start of execute packet
+[^:]*:28: Error: 'spmask' instruction not at start of execute packet
+[^:]*:30: Error: 'spmaskr' instruction not at start of execute packet
--- /dev/null
+# Test bad SPLOOP instructions and operands. Instructions not first
+# in execute packet.
+.text
+.globl f
+f:
+ nop
+|| sploop 1
+ nop
+ spkernel
+ nop
+|| sploopd 1
+ nop
+ spkernel
+ nop
+|| sploopw 1
+ nop
+ spkernel
+ sploop 1
+ nop
+|| spkernel
+ sploop 1
+ nop
+|| spkernel 0,0
+ sploop 1
+ nop
+|| spkernelr
+ nop
+|| spmask
+ nop
+|| spmaskr
--- /dev/null
+#name: C6X bad SPLOOP instructions 3
+#error-output: sploop-bad-3.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: 'spkernel' instruction not in a software pipelined loop
+[^:]*:6: Error: 'spkernel' instruction not in a software pipelined loop
+[^:]*:7: Error: 'spkernelr' instruction not in a software pipelined loop
--- /dev/null
+# Test bad SPLOOP instructions and operands. SPKERNEL not after SPLOOP.
+.text
+.globl f
+f:
+ spkernel
+ spkernel 0,0
+ spkernelr
--- /dev/null
+#name: C6X bad SPLOOP instructions 4
+#error-output: sploop-bad-4.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:6: Error: nested software pipelined loop
+[^:]*:10: Error: nested software pipelined loop
+[^:]*:13: Error: nested software pipelined loop
--- /dev/null
+# Test bad SPLOOP instructions and operands. SPLOOP after SPLOOP.
+.text
+.globl f
+f:
+ sploop 1
+ sploop 1
+ nop
+ spkernel
+ sploop 1
+ sploopd 1
+ spkernel
+ sploop 1
+ sploopw 1
+ spkernel
--- /dev/null
+#name: C6X bad SPLOOP instructions 5
+#error-output: sploop-bad-5.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: functional unit already masked for operand 2 of 'spmask'
+[^:]*:6: Error: functional unit already masked for operand 2 of 'spmaskr'
+[^:]*:8: Error: functional unit already masked
+[^:]*:10: Error: functional unit already masked
--- /dev/null
+# Test bad SPLOOP instructions and operands. Duplicate masking.
+.text
+.globl f
+f:
+ spmask L1,L1
+ spmaskr D1,D1
+ spmask L1
+||^ mv .L1 a1,a2
+ spmaskr S1
+||^ mv .S1 a1,a2
--- /dev/null
+#name: C6X bad SPLOOP instructions 6
+#error-output: sploop-bad-6.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:7: Error: operand 1 of 'spkernel' out of range
+[^:]*:8: Error: operand 2 of 'spkernel' out of range
+[^:]*:9: Error: operand 2 of 'spkernel' out of range
+[^:]*:10: Error: operand 1 of 'spkernel' out of range
+[^:]*:13: Error: operand 1 of 'spkernel' out of range
+[^:]*:14: Error: operand 2 of 'spkernel' out of range
+[^:]*:15: Error: operand 2 of 'spkernel' out of range
+[^:]*:16: Error: operand 1 of 'spkernel' out of range
+[^:]*:19: Error: operand 1 of 'spkernel' out of range
+[^:]*:20: Error: operand 2 of 'spkernel' out of range
+[^:]*:21: Error: operand 2 of 'spkernel' out of range
+[^:]*:22: Error: operand 1 of 'spkernel' out of range
+[^:]*:25: Error: operand 1 of 'spkernel' out of range
+[^:]*:26: Error: operand 2 of 'spkernel' out of range
+[^:]*:27: Error: operand 2 of 'spkernel' out of range
+[^:]*:28: Error: operand 1 of 'spkernel' out of range
+[^:]*:31: Error: operand 1 of 'spkernel' out of range
+[^:]*:32: Error: operand 2 of 'spkernel' out of range
+[^:]*:33: Error: operand 2 of 'spkernel' out of range
+[^:]*:34: Error: operand 1 of 'spkernel' out of range
+[^:]*:37: Error: operand 1 of 'spkernel' out of range
+[^:]*:38: Error: operand 2 of 'spkernel' out of range
+[^:]*:39: Error: operand 2 of 'spkernel' out of range
+[^:]*:40: Error: operand 1 of 'spkernel' out of range
--- /dev/null
+# Test bad SPLOOP instructions and operands. SPKERNEL operands out of
+# range.
+.text
+.globl f
+f:
+ sploop 1
+ spkernel -1,0
+ spkernel 0,-1
+ spkernel 0,1
+ spkernel 64,0
+ spkernel
+ sploop 2
+ spkernel -1,0
+ spkernel 0,-1
+ spkernel 0,2
+ spkernel 32,0
+ spkernel
+ sploop 3
+ spkernel -1,0
+ spkernel 0,-1
+ spkernel 0,3
+ spkernel 16,0
+ spkernel
+ sploop 4
+ spkernel -1,0
+ spkernel 0,-1
+ spkernel 0,4
+ spkernel 16,0
+ spkernel
+ sploop 5
+ spkernel -1,0
+ spkernel 0,-1
+ spkernel 0,5
+ spkernel 8,0
+ spkernel
+ sploop 9
+ spkernel -1,0
+ spkernel 0,-1
+ spkernel 0,9
+ spkernel 4,0
+ spkernel
--- /dev/null
+#name: C6X bad SPLOOP instructions 7
+#error-output: sploop-bad-7.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:6: Error: '||^' without previous SPMASK
+[^:]*:8: Error: cannot mask instruction using no functional unit
--- /dev/null
+# Test bad SPLOOP instructions and operands. Bad use of ||^.
+.text
+.globl f
+f:
+ nop
+||^ mv .L1 a2,a3
+ spmask
+||^ nop
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: C6X syntax variants
+#as: -march=c674x -mlittle-endian
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+0+00 <[^>]*> 00000000[ \t]+nop 1
+0+04 <[^>]*> 00008000[ \t]+nop 5
+0+08 <[^>]*> 00002000[ \t]+nop 2
+0+0c <[^>]*> 00004000[ \t]+nop 3
+0+10 <[^>]*> 00008000[ \t]+nop 5
+0+14 <[^>]*> 00002000[ \t]+nop 2
+0+18 <[^>]*> 00006000[ \t]+nop 4
+0+1c <[^>]*> 00002000[ \t]+nop 2
+0+20 <[^>]*> 05900358[ \t]+abs \.L1 a4,a11
+0+24 <[^>]*> 0694135a[ \t]+abs \.L2X a5,b13
+0+28 <[^>]*> 0593e1a0[ \t]+add \.S1 -1,a4,a11
+[ \t]*\.\.\.
--- /dev/null
+# Test variants of assembler syntax.
+* Another comment.
+.text
+.nocmp
+ .globl f ; comment here as well
+ f: nop;comment
+ nop 5
+ nop 4- 2
+nop (1+2) ; 3
+NoP 5
+NOP 2
+nop 4 @ nop 2
+ABS .l1 a4 , a11
+ABS .L2x A5, B13
+add .S1 0xffffffff,a4,a11
--- /dev/null
+if { [istarget tic6x-*-*] } {
+ run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+}
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * dis-asm.h (print_insn_tic6x): Declare.
+
2010-03-23 Joseph Myers <joseph@codesourcery.com>
* symcat.h (CONCAT5, CONCAT6, XCONCAT5, XCONCAT6): Define.
/* Interface between the opcode library and its callers.
- Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009
+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
extern int print_insn_tic30 (bfd_vma, disassemble_info *);
extern int print_insn_tic4x (bfd_vma, disassemble_info *);
extern int print_insn_tic54x (bfd_vma, disassemble_info *);
+extern int print_insn_tic6x (bfd_vma, disassemble_info *);
extern int print_insn_tic80 (bfd_vma, disassemble_info *);
extern int print_insn_v850 (bfd_vma, disassemble_info *);
extern int print_insn_vax (bfd_vma, disassemble_info *);
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
+ * tic6x.h: New.
+
2010-03-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* common.h (VER_FLG_*): Document.
#define ELFOSABI_NSK 14 /* Hewlett-Packard Non-Stop Kernel */
#define ELFOSABI_AROS 15 /* AROS */
#define ELFOSABI_FENIXOS 16 /* FenixOS */
+#define ELFOSABI_C6000_ELFABI 64 /* Bare-metal TMS320C6000 */
+#define ELFOSABI_C6000_LINUX 65 /* Linux TMS320C6000 */
#define ELFOSABI_ARM 97 /* ARM */
#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */
--- /dev/null
+/* TI C6X ELF support for BFD.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#ifndef _ELF_TIC6X_H
+#define _ELF_TIC6X_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types. */
+START_RELOC_NUMBERS (elf_tic6x_reloc_type)
+ RELOC_NUMBER (R_C6000_NONE, 0)
+ RELOC_NUMBER (R_C6000_ABS32, 1)
+ RELOC_NUMBER (R_C6000_ABS16, 2)
+ RELOC_NUMBER (R_C6000_ABS8, 3)
+ RELOC_NUMBER (R_C6000_PCR_S21, 4)
+ RELOC_NUMBER (R_C6000_PCR_S12, 5)
+ RELOC_NUMBER (R_C6000_PCR_S10, 6)
+ RELOC_NUMBER (R_C6000_PCR_S7, 7)
+ RELOC_NUMBER (R_C6000_ABS_S16, 8)
+ RELOC_NUMBER (R_C6000_ABS_L16, 9)
+ RELOC_NUMBER (R_C6000_ABS_H16, 10)
+ RELOC_NUMBER (R_C6000_SBR_U15_B, 11)
+ RELOC_NUMBER (R_C6000_SBR_U15_H, 12)
+ RELOC_NUMBER (R_C6000_SBR_U15_W, 13)
+ RELOC_NUMBER (R_C6000_SBR_S16, 14)
+ RELOC_NUMBER (R_C6000_SBR_L16_B, 15)
+ RELOC_NUMBER (R_C6000_SBR_L16_H, 16)
+ RELOC_NUMBER (R_C6000_SBR_L16_W, 17)
+ RELOC_NUMBER (R_C6000_SBR_H16_B, 18)
+ RELOC_NUMBER (R_C6000_SBR_H16_H, 19)
+ RELOC_NUMBER (R_C6000_SBR_H16_W, 20)
+ RELOC_NUMBER (R_C6000_SBR_GOT_U15_W, 21)
+ RELOC_NUMBER (R_C6000_SBR_GOT_L16_W, 22)
+ RELOC_NUMBER (R_C6000_SBR_GOT_H16_W, 23)
+ RELOC_NUMBER (R_C6000_DSBT_INDEX, 24)
+ RELOC_NUMBER (R_C6000_PREL31, 25)
+ RELOC_NUMBER (R_C6000_COPY, 26)
+ RELOC_NUMBER (R_C6000_ALIGN, 253)
+ RELOC_NUMBER (R_C6000_FPHEAD, 254)
+ RELOC_NUMBER (R_C6000_NOCMP, 255)
+END_RELOC_NUMBERS (R_TIC6X_max)
+
+/* Processor-specific flags. */
+
+/* File contains static relocation information. */
+#define EF_C6000_REL 0x1
+
+/* Processor-specific section types. */
+
+/* Unwind function table for stack unwinding. */
+#define SHT_C6000_UNWIND 0x70000001
+
+/* DLL dynamic linking pre-emption map. */
+#define SHT_C6000_PREEMPTMAP 0x70000002
+
+/* Object file compatibility attributes. */
+#define SHT_C6000_ATTRIBUTES 0x70000003
+
+/* Intermediate code for link-time optimization. */
+#define SHT_TI_ICODE 0x7F000000
+
+/* Symbolic cross reference information. */
+#define SHT_TI_XREF 0x7F000001
+
+/* Reserved. */
+#define SHT_TI_HANDLER 0x7F000002
+
+/* Compressed data for initializing C variables. */
+#define SHT_TI_INITINFO 0x7F000003
+
+/* Extended program header attributes. */
+#define SHT_TI_PHATTRS 0x7F000004
+
+/* Processor-specific segment types. */
+
+/* Extended Segment Attributes. */
+#define PT_C6000_PHATTR 0x70000000
+
+/* Processor-specific dynamic tags. */
+
+/* Undocumented. */
+#define DT_C6000_GSYM_OFFSET 0x6000000D
+
+/* Undocumented. */
+#define DT_C6000_GSTR_OFFSET 0x6000000F
+
+/* Statically linked base address of data segment. */
+#define DT_C6000_DSBT_BASE 0x70000000
+
+/* Number of entries in this module's DSBT. */
+#define DT_C6000_DSBT_SIZE 0x70000001
+
+/* Undocumented. */
+#define DT_C6000_PREEMPTMAP 0x70000002
+
+/* The hard-coded DSBT index for this module, if any. */
+#define DT_C6000_DSBT_INDEX 0x70000003
+
+/* Extended program header attributes. */
+
+/* Terminate a segment. */
+#define PHA_NULL 0x0
+
+/* Segment's address bound to the final address. */
+#define PHA_BOUND 0x1
+
+/* Segment cannot be further relocated. */
+#define PHA_READONLY 0x2
+
+#endif /* _ELF_TIC6X_H */
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * tic6x-control-registers.h, tic6x-insn-formats.h,
+ tic6x-opcode-table.h, tic6x.h: New.
+
2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
* mips.h: (LOONGSON2F_NOP_INSN): New macro.
--- /dev/null
+/* TI C6X control register information.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/* Define the CTRL macro before including this file; it takes as
+ arguments the fields from tic6x_ctrl (defined in tic6x.h). The
+ control register name is given as an identifier; the isa_variants
+ field without the leading TIC6X_INSN_; the rw field without the
+ leading tic6x_rw_. */
+
+CTRL(amr, C62X, read_write, 0x0, 0x10)
+CTRL(csr, C62X, read_write, 0x1, 0x10)
+CTRL(dnum, C64XP, read, 0x11, 0x1f)
+CTRL(ecr, C64XP, write, 0x1d, 0x1f)
+CTRL(efr, C64XP, read, 0x1d, 0x1f)
+CTRL(fadcr, C67X, read_write, 0x12, 0x1f)
+CTRL(faucr, C67X, read_write, 0x13, 0x1f)
+CTRL(fmcr, C67X, read_write, 0x14, 0x1f)
+CTRL(gfpgfr, C64X, read_write, 0x18, 0x1f)
+CTRL(gplya, C64XP, read_write, 0x16, 0x1f)
+CTRL(gplyb, C64XP, read_write, 0x17, 0x1f)
+CTRL(icr, C62X, write, 0x3, 0x10)
+CTRL(ier, C62X, read_write, 0x4, 0x10)
+CTRL(ierr, C64XP, read_write, 0x1f, 0x1f)
+CTRL(ifr, C62X, read, 0x2, 0x1d)
+CTRL(ilc, C64XP, read_write, 0xd, 0x1f)
+CTRL(irp, C62X, read_write, 0x6, 0x10)
+CTRL(isr, C62X, write, 0x2, 0x10)
+CTRL(istp, C62X, read_write, 0x5, 0x10)
+CTRL(itsr, C64XP, read_write, 0x1b, 0x1f)
+CTRL(nrp, C62X, read_write, 0x7, 0x10)
+CTRL(ntsr, C64XP, read_write, 0x1c, 0x1f)
+CTRL(pce1, C62X, read, 0x10, 0xf)
+CTRL(rep, C64XP, read_write, 0xf, 0x1f)
+CTRL(rilc, C64XP, read_write, 0xe, 0x1f)
+CTRL(ssr, C64XP, read_write, 0x15, 0x1f)
+CTRL(tsch, C64XP, read, 0xb, 0x1f)
+CTRL(tscl, C64XP, read, 0xa, 0x1f)
+CTRL(tsr, C64XP, read_write, 0x1a, 0x1f)
--- /dev/null
+/* TI C6X instruction format information.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/* Define the FMT macro before including this file; it takes a name
+ and the fields from tic6x_insn_format (defined in tic6x.h). */
+
+#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), (pos), (width) }
+#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1)
+#define CFLDS2(a, b) 5, { CFLDS, a, b }
+#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c }
+#define CFLDS4(a, b, c, d) 7, { CFLDS, a, b, c, d }
+#define CFLDS5(a, b, c, d, e) 8, { CFLDS, a, b, c, d, e }
+#define CFLDS6(a, b, c, d, e, f) 9, { CFLDS, a, b, c, d, e, f }
+#define CFLDS7(a, b, c, d, e, f, g) 10, { CFLDS, a, b, c, d, e, f, g }
+#define CFLDS8(a, b, c, d, e, f, g, h) 11, { CFLDS, a, b, c, d, e, f, g, h }
+#define NFLDS FLD(p, 0, 1)
+#define NFLDS1(a) 2, { NFLDS, a }
+#define NFLDS2(a, b) 3, { NFLDS, a, b }
+#define NFLDS3(a, b, c) 4, { NFLDS, a, b, c }
+#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e }
+#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f }
+#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g }
+
+/* These are in the order from SPRUFE8, appendices C-H. */
+
+/* Appendix C 32-bit formats. */
+
+FMT(d_1_or_2_src, 32, 0x40, 0x7c,
+ CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5),
+ FLD(dst, 23, 5)))
+FMT(d_ext_1_or_2_src, 32, 0x830, 0xc3c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(d_load_store, 32, 0x4, 0xc,
+ CFLDS8(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(r, 8, 1),
+ FLD(mode, 9, 4), FLD(offsetR, 13, 5), FLD(baseR, 18, 5),
+ FLD(srcdst, 23, 5)))
+/* The nonaligned loads and stores have the formats shown in the
+ individual instruction descriptions; the appendix is incorrect. */
+FMT(d_load_nonaligned, 32, 0x124, 0x17c,
+ CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
+ FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(dst, 24, 4)))
+FMT(d_store_nonaligned, 32, 0x174, 0x17c,
+ CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
+ FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(src, 24, 4)))
+FMT(d_load_store_long, 32, 0xc, 0xc,
+ CFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
+ FLD(dst, 23, 5)))
+FMT(d_adda_long, 32, 0x1000000c, 0xf000000c,
+ NFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
+ FLD(dst, 23, 5)))
+
+/* Appendix C 16-bit formats will go here. */
+
+/* Appendix D 32-bit formats. */
+
+FMT(l_1_or_2_src, 32, 0x18, 0x1c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(l_1_or_2_src_noncond, 32, 0x10000018, 0xf000001c,
+ NFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(l_unary, 32, 0x358, 0xffc,
+ CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+ FLD(dst, 23, 5)))
+
+/* Appendix D 16-bit formats will go here. */
+
+/* Appendix E 32-bit formats. */
+
+FMT(m_compound, 32, 0x30, 0x83c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(m_1_or_2_src, 32, 0x10000030, 0xf000083c,
+ NFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+/* Contrary to SPRUFE8, this does have predicate fields. */
+FMT(m_unary, 32, 0xf0, 0xffc,
+ CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+ FLD(dst, 23, 5)))
+
+/* M-unit formats missing from Appendix E. */
+FMT(m_mpy, 32, 0x0, 0x7c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 7, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+
+/* Appendix E 16-bit formats will go here. */
+
+/* Appendix F 32-bit formats. */
+
+FMT(s_1_or_2_src, 32, 0x20, 0x3c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 6), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23 ,5)))
+FMT(s_ext_1_or_2_src, 32, 0xc30, 0xc3c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(s_ext_1_or_2_src_noncond, 32, 0xc30, 0xe0000c3c,
+ NFLDS7(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5), FLD(z, 28, 1)))
+FMT(s_unary, 32, 0xf20, 0xffc,
+ CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+ FLD(dst, 23, 5)))
+FMT(s_ext_branch_cond_imm, 32, 0x10, 0x7c,
+ CFLDS2(FLD(s, 1, 1), FLD(cst, 7, 21)))
+FMT(s_call_imm_nop, 32, 0x10, 0xe000007c,
+ NFLDS3(FLD(s, 1, 1), FLD(cst, 7, 21), FLD(z, 28, 1)))
+FMT(s_branch_nop_cst, 32, 0x120, 0x1ffc,
+ CFLDS3(FLD(s, 1, 1), FLD(src1, 13, 3), FLD(src2, 16, 12)))
+FMT(s_branch_nop_reg, 32, 0x800360, 0xf830ffc,
+ CFLDS4(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src1, 13, 3), FLD(src2, 18, 5)))
+FMT(s_branch, 32, 0x360, 0xf8feffc,
+ CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src2, 18, 5)))
+FMT(s_mvk, 32, 0x28, 0x3c,
+ CFLDS4(FLD(s, 1, 1), FLD(h, 6, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
+FMT(s_field, 32, 0x8, 0x3c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 2), FLD(cstb, 8, 5), FLD(csta, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+
+/* S-unit formats missing from Appendix F. */
+FMT(s_addk, 32, 0x50, 0x7c,
+ CFLDS3(FLD(s, 1, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
+FMT(s_addkpc, 32, 0x160, 0x1ffc,
+ CFLDS4(FLD(s, 1, 1), FLD(src2, 13, 3), FLD(src1, 16, 7), FLD(dst, 23, 5)))
+FMT(s_b_irp, 32, 0x1800e0, 0x7feffc,
+ CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
+FMT(s_b_nrp, 32, 0x1c00e0, 0x7feffc,
+ CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
+FMT(s_bdec, 32, 0x1020, 0x1ffc,
+ CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
+FMT(s_bpos, 32, 0x20, 0x1ffc,
+ CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
+
+/* Appendix F 16-bit formats will go here. */
+
+/* Appendix G 16-bit formats will go here. */
+
+/* Appendix H 32-bit formats. */
+
+FMT(nfu_loop_buffer, 32, 0x00020000, 0x00021ffc,
+ CFLDS4(FLD(s, 1, 1), FLD(op, 13, 4), FLD(csta, 18, 5), FLD(cstb, 23, 5)))
+/* Corrected relative to Appendix H. */
+FMT(nfu_nop_idle, 32, 0x00000000, 0xfffe1ffc,
+ NFLDS2(FLD(s, 1, 1), FLD(op, 13, 4)))
+
+/* No-unit formats missing from Appendix H (given the NOP and IDLE
+ correction). */
+FMT(nfu_dint, 32, 0x10004000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_rint, 32, 0x10006000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_swe, 32, 0x10000000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_swenr, 32, 0x10002000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+/* Although formally covered by the loop buffer format, the fields in
+ that format are not useful for all such instructions and not all
+ instructions can be predicated. */
+FMT(nfu_spkernel, 32, 0x00034000, 0xf03ffffc,
+ NFLDS2(FLD(s, 1, 1), FLD(fstgfcyc, 22, 6)))
+FMT(nfu_spkernelr, 32, 0x00036000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc,
+ NFLDS3(FLD(s, 1, 1), FLD(op, 13, 4), FLD(mask, 18, 8)))
+
+/* Appendix H 16-bit formats will go here. */
+
+#undef FLD
+#undef CFLDS
+#undef CFLDS2
+#undef CFLDS3
+#undef CFLDS4
+#undef CFLDS5
+#undef CFLDS6
+#undef CFLDS7
+#undef CFLDS8
+#undef NFLDS
+#undef NFLDS1
+#undef NFLDS2
+#undef NFLDS3
+#undef NFLDS5
+#undef NFLDS6
+#undef NFLDS7
--- /dev/null
+/* TI C6X opcode table.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/* Define the INSN macro before including this file; it takes as
+ arguments the fields from tic6x_opcode (defined in tic6x.h). The
+ name is given as an identifier; the subsequent four operands should
+ have "tic6x_func_unit_", "tic6x_insn_format_", "tic6x_pipeline_"
+ and "TIC6X_INSN_", respectively, prepended to them by the macro
+ definition. Also define INSNE, which has a second argument that
+ goes after tic6x_opcode_NAME_ to form the enumeration value for
+ this instruction, where the value otherwise formed from the name,
+ functional unit and format is ambiguous, but otherwise has the same
+ arguments as INSN. */
+
+#define TIC6X_INSN_C64X_AND_C67X TIC6X_INSN_C64X|TIC6X_INSN_C67X
+#define tic6x_insn_format_nfu_s_branch_nop_cst \
+ tic6x_insn_format_s_branch_nop_cst
+#define tic6x_insn_format_s_l_1_or_2_src tic6x_insn_format_l_1_or_2_src
+#define RAN(id, min, max) { CONCAT2(tic6x_field_,id), (min), (max) }
+#define FIX(id, val) RAN(id, val, val)
+#define FIX0() 0, { { 0, 0, 0 } }
+#define FIX1(a) 1, { a }
+#define FIX2(a, b) 2, { a, b }
+#define FIX3(a, b, c) 3, { a, b, c }
+#define FIX4(a, b, c, d) 4, { a, b, c, d }
+#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } }
+#define OP1(a) 1, { a }
+#define OP2(a, b) 2, { a, b }
+#define OP3(a, b, c) 3, { a, b, c }
+#define OP4(a, b, c, d) 4, { a, b, c, d }
+#define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 }
+#define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 }
+#define ORREG14 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 4, 0, 0 }
+#define ORXREG14 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 4, 0, 0 }
+#define OWREG2 { tic6x_operand_reg, 4, tic6x_rw_write, 2, 2, 0, 0 }
+#define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 }
+#define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 }
+#define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 }
+#define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 }
+#define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 }
+#define OWREGD12 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 2, 2 }
+#define OWREGD4 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 4, 4 }
+#define ORREGD1 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 }
+#define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 }
+#define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 }
+#define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
+#define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
+#define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 }
+#define ORREGD1324 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 3, 2, 4 }
+#define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 }
+#define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_write, 3, 3, 0, 0 }
+#define ENC(id, meth, op) { \
+ CONCAT2(tic6x_field_,id), \
+ CONCAT2(tic6x_coding_,meth), \
+ op \
+ }
+#define ENC0() 0, { { 0, 0, 0 } }
+#define ENC1(a) 1, { a }
+#define ENC2(a, b) 2, { a, b }
+#define ENC3(a, b, c) 3, { a, b, c }
+#define ENC4(a, b, c, d) 4, { a, b, c, d }
+#define ENC5(a, b, c, d, e) 5, { a, b, c, d, e }
+#define ENC6(a, b, c, d, e, f) 6, { a, b, c, d, e, f }
+#define ENC7(a, b, c, d, e, f, g) 7, { a, b, c, d, e, f, g }
+
+INSN(abs, l, unary, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGL1, OWREGL1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(abs2, l, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x4)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x2c), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREGD12),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(abssp, s, unary, 1cycle, C67X, 0,
+ FIX1(FIX(op, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x3)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x23)),
+ OP3(ORREG1, ORXREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x21)),
+ OP3(ORXREG1, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x2)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x20), FIX(x, 0)),
+ OP3(OACST, ORREGL1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, d_si_si_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(add, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x12)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSNE(add, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0xa)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0xb)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, scst, 1), ENC(dst, reg, 2)))
+
+INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x30)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(addab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x32)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSN(addab, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 3)),
+ OP3(ORAREG1, OLCST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(addad, d_si_si_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X,
+ TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x3c)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(addad, d_si_u5_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X,
+ TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x3d)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(addah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x34)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(addah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x36)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSN(addah, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 5)),
+ OP3(ORAREG1, OLCST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(addaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x38)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(addaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x3a)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 7)),
+ OP3(ORAREG1, OLCST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1),
+ ENC(dst, reg, 2)))
+
+INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(ORREGD12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(adddp, s, l_1_or_2_src, addsubdp, C67XP, 0,
+ FIX1(FIX(op, 0x72)),
+ OP3(ORREGD12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX0(),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+
+INSN(addkpc, s, addkpc, 1cycle, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY,
+ FIX1(FIX(s, 1)),
+ OP3(OLCST, OWREG1, OACST),
+ ENC3(ENC(src1, pcrel, 0), ENC(dst, reg, 1), ENC(src2, ucst, 2)))
+
+INSN(addsp, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(addsp, s, l_1_or_2_src, 4cycle, C67XP, 0,
+ FIX1(FIX(op, 0x70)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xd)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(addu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x2b)),
+ OP3(ORREG1, ORXREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(addu, l_xui_ul_ul, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x29)),
+ OP3(ORXREG1, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(add2, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x5)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add2, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x4)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(add4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x65)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(and, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7a)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x6)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x7)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x7c)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(andn, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x6)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(andn, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x0)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(avg2, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(avgu4, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x12)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(b, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX0(),
+ OP1(OLCST),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(b, s, branch, branch, C62X, TIC6X_FLAG_SIDE_B_ONLY,
+ FIX1(FIX(s, 1)),
+ OP1(ORXREG1),
+ ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(b, s, b_irp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORIRP1),
+ ENC0())
+INSN(b, s, b_nrp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORNRP1),
+ ENC0())
+
+INSN(bdec, s, bdec, branch, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX0(),
+ OP2(OLCST, ORWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1)))
+
+INSN(bitc4, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(bitr, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1f)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(bnop, s, branch_nop_cst, branch, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+ FIX0(),
+ OP2(OLCST, OACST),
+ ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(bnop, nfu, s_branch_nop_cst, branch, C64XP,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP,
+ FIX1(FIX(s, 0)),
+ OP2(OLCST, OACST),
+ ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(bnop, s, branch_nop_reg, branch, C64X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP,
+ FIX1(FIX(s, 1)),
+ OP2(ORXREG1, OACST),
+ ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1)))
+
+INSN(bpos, s, bpos, branch, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX0(),
+ OP2(OLCST, ORREG1),
+ ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1)))
+
+INSN(call, s, ext_branch_cond_imm, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+ FIX0(),
+ OP1(OLCST),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(call, s, branch, branch, C62X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+ FIX1(FIX(s, 1)),
+ OP1(ORXREG1),
+ ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(call, s, b_irp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORIRP1),
+ ENC0())
+INSN(call, s, b_nrp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORNRP1),
+ ENC0())
+
+INSN(callnop, s, branch_nop_cst, branch, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+ FIX0(),
+ OP2(OLCST, OACST),
+ ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(callnop, nfu, s_branch_nop_cst, branch, C64XP,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+ FIX1(FIX(s, 0)),
+ OP2(OLCST, OACST),
+ ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(callnop, s, branch_nop_reg, branch, C64X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+ FIX1(FIX(s, 1)),
+ OP2(ORXREG1, OACST),
+ ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1)))
+
+INSN(callp, s, call_imm_nop, branch, C64XP,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+ FIX1(FIX(z, 1)),
+ OP2(OLCST, OWRETREG1),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+
+INSN(callret, s, ext_branch_cond_imm, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+ FIX0(),
+ OP1(OLCST),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(callret, s, branch, branch, C62X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+ FIX1(FIX(s, 1)),
+ OP1(ORXREG1),
+ ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(callret, s, b_irp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORIRP1),
+ ENC0())
+INSN(callret, s, b_nrp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORNRP1),
+ ENC0())
+
+INSN(clr, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x3)),
+ OP4(ORREG1, OACST, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+ ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(clr, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x3f)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpeq, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x53)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x52)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x51)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x50), FIX(x, 0)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+INSN(cmpeq2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1d)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeq4, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeqdp, s, 1_or_2_src, dpcmp, C67X, 0,
+ FIX1(FIX(op, 0x28)),
+ OP3(ORREGD12, ORXREGD12, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeqsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX1(FIX(op, 0x38)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpgt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x47)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x46)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x45)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x44), FIX(x, 0)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x57)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x56)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x55)),
+ OP3(ORREGL1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x54), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0),
+ ENC(dst, reg, 2)))
+
+INSN(cmpgt2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpgtdp, s, 1_or_2_src, dpcmp, C67X, 0,
+ FIX1(FIX(op, 0x29)),
+ OP3(ORREGD12, ORXREGD12, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpgtsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX1(FIX(op, 0x39)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpgtu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x4f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 0x4e), RAN(src1, 0, 15)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/* Although not mentioned in SPRUFE8, CMPGTU and CMPLTU support a
+ 5-bit unsigned constant operand on C64X and above. */
+INSNE(cmpgtu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX2(FIX(op, 0x4e), RAN(src1, 16, 31)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x4d)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 0, 15)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 16, 31)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+INSN(cmpgtu4, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmplt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x57)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x56)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x55)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x54), FIX(x, 0)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x47)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x46)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x45)),
+ OP3(ORREGL1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x44), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0),
+ ENC(dst, reg, 2)))
+
+INSN(cmplt2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpltdp, s, 1_or_2_src, dpcmp, C67X, 0,
+ FIX1(FIX(op, 0x2a)),
+ OP3(ORREGD12, ORXREGD12, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpltsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX1(FIX(op, 0x3a)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpltu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x5f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 0x5e), RAN(src1, 0, 15)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX2(FIX(op, 0x5e), RAN(src1, 16, 31)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x5d)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 0, 15)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 16, 31)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+INSN(cmpltu4, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpy, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0xa)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpyr, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0xb)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpyr1, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmtl, d, 1_or_2_src, load, ATOMIC,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(s, 1), FIX(op, 0xe), FIX(src1, 0)),
+ OP2(ORMEMDW, OWDREG5),
+ ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(ddotp4, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotph2, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x17)),
+ OP3(ORREGD1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotph2r, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORREGD1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotpl2, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x16)),
+ OP3(ORREGD1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotpl2r, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORREGD1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(deal, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1d)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(dint, nfu, dint, 1cycle, C64XP, 0,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSN(dmv, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xb)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(dotp2, m_s2_xs2_si, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(dotp2, m_s2_xs2_sll, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0xb)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpn2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x9)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpnrsu2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x7)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpnrus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x7)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotprsu2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0xd)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotprus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0xd)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpsu4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpu4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x6)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpack2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x34)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x33)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x8), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREG4),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x9), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREG4),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x1), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREG4),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x1)),
+ OP4(ORREG1, OACST, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+ ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(ext, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x2f)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(extu, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x0)),
+ OP4(ORREG1, OACST, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+ ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(extu, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x2b)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(gmpy, m, 1_or_2_src, 4cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x1f), FIX(x, 0)),
+ OP3(ORREG1, ORREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+/* This instruction can be predicated as usual; SPRUFE8 is incorrect
+ where it shows the "z" field as fixed to 1. */
+INSN(gmpy4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(idle, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MCNOP,
+ FIX2(FIX(s, 0), FIX(op, 0xf)),
+ OP0(),
+ ENC0())
+
+INSN(intdp, l, 1_or_2_src, intdp, C67X, 0,
+ FIX2(FIX(op, 0x39), FIX(src1, 0)),
+ OP2(ORXREG1, OWREGD45),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(intdpu, l, 1_or_2_src, intdp, C67X, 0,
+ FIX2(FIX(op, 0x3b), FIX(src1, 0)),
+ OP2(ORXREG1, OWREGD45),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(intsp, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX2(FIX(op, 0x4a), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(intspu, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX2(FIX(op, 0x49), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ldb, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 2), FIX(r, 0)),
+ OP2(ORMEMSB, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldb, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 2)),
+ OP2(ORMEMLB, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ldbu, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 1), FIX(r, 0)),
+ OP2(ORMEMSB, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldbu, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 1)),
+ OP2(ORMEMLB, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0),
+ ENC(dst, reg, 1)))
+
+INSN(lddw, d, load_store, load, C64X_AND_C67X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 6), FIX(r, 1)),
+ OP2(ORMEMSD, OWDREGD5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+
+INSN(ldh, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 4), FIX(r, 0)),
+ OP2(ORMEMSH, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldh, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 4)),
+ OP2(ORMEMLH, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ldhu, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 0), FIX(r, 0)),
+ OP2(ORMEMSH, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldhu, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0)),
+ OP2(ORMEMLH, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ldndw, d, load_nonaligned, load, C64X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+ FIX0(),
+ OP2(ORMEMND, OWDREGD5),
+ ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset_noscale, 0), ENC(baseR, reg, 0),
+ ENC(sc, scaled, 0), ENC(dst, reg_shift, 1)))
+
+INSN(ldnw, d, load_store, load, C64X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+ FIX2(FIX(op, 3), FIX(r, 1)),
+ OP2(ORMEMSW, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+
+INSN(ldw, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 6), FIX(r, 0)),
+ OP2(ORMEMSW, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldw, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 6)),
+ OP2(ORMEMLW, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ll, d, 1_or_2_src, load, ATOMIC,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(s, 1), FIX(op, 0xc), FIX(src1, 0)),
+ OP2(ORMEMDW, OWDREG5),
+ ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSNE(lmbd, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(lmbd, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6a)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(max2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x42)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(max2, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xd)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(maxu4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x43)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(min2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x41)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(min2, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(minu4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x48)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpy, m_sl16_xsl16_si, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x19)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(OACST, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpydp, m, mpy, mpydp, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x0e), FIX(x, 0)),
+ OP3(ORREGD1234, ORREGD1324, OWREGD910),
+ ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+INSN(mpyh, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x01)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhi, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhir, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhl, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x09)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhlu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x0f)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhslu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x0b)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhsu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x03)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x07)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhuls, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x0d)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhus, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x05)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpyi, m_si_xsi_si, m, mpy, mpyi, C67X, 0,
+ FIX1(FIX(op, 0x04)),
+ OP3(ORREG14, ORXREG14, OWREG9),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpyi, m_s5_xsi_si, m, mpy, mpyi, C67X, 0,
+ FIX1(FIX(op, 0x06)),
+ OP3(OACST, ORXREG14, OWREG9),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpyid, m_si_xsi_sll, m, mpy, mpyid, C67X, 0,
+ FIX1(FIX(op, 0x08)),
+ OP3(ORREG14, ORXREG14, OWREGD910),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpyid, m_s5_xsi_sll, m, mpy, mpyid, C67X, 0,
+ FIX1(FIX(op, 0x0c)),
+ OP3(OACST, ORXREG14, OWREGD910),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyih, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORXREG1, ORREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyihr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyil, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORXREG1, ORREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyilr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x0e)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylh, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylhu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x17)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyli, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylir, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x0e)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylshu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyluhs, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysp, m, mpy, 4cycle, C67X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRU733A, MPYSPDP and MPYSP2DP are on both C67X and
+ C67X+. */
+INSN(mpyspdp, m, compound, mpyspdp, C67X, 0,
+ FIX1(FIX(op, 0x16)),
+ OP3(ORREG12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysp2dp, m, compound, mpyspdp, C67X, 0,
+ FIX1(FIX(op, 0x17)),
+ OP3(ORREG1, ORXREG1, OWREGD45),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpysu, m_sl16_xul16_si, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1b)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpysu, m_s5_xul16_si, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP3(OACST, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysu4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x05)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1f)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyu4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x04)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyus, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1d)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x05)),
+ OP3(ORXREG1, ORREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x00)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy2ir, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x0f)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpy32, 32_32_32, m, mpy, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpy32, 32_32_64, m, mpy, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32su, m, mpy, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x16)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32u, m, compound, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32us, m, compound, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x19)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* "or" forms of "mv" are preferred over "add" forms when available
+ because "or" uses less power. However, 40-bit moves are only
+ available through "add", and before C64X D-unit moves are only
+ available through "add" (without cross paths being available). */
+INSNE(mv, l_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x7e), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(mv, l_sl_sl, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX3(FIX(op, 0x20), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGL1, OWREGL1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSNE(mv, s_xui_ui, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x1a), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(mv, d_si_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(0),
+ FIX2(FIX(op, 0x12), FIX(src1, 0)),
+ OP2(ORREG1, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSNE(mv, d_xui_ui, d, ext_1_or_2_src, 1cycle, C64X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 0x3), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(mvc, from_cr, s, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(s, 1), FIX(op, 0x0f), FIX(x, 0)),
+ OP2(ORCREG1, OWREG1),
+ ENC3(ENC(src1, crhi, 0), ENC(src2, crlo, 0), ENC(dst, reg, 1)))
+INSNE(mvc, to_cr, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_SIDE_B_ONLY,
+ FIX2(FIX(s, 1), FIX(op, 0x0e)),
+ OP2(ORXREG1, OWCREG1),
+ ENC4(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, crhi, 1),
+ ENC(dst, crlo, 1)))
+
+INSN(mvd, m, unary, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x1a)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(mvk, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(h, 0)),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, l, unary, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(x, 0), FIX(op, 0x05)),
+ OP2(OACST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src2, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, d, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x00), FIX(src2, 0)),
+ OP2(OACST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(dst, reg, 1)))
+
+INSN(mvkh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(h, 1)),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, lcst_high16, 0), ENC(dst, reg, 1)))
+
+INSN(mvklh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX1(FIX(h, 1)),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1)))
+
+INSN(mvkl, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX1(FIX(h, 0)),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1)))
+
+INSNE(neg, s_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x16), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(neg, l_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x06), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(neg, l_sl_sl, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x24), FIX(src1, 0)),
+ OP2(ORREGL1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(nop, nfu, nop_idle, nop, C62X, 0,
+ FIX2(FIX(s, 0), RAN(op, 0, 8)),
+ OP1(OACST),
+ ENC1(ENC(op, ucst_minus_one, 0)))
+INSNE(nop, 1, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(s, 0), FIX(op, 0)),
+ OP0(),
+ ENC0())
+
+INSNE(norm, l_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX2(FIX(op, 0x63), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(norm, l_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x60), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGL1, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(not, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x6e), FIX(src1, 0x1f)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(not, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x0a), FIX(src1, 0x1f)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(not, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0xf), FIX(src1, 0x1f)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(or, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x3)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7e)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1a)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(pack2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x0)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(pack2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0xf)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packh2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packh2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x9)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packh4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x69)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packhl2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packhl2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x8)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packlh2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packlh2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x68)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x2d), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREGD12),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX2(FIX(op, 0x3d), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ret, s, ext_branch_cond_imm, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX0(),
+ OP1(OLCST),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(ret, s, branch, branch, C62X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX1(FIX(s, 1)),
+ OP1(ORXREG1),
+ ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(ret, s, b_irp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORIRP1),
+ ENC0())
+INSN(ret, s, b_nrp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORNRP1),
+ ENC0())
+
+INSN(retp, s, call_imm_nop, branch, C64XP,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX1(FIX(z, 1)),
+ OP2(OLCST, OWRETREG1),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+
+INSN(rint, nfu, rint, 1cycle, C64XP, 0,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSNE(rotl, m_ui_xui_ui, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1d)),
+ OP3(ORXREG1, ORREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(rotl, m_u5_xui_ui, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP3(ORXREG1, OACST, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX2(FIX(op, 0xb), FIX(z, 1)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x2e), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREGD12),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX2(FIX(op, 0x3e), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(sadd, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x31)),
+ OP3(ORXREG1, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x12)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x30)),
+ OP3(OACST, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, s_si_xsi_si, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x20)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sadd2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x0)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x0e)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x0f)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsu2, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x1)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddus2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddu4, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x3)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sat, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x40), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGL1, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(set, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x2)),
+ OP4(ORREG1, OACST, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+ ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(set, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x3b)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(shfl, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(shfl3, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x36)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x33)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x31), FIX(x, 0)),
+ OP3(ORREGL1, ORREG1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(shl, s_xui_ui_ul, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORXREG1, ORREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x32)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x30), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSNE(shl, s_xui_u5_ul, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x12)),
+ OP3(ORXREG1, OACST, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(shlmb, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x61)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(shlmb, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x9)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shr, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x37)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shr, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x35), FIX(x, 0)),
+ OP3(ORREGL1, ORREG1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(shr, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x36)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shr, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x34), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(shr2, s_xs2_ui_s2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x7)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shr2, s_xs2_u5_s2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(shrmb, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x62)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(shrmb, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0xa)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shru, s_xui_ui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x27)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shru, s_ul_ui_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x25), FIX(x, 0)),
+ OP3(ORREGL1, ORREG1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(shru, s_xui_u5_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x26)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shru, s_ul_u5_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x24), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(shru2, s_xu2_ui_u2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x8)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shru2, s_xu2_u5_u2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x19)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(sl, d, 1_or_2_src, store, ATOMIC,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(s, 1), FIX(op, 0xd), FIX(src1, 0)),
+ OP2(ORDREG1, OWMEMDW),
+ ENC2(ENC(dst, reg, 0), ENC(src2, reg, 1)))
+
+INSN(smpy, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1a)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpyh, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x02)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpyhl, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x0a)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpylh, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x12)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpy2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x01)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRUFE8, this is the correct operand order for this
+ instruction. */
+INSN(smpy32, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x19)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spack2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spacku4, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x4)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spdp, s, 1_or_2_src, 2cycle_dp, C67X, 0,
+ FIX2(FIX(op, 0x02), FIX(src1, 0)),
+ OP2(ORXREG1, OWREGD12),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(spint, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX2(FIX(op, 0x0a), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(spkernel, nfu_2, nfu, spkernel, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+ FIX1(FIX(s, 0)),
+ OP2(OACST, OACST),
+ ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1)))
+INSNE(spkernel, nfu_0, nfu, spkernel, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL|TIC6X_FLAG_MACRO,
+ FIX2(FIX(s, 0), FIX(fstgfcyc, 0)),
+ OP0(),
+ ENC0())
+
+INSN(spkernelr, nfu, spkernelr, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSN(sploop, nfu, loop_buffer, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+ FIX4(FIX(s, 0), FIX(op, 0xc), FIX(csta, 0), RAN(cstb, 0, 13)),
+ OP1(OACST),
+ ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+INSN(sploopd, nfu, loop_buffer, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+ FIX4(FIX(s, 0), FIX(op, 0xd), FIX(csta, 0), RAN(cstb, 0, 13)),
+ OP1(OACST),
+ ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+INSN(sploopw, nfu, loop_buffer, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+ FIX4(FIX(s, 0), FIX(op, 0xf), FIX(csta, 0), RAN(cstb, 0, 13)),
+ OP1(OACST),
+ ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+ instruction. */
+INSN(spmask, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+ FIX2(FIX(s, 0), FIX(op, 0x8)),
+ OP1(OFULIST),
+ ENC1(ENC(mask, spmask, 0)))
+
+INSN(spmaskr, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+ FIX2(FIX(s, 0), FIX(op, 0x9)),
+ OP1(OFULIST),
+ ENC1(ENC(mask, spmask, 0)))
+
+INSN(sptrunc, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX2(FIX(op, 0x0b), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(sshl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x23)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(sshl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x22)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(sshvl, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP3(ORXREG1, ORREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+ instruction. */
+INSN(sshvr, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1a)),
+ OP3(ORXREG1, ORREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(ssub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x0f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x1f)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x0e)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x2c)),
+ OP3(OACST, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ssub2, l, 1_or_2_src, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x64)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(stb, d, load_store, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 3), FIX(r, 0)),
+ OP2(ORDREG1, OWMEMSB),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+INSN(stb, d, load_store_long, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 3)),
+ OP2(ORDREG1, OWMEMLB),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_byte, 1),
+ ENC(dst, reg, 0)))
+
+INSN(stdw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 4), FIX(r, 1)),
+ OP2(ORDREGD1, OWMEMSD),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+
+INSN(sth, d, load_store, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 5), FIX(r, 0)),
+ OP2(ORDREG1, OWMEMSH),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+INSN(sth, d, load_store_long, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 5)),
+ OP2(ORDREG1, OWMEMLH),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_half, 1),
+ ENC(dst, reg, 0)))
+
+INSN(stndw, d, store_nonaligned, store, C64X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+ FIX0(),
+ OP2(ORDREGD1, OWMEMND),
+ ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset_noscale, 1), ENC(baseR, reg, 1),
+ ENC(sc, scaled, 1), ENC(src, reg_shift, 0)))
+
+INSN(stnw, d, load_store, store, C64X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+ FIX2(FIX(op, 5), FIX(r, 1)),
+ OP2(ORDREG1, OWMEMSW),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+
+INSN(stw, d, load_store, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 7), FIX(r, 0)),
+ OP2(ORDREG1, OWMEMSW),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+INSN(stw, d, load_store_long, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 7)),
+ OP2(ORDREG1, OWMEMLW),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_word, 1),
+ ENC(dst, reg, 0)))
+
+INSNE(sub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x07)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x17)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x27)),
+ OP3(ORREG1, ORXREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_si_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x37)),
+ OP3(ORXREG1, ORREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x06)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x24)),
+ OP3(OACST, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_s5_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(sub, l_sl_s5_sl, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x20), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst_negate, 1), ENC(src2, reg, 0),
+ ENC(dst, reg, 2)))
+INSNE(sub, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x17)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x16)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/* Contrary to SPRUFE8, this is the correct encoding for this
+ instruction; this instruction can be predicated. */
+INSNE(sub, s_xsi_si_si, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x5)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, s_xsi_s5_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x6)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(sub, d_si_si_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(sub, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSNE(sub, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x31)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(subab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x33)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSN(subabs4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x5a)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x35)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(subah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x37)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(subaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x39)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(subaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x3b)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSN(subc, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x4b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subdp, l_dp_xdp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x19)),
+ OP3(ORREGD12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, l_xdp_dp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x1d)),
+ OP3(ORXREGD12, ORREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, s_dp_xdp_dp, s, l_1_or_2_src, addsubdp, C67XP,
+ TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x73)),
+ OP3(ORREGD12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, s_xdp_dp_dp, s, l_1_or_2_src, addsubdp, C67XP,
+ TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x77)),
+ OP3(ORXREGD12, ORREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subsp, l_sp_xsp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, l_xsp_sp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x15)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, s_sp_xsp_sp, s, l_1_or_2_src, 4cycle, C67XP,
+ TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x71)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, s_xsp_sp_sp, s, l_1_or_2_src, 4cycle, C67XP,
+ TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x75)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x2f)),
+ OP3(ORREG1, ORXREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subu, l_xui_ui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x3f)),
+ OP3(ORXREG1, ORREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sub2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x04)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub2, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub2, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x5)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sub4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x66)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(swap2, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x1b), FIX(x, 0)),
+ OP2(ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSN(swap2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x10), FIX(x, 0)),
+ OP2(ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+ instruction. */
+INSN(swap4, l, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(swe, nfu, swe, 1cycle, C64XP, 0,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSN(swenr, nfu, swenr, 1cycle, C64XP, 0,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSN(unpkhu4, l, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x03)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(unpkhu4, s, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x03)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(unpklu4, l, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x02)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(unpklu4, s, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x02)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(xor, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6e)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x0b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x0a)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0xe)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0xf)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(xormpy, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x1b)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(xpnd2, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x19)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(xpnd4, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x18)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(zero, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX2(FIX(h, 0), FIX(cst, 0)),
+ OP1(OWREG1),
+ ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSN(zero, l, unary, 1cycle, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+ FIX3(FIX(x, 0), FIX(op, 0x05), FIX(src2, 0)),
+ OP1(OWREG1),
+ ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSNE(zero, l_sub, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+ FIX2(FIX(op, 0x07), FIX(x, 0)),
+ OP1(OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0),
+ ENC(dst, reg, 0)))
+INSNE(zero, l_sub_sl, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x27), FIX(x, 0)),
+ OP1(OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0),
+ ENC(dst, reg, 0)))
+INSNE(zero, d_mvk, d, 1_or_2_src, 1cycle, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+ FIX3(FIX(op, 0x00), FIX(src1, 0), FIX(src2, 0)),
+ OP1(OWREG1),
+ ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x11)),
+ OP1(OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg_unused, 0), ENC(src1, reg_unused, 0),
+ ENC(dst, reg, 0)))
+
+#undef TIC6X_INSN_C64X_AND_C67X
+#undef tic6x_insn_format_nfu_s_branch_nop_cst
+#undef tic6x_insn_format_s_l_1_or_2_src
+#undef RAN
+#undef FIX
+#undef FIX0
+#undef FIX1
+#undef FIX2
+#undef FIX3
+#undef FIX4
+#undef OP0
+#undef OP1
+#undef OP2
+#undef OP3
+#undef OP4
+#undef OACST
+#undef OLCST
+#undef OFULIST
+#undef ORIRP1
+#undef ORNRP1
+#undef OWREG1
+#undef OWRETREG1
+#undef ORREG1
+#undef ORDREG1
+#undef ORWREG1
+#undef ORAREG1
+#undef ORXREG1
+#undef ORREG12
+#undef ORREG14
+#undef ORXREG14
+#undef OWREG2
+#undef OWREG4
+#undef OWREG9
+#undef OWDREG5
+#undef OWREGL1
+#undef ORREGL1
+#undef OWREGD1
+#undef OWREGD12
+#undef OWREGD4
+#undef ORREGD1
+#undef OWREGD45
+#undef OWREGD67
+#undef ORDREGD1
+#undef OWDREGD5
+#undef ORREGD12
+#undef ORXREGD12
+#undef ORREGD1234
+#undef ORREGD1324
+#undef OWREGD910
+#undef ORCREG1
+#undef OWCREG1
+#undef ORMEMDW
+#undef OWMEMDW
+#undef ORMEMSB
+#undef OWMEMSB
+#undef ORMEMLB
+#undef OWMEMLB
+#undef ORMEMSH
+#undef OWMEMSH
+#undef ORMEMLH
+#undef OWMEMLH
+#undef ORMEMSW
+#undef OWMEMSW
+#undef ORMEMLW
+#undef OWMEMLW
+#undef ORMEMSD
+#undef OWMEMSD
+#undef ORMEMND
+#undef OWMEMND
+#undef ENC
+#undef ENC0
+#undef ENC1
+#undef ENC2
+#undef ENC3
+#undef ENC4
+#undef ENC5
+#undef ENC6
+#undef ENC7
--- /dev/null
+/* TI C6X opcode information.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#ifndef OPCODE_TIC6X_H
+#define OPCODE_TIC6X_H
+
+#include "bfd.h"
+#include "symcat.h"
+
+/* A field in an instruction format. The names are based on those
+ used in the architecture manuals. */
+typedef enum
+ {
+ tic6x_field_baseR,
+ tic6x_field_creg,
+ tic6x_field_cst,
+ tic6x_field_csta,
+ tic6x_field_cstb,
+ tic6x_field_dst,
+ tic6x_field_fstgfcyc,
+ tic6x_field_h,
+ tic6x_field_mask,
+ tic6x_field_mode,
+ tic6x_field_offsetR,
+ tic6x_field_op,
+ tic6x_field_p,
+ tic6x_field_r,
+ tic6x_field_s,
+ tic6x_field_sc,
+ tic6x_field_src,
+ tic6x_field_src1,
+ tic6x_field_src2,
+ tic6x_field_srcdst,
+ tic6x_field_x,
+ tic6x_field_y,
+ tic6x_field_z
+ } tic6x_insn_field_id;
+
+typedef struct
+{
+ /* The name used to reference the field. */
+ tic6x_insn_field_id field_id;
+
+ /* The least-significant bit position in the field. */
+ unsigned short low_pos;
+
+ /* The number of bits in the field. */
+ unsigned short width;
+} tic6x_insn_field;
+
+/* Maximum number of variable fields in an instruction format. */
+#define TIC6X_MAX_INSN_FIELDS 11
+
+/* A particular instruction format. */
+typedef struct
+{
+ /* How many bits in the instruction. */
+ unsigned int num_bits;
+
+ /* Constant bits in the instruction. */
+ unsigned int cst_bits;
+
+ /* Mask matching those bits. */
+ unsigned int mask;
+
+ /* The number of instruction fields. */
+ unsigned int num_fields;
+
+ /* Descriptions of instruction fields. */
+ tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS];
+} tic6x_insn_format;
+
+/* An index into the table of instruction formats. */
+typedef enum
+ {
+#define FMT(name, num_bits, cst_bits, mask, fields) \
+ CONCAT2(tic6x_insn_format_, name),
+#include "tic6x-insn-formats.h"
+#undef FMT
+ tic6x_insn_format_max
+ } tic6x_insn_format_id;
+
+/* The table itself. */
+extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max];
+
+/* If instruction format FMT has a field FIELD, return a pointer to
+ the description of that field; otherwise return NULL. */
+
+const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt,
+ tic6x_insn_field_id field);
+
+/* Description of a field (in an instruction format) whose value is
+ fixed, or constrained to be in a particular range, in a particular
+ opcode. */
+typedef struct
+{
+ /* The name of the field. */
+ tic6x_insn_field_id field_id;
+
+ /* The least value of the field in this instruction. */
+ unsigned int min_val;
+
+ /* The greatest value of the field in this instruction. */
+ unsigned int max_val;
+} tic6x_fixed_field;
+
+/* Bit-masks for defining instructions present on some subset of
+ processors; each indicates an instruction present on that processor
+ and those that are supersets of it. The options passed to the
+ assembler determine a bit-mask ANDed with the bit-mask indicating
+ when the instruction was added to determine whether the instruction
+ is enabled. */
+#define TIC6X_INSN_C62X 0x0001
+#define TIC6X_INSN_C64X 0x0002
+#define TIC6X_INSN_C64XP 0x0004
+#define TIC6X_INSN_C67X 0x0008
+#define TIC6X_INSN_C67XP 0x0010
+#define TIC6X_INSN_C674X 0x0020
+#define TIC6X_INSN_ATOMIC 0x0040
+
+/* Flags with further information about an opcode table entry. */
+
+/* Only used by the assembler, not the disassembler. */
+#define TIC6X_FLAG_MACRO 0x0001
+
+/* Must be first in its execute packet. */
+#define TIC6X_FLAG_FIRST 0x0002
+
+/* Multi-cycle NOP (not used for the NOP n instruction itself, which
+ is only a multicycle NOP if n > 1). */
+#define TIC6X_FLAG_MCNOP 0x0004
+
+/* Cannot be in parallel with a multi-cycle NOP. */
+#define TIC6X_FLAG_NO_MCNOP 0x0008
+
+/* Load instruction. */
+#define TIC6X_FLAG_LOAD 0x0010
+
+/* Store instruction. */
+#define TIC6X_FLAG_STORE 0x0020
+
+/* Unaligned memory operation. */
+#define TIC6X_FLAG_UNALIGNED 0x0040
+
+/* Only on side B. */
+#define TIC6X_FLAG_SIDE_B_ONLY 0x0080
+
+/* Only on data path T2. */
+#define TIC6X_FLAG_SIDE_T2_ONLY 0x0100
+
+/* Does not support cross paths. */
+#define TIC6X_FLAG_NO_CROSS 0x0200
+
+/* Annotate this branch instruction as a call. */
+#define TIC6X_FLAG_CALL 0x0400
+
+/* Annotate this branch instruction as a return. */
+#define TIC6X_FLAG_RETURN 0x0800
+
+/* This instruction starts a software pipelined loop. */
+#define TIC6X_FLAG_SPLOOP 0x1000
+
+/* This instruction ends a software pipelined loop. */
+#define TIC6X_FLAG_SPKERNEL 0x2000
+
+/* This instruction takes a list of functional units as parameters;
+ although described as having one parameter, the number may be 0 to
+ 8. */
+#define TIC6X_FLAG_SPMASK 0x4000
+
+/* When more than one opcode matches the assembly source, prefer the
+ one with the highest value for this bit-field. If two opcode table
+ entries can match the same syntactic form, they must have different
+ values here. */
+#define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15)
+#define TIC6X_FLAG_PREFER(n) ((n) << 15)
+#define TIC6X_NUM_PREFER 2
+
+/* Maximum number of fixed fields for a particular opcode. */
+#define TIC6X_MAX_FIXED_FIELDS 4
+
+/* Maximum number of operands in the opcode table for a particular
+ opcode. */
+#define TIC6X_MAX_OPERANDS 4
+
+/* Maximum number of operands in the source code for a particular
+ opcode (different from the number in the opcode table for SPMASK
+ and SPMASKR). */
+#define TIC6X_MAX_SOURCE_OPERANDS 8
+
+/* Maximum number of variable fields for a particular opcode. */
+#define TIC6X_MAX_VAR_FIELDS 7
+
+/* Which functional units an opcode uses. This only describes the
+ basic choice of D, L, M, S or no functional unit; other fields are
+ used to describe further restrictions (instructions only operating
+ on one side), use of cross paths and load/store instructions using
+ one side for the address and the other side for the source or
+ destination register. */
+typedef enum
+ {
+ tic6x_func_unit_d,
+ tic6x_func_unit_l,
+ tic6x_func_unit_m,
+ tic6x_func_unit_s,
+ tic6x_func_unit_nfu
+ } tic6x_func_unit_base;
+
+/* Possible forms of source operand. */
+typedef enum
+ {
+ /* An assembly-time constant. */
+ tic6x_operand_asm_const,
+ /* A link-time constant. */
+ tic6x_operand_link_const,
+ /* A register, from the same side as the functional unit
+ selected. */
+ tic6x_operand_reg,
+ /* A register, that is from the other side if a cross path is
+ used. */
+ tic6x_operand_xreg,
+ /* A register, that is from the side of the data path
+ selected. */
+ tic6x_operand_dreg,
+ /* An address register usable with 15-bit offsets (B14 or B15).
+ This is from the same side as the functional unit if a cross
+ path is not used, and the other side if a cross path is
+ used. */
+ tic6x_operand_areg,
+ /* A return address register (A3 or B3), from the same side as the
+ functional unit selected. */
+ tic6x_operand_retreg,
+ /* A register pair, from the same side as the functional unit
+ selected. */
+ tic6x_operand_regpair,
+ /* A register pair, that is from the other side if a cross path is
+ used. */
+ tic6x_operand_xregpair,
+ /* A register pair, from the side of the data path selected. */
+ tic6x_operand_dregpair,
+ /* The literal string "irp" (case-insensitive). */
+ tic6x_operand_irp,
+ /* The literal string "nrp" (case-insensitive). */
+ tic6x_operand_nrp,
+ /* A control register. */
+ tic6x_operand_ctrl,
+ /* A memory reference (base and offset registers from the side of
+ the functional unit selected), using either unsigned 5-bit
+ constant or register offset, if any offset; register offsets
+ cannot use unscaled () syntax. */
+ tic6x_operand_mem_short,
+ /* A memory reference (base and offset registers from the side of
+ the functional unit selected), using either unsigned 5-bit
+ constant or register offset, if any offset; register offsets
+ can use unscaled () syntax (for LDNDW and STNDW). */
+ tic6x_operand_mem_ndw,
+ /* A memory reference using 15-bit link-time constant offset
+ relative to B14 or B15. */
+ tic6x_operand_mem_long,
+ /* A memory reference that only dereferences a register with no
+ further adjustments (*REG), that register being from the side
+ of the functional unit selected. */
+ tic6x_operand_mem_deref,
+ /* A functional unit name or a list thereof (for SPMASK and
+ SPMASKR). */
+ tic6x_operand_func_unit
+ } tic6x_operand_form;
+
+/* Whether something is, or can be, read or written. */
+typedef enum
+ {
+ tic6x_rw_none,
+ tic6x_rw_read,
+ tic6x_rw_write,
+ tic6x_rw_read_write
+ } tic6x_rw;
+
+/* Description of a source operand and how it is used. */
+typedef struct
+{
+ /* The syntactic form of the operand. */
+ tic6x_operand_form form;
+
+ /* For non-constant operands, the size in bytes (1, 2, 4, 5 or
+ 8). Ignored for constant operands. */
+ unsigned int size;
+
+ /* Whether the operand is read, written or both. In addition to the
+ operations described here, address registers are read on cycle 1
+ regardless of when the memory operand is read or written, and may
+ be modified as described by the addressing mode, and control
+ registers may be implicitly read by some instructions. There are
+ also some special cases not fully described by this
+ structure.
+
+ - For mpydp, the low part of src2 is read on cycles 1 and 3 but
+ not 2, and the high part on cycles 2 and 4 but not 3.
+
+ - The swap2 pseudo-operation maps to packlh2, reading the first
+ operand of swap2 twice. */
+ tic6x_rw rw;
+
+ /* The first and last cycles (1 for E1, etc.) at which the operand,
+ or the low part for two-register operands, is read or
+ written. */
+ unsigned short low_first;
+ unsigned short low_last;
+
+ /* Likewise, for the high part. */
+ unsigned short high_first;
+ unsigned short high_last;
+} tic6x_operand_info;
+
+/* Ways of converting an operand or functional unit specifier to a
+ field value. */
+typedef enum
+ {
+ /* Store an unsigned assembly-time constant (which must fit) in
+ the field. */
+ tic6x_coding_ucst,
+ /* Store a signed constant (which must fit) in the field. This
+ may be used both for assembly-time constants and for link-time
+ constants. */
+ tic6x_coding_scst,
+ /* Subtract one from an unsigned assembly-time constant (which
+ must be strictly positive before the subtraction) and store the
+ value (which must fit) in the field. */
+ tic6x_coding_ucst_minus_one,
+ /* Negate a signed assembly-time constant, and store the result of
+ negation (which must fit) in the field. Used only for
+ pseudo-operations. */
+ tic6x_coding_scst_negate,
+ /* Store an unsigned link-time constant, implicitly DP-relative
+ and counting in bytes, in the field. For expression operands,
+ assembly-time constants are encoded as-is. For memory
+ reference operands, the offset is encoded as-is if [] syntax is
+ used and shifted if () is used. */
+ tic6x_coding_ulcst_dpr_byte,
+ /* Store an unsigned link-time constant, implicitly DP-relative
+ and counting in half-words, in the field. For expression
+ operands, assembly-time constants are encoded as-is. For
+ memory reference operands, the offset is encoded as-is if []
+ syntax is used and shifted if () is used. */
+ tic6x_coding_ulcst_dpr_half,
+ /* Store an unsigned link-time constant, implicitly DP-relative
+ and counting in words, in the field. For expression operands,
+ assembly-time constants are encoded as-is. For memory
+ reference operands, the offset is encoded as-is if [] syntax is
+ used and shifted if () is used. */
+ tic6x_coding_ulcst_dpr_word,
+ /* Store the low 16 bits of a link-time constant in the field;
+ considered unsigned for disassembly. */
+ tic6x_coding_lcst_low16,
+ /* Store the high 16 bits of a link-time constant in the field;
+ considered unsigned for disassembly. */
+ tic6x_coding_lcst_high16,
+ /* Store a signed PC-relative value (address of label minus
+ address of fetch packet containing the current instruction,
+ counted in words) in the field. */
+ tic6x_coding_pcrel,
+ /* Likewise, but counting in half-words if in a header-based fetch
+ packet. */
+ tic6x_coding_pcrel_half,
+ /* Encode the register number (even number for a register pair) in
+ the field. When applied to a memory reference, encode the base
+ register. */
+ tic6x_coding_reg,
+ /* Store 0 for register B14, 1 for register B15. When applied to
+ a memory reference, encode the base register. */
+ tic6x_coding_areg,
+ /* Store the low part of a control register address. */
+ tic6x_coding_crlo,
+ /* Store the high part of a control register address. */
+ tic6x_coding_crhi,
+ /* Encode the even register number for a register pair, shifted
+ right by one bit. */
+ tic6x_coding_reg_shift,
+ /* Store either the offset register or the 5-bit unsigned offset
+ for a memory reference. If an offset uses the unscaled ()
+ form, which is only permitted with constants, it is scaled
+ according to the access size of the operand before being
+ stored. */
+ tic6x_coding_mem_offset,
+ /* Store either the offset register or the 5-bit unsigned offset
+ for a memory reference, but with no scaling applied to the
+ offset (for nonaligned doubleword operations). */
+ tic6x_coding_mem_offset_noscale,
+ /* Store the addressing mode for a memory reference. */
+ tic6x_coding_mem_mode,
+ /* Store whether a memory reference is scaled. */
+ tic6x_coding_scaled,
+ /* Store the stage in an SPKERNEL instruction in the upper part of
+ the field. */
+ tic6x_coding_fstg,
+ /* Store the cycle in an SPKERNEL instruction in the lower part of
+ the field. */
+ tic6x_coding_fcyc,
+ /* Store the mask bits for functional units in the field in an
+ SPMASK or SPMASKR instruction. */
+ tic6x_coding_spmask,
+ /* Store the number of a register that is unused, or minimally
+ used, in this execute packet. The number must be the same for
+ all uses of this coding in a single instruction, but may be
+ different for different instructions in the execute packet.
+ This is for the "zero" pseudo-operation. This is not safe when
+ reads may occur from instructions in previous execute packets;
+ in such cases the programmer or compiler should use explicit
+ "sub" instructions for those cases of "zero" that cannot be
+ implemented as "mvk" for the processor specified. */
+ tic6x_coding_reg_unused,
+ /* Store 1 if the functional unit used is on side B, 0 for side
+ A. */
+ tic6x_coding_fu,
+ /* Store 1 if the data path used (source register for store,
+ destination for load) is on side B, 0 for side A. */
+ tic6x_coding_data_fu,
+ /* Store 1 if the cross path is being used, 0 otherwise. */
+ tic6x_coding_xpath
+ } tic6x_coding_method;
+
+/* How to generate the value of a particular field. */
+typedef struct
+{
+ /* The name of the field. */
+ tic6x_insn_field_id field_id;
+
+ /* How it is encoded. */
+ tic6x_coding_method coding_method;
+
+ /* Source operand number, if any. */
+ unsigned int operand_num;
+} tic6x_coding_field;
+
+/* Types of instruction for pipeline purposes. The type determines
+ functional unit and cross path latency (when the same functional
+ unit can be used by other instructions, when the same cross path
+ can be used by other instructions). */
+typedef enum
+ {
+ tic6x_pipeline_nop,
+ tic6x_pipeline_1cycle,
+ tic6x_pipeline_1616_m,
+ tic6x_pipeline_store,
+ tic6x_pipeline_mul_ext,
+ tic6x_pipeline_load,
+ tic6x_pipeline_branch,
+ tic6x_pipeline_2cycle_dp,
+ tic6x_pipeline_4cycle,
+ tic6x_pipeline_intdp,
+ tic6x_pipeline_dpcmp,
+ tic6x_pipeline_addsubdp,
+ tic6x_pipeline_mpyi,
+ tic6x_pipeline_mpyid,
+ tic6x_pipeline_mpydp,
+ tic6x_pipeline_mpyspdp,
+ tic6x_pipeline_mpysp2dp
+ } tic6x_pipeline_type;
+
+/* Description of a control register. */
+typedef struct
+{
+ /* The name of the register. */
+ const char *name;
+
+ /* Which ISA variants include this control register. */
+ unsigned short isa_variants;
+
+ /* Whether it can be read, written or both (in supervisor mode).
+ Some registers use the same address, but different names, for
+ reading and writing. */
+ tic6x_rw rw;
+
+ /* crlo value for this register. */
+ unsigned int crlo;
+
+ /* Mask that, ANDed with the crhi value in the instruction, must be
+ 0. 0 is always generated when generating code. */
+ unsigned int crhi_mask;
+} tic6x_ctrl;
+
+/* An index into the table of control registers. */
+typedef enum
+ {
+#define CTRL(name, isa, rw, crlo, crhi_mask) \
+ CONCAT2(tic6x_ctrl_,name),
+#include "tic6x-control-registers.h"
+#undef CTRL
+ tic6x_ctrl_max
+ } tic6x_ctrl_id;
+
+/* The table itself. */
+extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max];
+
+/* An entry in the opcode table. */
+typedef struct
+{
+ /* The name of the instruction. */
+ const char *name;
+
+ /* Functional unit used by this instruction (basic information). */
+ tic6x_func_unit_base func_unit;
+
+ /* The format of this instruction. */
+ tic6x_insn_format_id format;
+
+ /* The pipeline type of this instruction. */
+ tic6x_pipeline_type type;
+
+ /* Which ISA variants include this instruction. */
+ unsigned short isa_variants;
+
+ /* Flags for this instruction. */
+ unsigned short flags;
+
+ /* Number of fixed fields, or fields with restricted value ranges,
+ for this instruction. */
+ unsigned int num_fixed_fields;
+
+ /* Values of fields fixed for this instruction. */
+ tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS];
+
+ /* The number of operands in the source form of this
+ instruction. */
+ unsigned int num_operands;
+
+ /* Information about individual operands. */
+ tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS];
+
+ /* The number of variable fields for this instruction with encoding
+ instructions explicitly given. */
+ unsigned int num_variable_fields;
+
+ /* How fields (other than ones with fixed value) are computed from
+ the source operands and functional unit specifiers. In addition
+ to fields specified here:
+
+ - creg, if present, is set from the predicate, along with z which
+ must be present if creg is present.
+
+ - p, if present (on all non-compact instructions), is set from
+ the parallel bars.
+ */
+ tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS];
+} tic6x_opcode;
+
+/* An index into the table of opcodes. */
+typedef enum
+ {
+#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \
+ CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
+#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
+ CONCAT4(tic6x_opcode_,name,_,e),
+#include "tic6x-opcode-table.h"
+#undef INSN
+#undef INSNE
+ tic6x_opcode_max
+ } tic6x_opcode_id;
+
+/* The table itself. */
+extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max];
+
+/* A linked list of opcodes. */
+typedef struct tic6x_opcode_list_tag
+{
+ tic6x_opcode_id id;
+ struct tic6x_opcode_list_tag *next;
+} tic6x_opcode_list;
+
+/* The information from a fetch packet header. */
+typedef struct
+{
+ /* The header itself. */
+ unsigned int header;
+
+ /* Whether each word uses compact instructions. */
+ bfd_boolean word_compact[7];
+
+ /* Whether loads are protected. */
+ bfd_boolean prot;
+
+ /* Whether instructions use the high register set. */
+ bfd_boolean rs;
+
+ /* Data size. */
+ unsigned int dsz;
+
+ /* Whether compact instructions in the S unit are decoded as
+ branches. */
+ bfd_boolean br;
+
+ /* Whether compact instructions saturate. */
+ bfd_boolean sat;
+
+ /* P-bits. */
+ bfd_boolean p_bits[14];
+} tic6x_fetch_packet_header;
+
+#endif /* OPCODE_TIC6X_H */
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and
+ eelf32_tic6x_le.o.
+ (eelf32_tic6x_be.c, eelf32_tic6x_le.c): New.
+ * NEWS: Add news entry for TI C6X support.
+ * configure.tgt (tic6x-*-*): New.
+ * emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New.
+
2010-03-23 Joseph Myers <joseph@codesourcery.com>
* scripttempl/elf.sc (RODATA_NAME, SDATA_NAME, SBSS_NAME,
eelf32_sparc.o \
eelf32_sparc_sol2.o \
eelf32_sparc_vxworks.o \
+ eelf32_tic6x_be.o \
+ eelf32_tic6x_le.o \
eelf32b4300.o \
eelf32bfin.o \
eelf32bfinfd.o \
eelf32_dlx.c: $(srcdir)/emulparams/elf32_dlx.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/dlx.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32_dlx "$(tdir_elf32_dlx)"
+eelf32_tic6x_be.c: $(srcdir)/emulparams/elf32_tic6x_be.sh \
+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32_tic6x_be "$(tdir_elf32_tic6x_be)"
+eelf32_tic6x_le.c: $(srcdir)/emulparams/elf32_tic6x_le.sh \
+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32_tic6x_le "$(tdir_elf32_tic6x_le)"
eelf32xc16x.c: $(srcdir)/emulparams/elf32xc16x.sh \
$(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
eelf32_sparc.o \
eelf32_sparc_sol2.o \
eelf32_sparc_vxworks.o \
+ eelf32_tic6x_be.o \
+ eelf32_tic6x_le.o \
eelf32b4300.o \
eelf32bfin.o \
eelf32bfinfd.o \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_sparc_sol2.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_sparc_vxworks.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_spu.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_tic6x_be.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_tic6x_le.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32b4300.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bfin.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bfinfd.Po@am__quote@
eelf32_dlx.c: $(srcdir)/emulparams/elf32_dlx.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/dlx.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32_dlx "$(tdir_elf32_dlx)"
+eelf32_tic6x_be.c: $(srcdir)/emulparams/elf32_tic6x_be.sh \
+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32_tic6x_be "$(tdir_elf32_tic6x_be)"
+eelf32_tic6x_le.c: $(srcdir)/emulparams/elf32_tic6x_le.sh \
+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32_tic6x_le "$(tdir_elf32_tic6x_le)"
eelf32xc16x.c: $(srcdir)/emulparams/elf32xc16x.sh \
$(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
-*- text -*-
+* Add support for the TMS320C6000 (TI C6X) processor family.
+
* --add-needed renamed to --copy-dt-needed-entries in order to avoid confusion
with --as-needed option.
tic30-*-*coff*) targ_emul=tic30coff ;;
tic4x-*-* | c4x-*-*) targ_emul=tic4xcoff ; targ_extra_emuls="tic3xcoff tic3xcoff_onchip" ;;
tic54x-*-* | c54x*-*-*) targ_emul=tic54xcoff ;;
+tic6x-*-*) targ_emul=elf32_tic6x_le
+ targ_extra_emuls="elf32_tic6x_be"
+ ;;
tic80-*-*) targ_emul=tic80coff
;;
v850-*-*) targ_emul=v850 ;;
--- /dev/null
+. ${srcdir}/emulparams/elf32_tic6x_le.sh
+OUTPUT_FORMAT="elf32-tic6x-be"
--- /dev/null
+SCRIPT_NAME=elf
+TEMPLATE_NAME=elf32
+OUTPUT_FORMAT="elf32-tic6x-le"
+# This address is an arbitrary value expected to be suitable for
+# semihosting simulator use, but not on hardware where it is expected
+# to be overridden.
+TEXT_START_ADDR=0x8000
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+ARCH=tic6x
+EXECUTABLE_SYMBOLS="EXTERN (__c6xabi_DSBT_BASE);"
+SDATA_START_SYMBOLS="PROVIDE_HIDDEN (__c6xabi_DSBT_BASE = .);"
+# ".bss" is near (small) BSS, ".far" is far (normal) BSS, ".const" is
+# far read-only data, ".rodata" is near read-only data. ".neardata"
+# is near (small) data, ".fardata" is (along with .data) far data.
+RODATA_NAME="const"
+SDATA_NAME="neardata"
+SBSS_NAME="bss"
+BSS_NAME="far"
+OTHER_SDATA_SECTIONS=".rodata ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.*}) }"
+OTHER_READONLY_RELOC_SECTIONS="
+ .rel.rodata ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.*}) }
+ .rela.rodata ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.*}) }"
+OTHER_READWRITE_SECTIONS=".fardata ${RELOCATING-0} : { *(.fardata${RELOCATING+ .fardata.*}) }"
+OTHER_READWRITE_RELOC_SECTIONS="
+ .rel.fardata ${RELOCATING-0} : { *(.rel.fardata${RELOCATING+ .rel.fardata.*}) }
+ .rela.fardata ${RELOCATING-0} : { *(.rela.fardata${RELOCATING+ .rela.fardata.*}) }"
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x-*-*.
+ * ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x-*-*.
+ * ld-tic6x: New directory and testcases.
+
2010-03-19 Jie Zhang <jie@codesourcery.com>
PR ld/11304
#objcopy_linked_file: --set-section-flags .post_text_reserve=contents,alloc,load,readonly,code
#readelf: -l --wide
#xfail: "arm*-*-*" "xscale-*-*"
-#xfail: "avr-*-*" "dlx-*-*" "h8300-*-*" "m32r-*-*" "msp430-*-*"
+#xfail: "avr-*-*" "dlx-*-*" "h8300-*-*" "m32r-*-*" "msp430-*-*" "tic6x-*-*"
#xfail: "*-*-hpux*"
# Fails on the ARM because the .section type character is % rather than @.
-# Fails on the AVR, DLX, H8300, M32R and MSP430 because the two sections
-# are not merged into one segment. (There is no good reason why they have to be).
+# Fails on the AVR, DLX, H8300, M32R, MSP430 and TI C6X because the two
+# sections are not merged into one segment. (There is no good reason why
+# they have to be).
# Fails on HPUX systems because the .type pseudo-op behaves differently.
#...
#xfail: "dlx-*-*" "fr30-*-*" "frv-*-*" "hppa*64*-*-*" "h8300-*-*" "score-*-*"
#xfail: "i370-*-*" "i860-*-*" "i960-*-*" "ip2k-*-*" "iq2000-*-*" "lm32-*-*"
#xfail: "mcore-*-*" "mn102*-*-*" "mips*-*-*" "ms1-*-*" "msp430-*-*" "mep-*-*"
-#xfail: "or32-*-*" "pj-*-*" "sparc*-*-*" "vax-*-*" "xstormy16-*-*" "xtensa*-*-*"
+#xfail: "or32-*-*" "pj-*-*" "sparc*-*-*" "tic6x-*-*" "vax-*-*" "xstormy16-*-*"
+#xfail: "xtensa*-*-*"
.*: file format .*elf.*
# Test the assigment of sections to segments.
#
-# Copyright 2008 Free Software Foundation, Inc.
+# Copyright 2008, 2010 Free Software Foundation, Inc.
# Contributed by Red Hat.
#
# This file is part of the GNU Binutils.
|| [istarget m32r-*-*]
|| [istarget m88k-*-*]
|| [istarget msp430-*-*]
+ || [istarget tic6x-*-*]
} {
set B_test_same_seg 0
} else {
--- /dev/null
+#name: C6X data relocations, global symbols
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s0=0 --defsym sff=0xff --defsym sffff=0xffff --defsym s80000000=0x80000000 --defsym sffff8000=0xffff8000 --defsym sffffff80=0xffffff80 --defsym sffffffff=0xffffffff
+#source: data-reloc-global.s
+#objdump: -r -s -j .data
+
+.*: *file format elf32-tic6x-le
+
+Contents of section \.data:
+[ \t]*0080 00000080 ffffffff 00000000 feffffff .*
+[ \t]*0090 00000000 ffffffff 00800080 0000ffff .*
+[ \t]*00a0 808000 .*
--- /dev/null
+.globl s0
+.globl sff
+.globl sffff
+.globl s80000000
+.globl sffff8000
+.globl sffffff80
+.globl sffffffff
+.data
+ .word s80000000
+ .word sffffffff
+ .word s0
+ .word sffffffff+0xffffffff
+ .word s80000000+0x80000000
+ .short sffffffff
+ .short sffff
+ .short sffff8000
+ .short s0-0x8000
+ .short s80000000+0x80000000
+ .byte sffffffff
+ .byte sff
+ .byte sffffff80
+ .byte s0-0x80
+ .byte s80000000+0x80000000
--- /dev/null
+.data
+a:
+ .word a
+b:
+ .word b
--- /dev/null
+.data
+c:
+ .word d
+d:
+ .word c
+ .short d
+ .byte c
+ .byte d
--- /dev/null
+#name: C6X data relocations, local symbols, -r
+#as: -mlittle-endian
+#ld: -r -melf32_tic6x_le
+#source: data-reloc-local-1.s
+#source: data-reloc-local-2.s
+#objdump: -r -s -j .data
+
+.*: *file format elf32-tic6x-le
+
+RELOCATION RECORDS FOR \[\.data\]:
+OFFSET TYPE VALUE
+0+ R_C6000_ABS32 \.data
+0+4 R_C6000_ABS32 \.data\+0x00000004
+0+8 R_C6000_ABS32 \.data\+0x0000000c
+0+c R_C6000_ABS32 \.data\+0x00000008
+0+10 R_C6000_ABS16 \.data\+0x0000000c
+0+12 R_C6000_ABS8 \.data\+0x00000008
+0+13 R_C6000_ABS8 \.data\+0x0000000c
+
+
+Contents of section \.data:
+[ \t]*0000 00000000 00000000 00000000 00000000 .*
+[ \t]*0010 00000000 .*
--- /dev/null
+#name: C6X data relocations, local symbols
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld
+#source: data-reloc-local-1.s
+#source: data-reloc-local-2.s
+#objdump: -r -s -j .data
+
+.*: *file format elf32-tic6x-le
+
+Contents of section \.data:
+[ \t]*0080 80000000 84000000 8c000000 88000000 .*
+[ \t]*0090 8c00888c .*
--- /dev/null
+SECTIONS
+{
+ . = 0x80;
+ .data : { *(.data*) }
+ . = 0x10000000;
+ .text : { *(.text*) }
+ /DISCARD/ : { *(*) }
+}
--- /dev/null
+#name: C6X MVK relocations, global symbols
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s0=0 --defsym s7fff=0x7fff --defsym s80000000=0x80000000 --defsym sffff8000=0xffff8000 --defsym sffffffff=0xffffffff
+#source: mvk-reloc-global.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+10000000 <[^>]*>:
+10000000:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+10000004:[ \t]+00c00068[ \t]+mvkh \.S1 2147483648,a1
+10000008:[ \t]+00ffffa8[ \t]+mvk \.S1 -1,a1
+1000000c:[ \t]+00ffffe8[ \t]+mvkh \.S1 4294901760,a1
+10000010:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+10000014:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+10000018:[ \t]+00ffff28[ \t]+mvk \.S1 -2,a1
+1000001c:[ \t]+00ffffe8[ \t]+mvkh \.S1 4294901760,a1
+10000020:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+10000024:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+10000028:[ \t]+00c00028[ \t]+mvk \.S1 -32768,a1
+1000002c:[ \t]+00c00028[ \t]+mvk \.S1 -32768,a1
+10000030:[ \t]+00bfffa8[ \t]+mvk \.S1 32767,a1
+[ \t]*\.\.\.
--- /dev/null
+.globl s0
+.globl s7fff
+.globl s80000000
+.globl sffff8000
+.globl sffffffff
+.text
+.nocmp
+ mvkl .S1 s80000000,a1
+ mvkh .S1 s80000000,a1
+ mvkl .S1 sffffffff,a1
+ mvkh .S1 sffffffff,a1
+ mvkl .S1 s0,a1
+ mvkh .S1 s0,a1
+ mvkl .S1 sffffffff+0xffffffff,a1
+ mvkh .S1 sffffffff+0xffffffff,a1
+ mvkl .S1 s80000000+0x80000000,a1
+ mvkh .S1 s80000000+0x80000000,a1
+ mvk .S1 sffff8000,a1
+ mvk .S1 s0-0x8000,a1
+ mvk .S1 s7fff,a1
--- /dev/null
+.text
+.nocmp
+ mvk .S1 a,a1
+ mvkl .S1 b,a2
+ mvkh .S1 c,a3
+.data
+a:
+ .word 0
+b:
+ .word 0
+c:
+ .word 0
--- /dev/null
+.text
+.nocmp
+ mvk .S1 d,a1
+ mvkl .S1 e,a2
+ mvkh .S1 f-0x100,a3
+.data
+d:
+ .word 0
+e:
+ .word 0
+f:
+ .word 0
--- /dev/null
+#name: C6X MVK relocations, local symbols, -r
+#as: -mlittle-endian
+#ld: -r -melf32_tic6x_le
+#source: mvk-reloc-local-1.s
+#source: mvk-reloc-local-2.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+0+ <[^>]*>:
+[ \t]*0:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*0: R_C6000_ABS_S16[ \t]+\.data
+[ \t]*4:[ \t]+01000028[ \t]+mvk \.S1 0,a2
+[ \t]*4: R_C6000_ABS_L16[ \t]+\.data\+0x4
+[ \t]*8:[ \t]+01800068[ \t]+mvkh \.S1 0,a3
+[ \t]*8: R_C6000_ABS_H16[ \t]+\.data\+0x8
+[ \t]*\.\.\.
+[ \t]*20:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*20: R_C6000_ABS_S16[ \t]+\.data\+0xc
+[ \t]*24:[ \t]+01000028[ \t]+mvk \.S1 0,a2
+[ \t]*24: R_C6000_ABS_L16[ \t]+\.data\+0x10
+[ \t]*28:[ \t]+01800068[ \t]+mvkh \.S1 0,a3
+[ \t]*28: R_C6000_ABS_H16[ \t]+\.data\+0xffffff14
+[ \t]*\.\.\.
--- /dev/null
+#name: C6X MVK relocations, local symbols
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld
+#source: mvk-reloc-local-1.s
+#source: mvk-reloc-local-2.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+10000000 <[^>]*>:
+10000000:[ \t]+00804028[ \t]+mvk \.S1 128,a1
+10000004:[ \t]+01004228[ \t]+mvk \.S1 132,a2
+10000008:[ \t]+01800068[ \t]+mvkh \.S1 0,a3
+[ \t]*\.\.\.
+10000020:[ \t]+00804628[ \t]+mvk \.S1 140,a1
+10000024:[ \t]+01004828[ \t]+mvk \.S1 144,a2
+10000028:[ \t]+01ffffe8[ \t]+mvkh \.S1 4294901760,a3
+[ \t]*\.\.\.
--- /dev/null
+#name: C6X PC-relative relocations, global symbols
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s7a=0x0fffff00 --defsym s7b=0x100000fc --defsym s10a=0x0ffff800 --defsym s10b=0x100007fc --defsym s12a=0x0fffe000 --defsym s12b=0x10001ffc --defsym s21a=0x0fc00000 --defsym s21b=0x103ffffc
+#source: pcrel-reloc-global.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+10000000 <[^>]*>:
+10000000:[ \t]+00c00162[ \t]+addkpc \.S2 fffff00 <[^>]*>,b1,0
+10000004:[ \t]+00bf0162[ \t]+addkpc \.S2 100000fc <[^>]*>,b1,0
+10000008:[ \t]+08000012[ \t]+b \.S2 fc00000 <[^>]*>
+1000000c:[ \t]+07ffff92[ \t]+b \.S2 103ffffc <[^>]*>
+10000010:[ \t]+00c01022[ \t]+bdec \.S2 ffff800 <[^>]*>,b1
+10000014:[ \t]+00bff022[ \t]+bdec \.S2 100007fc <[^>]*>,b1
+10000018:[ \t]+08000122[ \t]+bnop \.S2 fffe000 <[^>]*>,0
+1000001c:[ \t]+07ff0122[ \t]+bnop \.S2 10001ffc <[^>]*>,0
--- /dev/null
+.globl s7a
+.globl s7b
+.globl s21a
+.globl s21b
+.globl s10a
+.globl s10b
+.globl s12a
+.globl s12b
+.text
+.nocmp
+ addkpc .S2 s7a,b1,0
+ addkpc .S2 s7b,b1,0
+ b .S2 s21a
+ b .S2 s21b
+ bdec .S2 s10a,b1
+ bdec .S2 s10b,b1
+ bnop .S2 s12a,0
+ bnop .S2 s12b,0
--- /dev/null
+.text
+.nocmp
+ nop
+ addkpc .S2 f1,b1,0
+ addkpc .S2 f2,b1,0
+ b .S2 f1
+ b .S2 f2
+ bdec .S2 f1,b1
+ bdec .S2 f2,b1
+ bnop .S2 f1,0
+ bnop .S2 f2,0
+.section .text.1,"ax",@progbits
+f1:
+ nop
+f2:
+ nop
--- /dev/null
+.text
+.nocmp
+ nop
+ bnop .S2 f3,0
+ bnop .S2 f4,0
+ bdec .S2 f3,b1
+ bdec .S2 f4,b1
+ b .S2 f3
+ b .S2 f4
+ addkpc .S2 f3,b1,0
+ addkpc .S2 f4,b1,0
+.section .text.1,"ax",@progbits
+f3:
+ nop
+f4:
+ nop
--- /dev/null
+#name: C6X PC-relative relocations, local symbols, -r
+#as: -mlittle-endian
+#ld: -r -melf32_tic6x_le
+#source: pcrel-reloc-local-1.s
+#source: pcrel-reloc-local-2.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+0+ <[^>]*>:
+[ \t]*0:[ \t]+00000000[ \t]+nop 1
+[ \t]*4:[ \t]+00800162[ \t]+addkpc \.S2 0 <[^>]*>,b1,0
+[ \t]*4: R_C6000_PCR_S7[ \t]+\.text\.1
+[ \t]*8:[ \t]+00800162[ \t]+addkpc \.S2 0 <[^>]*>,b1,0
+[ \t]*8: R_C6000_PCR_S7[ \t]+\.text\.1\+0x4
+[ \t]*c:[ \t]+00000012[ \t]+b \.S2 0 <[^>]*>
+[ \t]*c: R_C6000_PCR_S21[ \t]+\.text\.1
+[ \t]*10:[ \t]+00000012[ \t]+b \.S2 0 <[^>]*>
+[ \t]*10: R_C6000_PCR_S21[ \t]+\.text\.1\+0x4
+[ \t]*14:[ \t]+00801022[ \t]+bdec \.S2 0 <[^>]*>,b1
+[ \t]*14: R_C6000_PCR_S10[ \t]+\.text\.1
+[ \t]*18:[ \t]+00801022[ \t]+bdec \.S2 0 <[^>]*>,b1
+[ \t]*18: R_C6000_PCR_S10[ \t]+\.text\.1\+0x4
+[ \t]*1c:[ \t]+00000122[ \t]+bnop \.S2 0 <[^>]*>,0
+[ \t]*1c: R_C6000_PCR_S12[ \t]+\.text\.1
+[ \t]*20:[ \t]+00000122[ \t]+bnop \.S2 20 <[^>]*>,0
+[ \t]*20: R_C6000_PCR_S12[ \t]+\.text\.1\+0x4
+[ \t]*\.\.\.
+[ \t]*44:[ \t]+00000122[ \t]+bnop \.S2 40 <[^>]*>,0
+[ \t]*44: R_C6000_PCR_S12[ \t]+\.text\.1\+0x20
+[ \t]*48:[ \t]+00000122[ \t]+bnop \.S2 40 <[^>]*>,0
+[ \t]*48: R_C6000_PCR_S12[ \t]+\.text\.1\+0x24
+[ \t]*4c:[ \t]+00801022[ \t]+bdec \.S2 40 <[^>]*>,b1
+[ \t]*4c: R_C6000_PCR_S10[ \t]+\.text\.1\+0x20
+[ \t]*50:[ \t]+00801022[ \t]+bdec \.S2 40 <[^>]*>,b1
+[ \t]*50: R_C6000_PCR_S10[ \t]+\.text\.1\+0x24
+[ \t]*54:[ \t]+00000012[ \t]+b \.S2 40 <[^>]*>
+[ \t]*54: R_C6000_PCR_S21[ \t]+\.text\.1\+0x20
+[ \t]*58:[ \t]+00000012[ \t]+b \.S2 40 <[^>]*>
+[ \t]*58: R_C6000_PCR_S21[ \t]+\.text\.1\+0x24
+[ \t]*5c:[ \t]+00800162[ \t]+addkpc \.S2 40 <[^>]*>,b1,0
+[ \t]*5c: R_C6000_PCR_S7[ \t]+\.text\.1\+0x20
+[ \t]*60:[ \t]+00800162[ \t]+addkpc \.S2 60 <[^>]*>,b1,0
+[ \t]*60: R_C6000_PCR_S7[ \t]+\.text\.1\+0x24
+[ \t]*\.\.\.
+
+Disassembly of section \.text\.1:
+
+0+ <[^>]*>:
+[ \t]*0:[ \t]+00000000[ \t]+nop 1
+
+0+4 <[^>]*>:
+[ \t]*\.\.\.
+
+0+20 <[^>]*>:
+[ \t]*20:[ \t]+00000000[ \t]+nop 1
+
+0+24 <[^>]*>:
+[ \t]*\.\.\.
--- /dev/null
+#name: C6X PC-relative relocations, local symbols
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld
+#source: pcrel-reloc-local-1.s
+#source: pcrel-reloc-local-2.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+10000000 <[^>]*>:
+10000000:[ \t]+00000000[ \t]+nop 1
+10000004:[ \t]+00900162[ \t]+addkpc \.S2 10000040 <[^>]*>,b1,0
+10000008:[ \t]+00910162[ \t]+addkpc \.S2 10000044 <[^>]*>,b1,0
+1000000c:[ \t]+00000812[ \t]+b \.S2 10000040 <[^>]*>
+10000010:[ \t]+00000892[ \t]+b \.S2 10000044 <[^>]*>
+10000014:[ \t]+00821022[ \t]+bdec \.S2 10000040 <[^>]*>,b1
+10000018:[ \t]+00823022[ \t]+bdec \.S2 10000044 <[^>]*>,b1
+1000001c:[ \t]+00100122[ \t]+bnop \.S2 10000040 <[^>]*>,0
+10000020:[ \t]+00090122[ \t]+bnop \.S2 10000044 <[^>]*>,0
+[ \t]*\.\.\.
+
+10000040 <[^>]*>:
+10000040:[ \t]+00000000[ \t]+nop 1
+
+10000044 <[^>]*>:
+[ \t]*\.\.\.
+10000064:[ \t]+00100122[ \t]+bnop \.S2 100000a0 <[^>]*>,0
+10000068:[ \t]+00110122[ \t]+bnop \.S2 100000a4 <[^>]*>,0
+1000006c:[ \t]+00821022[ \t]+bdec \.S2 100000a0 <[^>]*>,b1
+10000070:[ \t]+00823022[ \t]+bdec \.S2 100000a4 <[^>]*>,b1
+10000074:[ \t]+00000812[ \t]+b \.S2 100000a0 <[^>]*>
+10000078:[ \t]+00000892[ \t]+b \.S2 100000a4 <[^>]*>
+1000007c:[ \t]+00900162[ \t]+addkpc \.S2 100000a0 <[^>]*>,b1,0
+10000080:[ \t]+00890162[ \t]+addkpc \.S2 100000a4 <[^>]*>,b1,0
+[ \t]*\.\.\.
+
+100000a0 <[^>]*>:
+100000a0:[ \t]+00000000[ \t]+nop 1
+
+100000a4 <[^>]*>:
+[ \t]*\.\.\.
--- /dev/null
+#name: C6X relocation overflow, ABS_S16
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x8000
+#source: reloc-overflow-abs-s16.s
+#error: .*relocation truncated to fit: R_C6000_ABS_S16.*
--- /dev/null
+#name: C6X relocation underflow, ABS_S16
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0xffff7fff
+#source: reloc-overflow-abs-s16.s
+#error: .*relocation truncated to fit: R_C6000_ABS_S16.*
--- /dev/null
+.text
+.nocmp
+ mvk .S1 s,a1
--- /dev/null
+#name: C6X relocation overflow, ABS16
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x10000
+#source: reloc-overflow-abs16.s
+#error: .*relocation truncated to fit: R_C6000_ABS16.*
--- /dev/null
+#name: C6X relocation underflow, ABS16
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0xffff7fff
+#source: reloc-overflow-abs16.s
+#error: .*relocation truncated to fit: R_C6000_ABS16.*
--- /dev/null
+.globl s
+.data
+ .short s
--- /dev/null
+#name: C6X relocation overflow, ABS8
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x100
+#source: reloc-overflow-abs8.s
+#error: .*relocation truncated to fit: R_C6000_ABS8.*
--- /dev/null
+#name: C6X relocation underflow, ABS8
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0xffffff7f
+#source: reloc-overflow-abs8.s
+#error: .*relocation truncated to fit: R_C6000_ABS8.*
--- /dev/null
+.globl s
+.data
+ .byte s
--- /dev/null
+#name: C6X relocation overflow, PCR_S10
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x10000800
+#source: reloc-overflow-pcr-s10.s
+#error: .*relocation truncated to fit: R_C6000_PCR_S10.*
--- /dev/null
+#name: C6X relocation underflow, PCR_S10
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x0ffff7fc
+#source: reloc-overflow-pcr-s10.s
+#error: .*relocation truncated to fit: R_C6000_PCR_S10.*
--- /dev/null
+.text
+.nocmp
+ bdec .S2 s,b1
--- /dev/null
+#name: C6X relocation overflow, PCR_S12
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x10002000
+#source: reloc-overflow-pcr-s12.s
+#error: .*relocation truncated to fit: R_C6000_PCR_S12.*
--- /dev/null
+#name: C6X relocation underflow, PCR_S12
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x0fffdffc
+#source: reloc-overflow-pcr-s12.s
+#error: .*relocation truncated to fit: R_C6000_PCR_S12.*
--- /dev/null
+.text
+.nocmp
+ bnop .S2 s,0
--- /dev/null
+#name: C6X relocation overflow, PCR_S21
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x10400000
+#source: reloc-overflow-pcr-s21.s
+#error: .*relocation truncated to fit: R_C6000_PCR_S21.*
--- /dev/null
+#name: C6X relocation underflow, PCR_S21
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x0fbffffc
+#source: reloc-overflow-pcr-s21.s
+#error: .*relocation truncated to fit: R_C6000_PCR_S21.*
--- /dev/null
+.text
+.nocmp
+ b .S2 s
--- /dev/null
+#name: C6X relocation overflow, PCR_S7
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x10000100
+#source: reloc-overflow-pcr-s7.s
+#error: .*relocation truncated to fit: R_C6000_PCR_S7.*
--- /dev/null
+#name: C6X relocation underflow, PCR_S7
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s=0x0ffffefc
+#source: reloc-overflow-pcr-s7.s
+#error: .*relocation truncated to fit: R_C6000_PCR_S7.*
--- /dev/null
+.text
+.nocmp
+ addkpc .S2 s,b1,0
--- /dev/null
+#name: C6X relocation overflow, SBR_S16
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym s=0x8080
+#source: reloc-overflow-sbr-s16.s
+#error: .*relocation truncated to fit: R_C6000_SBR_S16.*
--- /dev/null
+#name: C6X relocation underflow, SBR_S16
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym s=0xffff807f
+#source: reloc-overflow-sbr-s16.s
+#error: .*relocation truncated to fit: R_C6000_SBR_S16.*
--- /dev/null
+.text
+.nocmp
+ mvk .S1 $dpr_byte(s),a1
--- /dev/null
+#name: C6X relocation overflow, SBR_U15_B
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym s=0x8080
+#source: reloc-overflow-sbr-u15-b.s
+#error: .*relocation truncated to fit: R_C6000_SBR_U15_B.*
--- /dev/null
+#name: C6X relocation underflow, SBR_U15_B
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym s=0x7f
+#source: reloc-overflow-sbr-u15-b.s
+#error: .*relocation truncated to fit: R_C6000_SBR_U15_B.*
--- /dev/null
+.text
+.nocmp
+ ldb .D2T2 *+b14(s),b1
--- /dev/null
+#name: C6X relocation overflow, SBR_U15_H
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym s=0x10080
+#source: reloc-overflow-sbr-u15-h.s
+#error: .*relocation truncated to fit: R_C6000_SBR_U15_H.*
--- /dev/null
+#name: C6X relocation underflow, SBR_U15_H
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym s=0x7e
+#source: reloc-overflow-sbr-u15-h.s
+#error: .*relocation truncated to fit: R_C6000_SBR_U15_H.*
--- /dev/null
+.text
+.nocmp
+ ldh .D2T2 *+b14(s),b1
--- /dev/null
+#name: C6X relocation overflow, SBR_U15_W
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym s=0x20080
+#source: reloc-overflow-sbr-u15-w.s
+#error: .*relocation truncated to fit: R_C6000_SBR_U15_W.*
--- /dev/null
+#name: C6X relocation underflow, SBR_U15_W
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym s=0x7c
+#source: reloc-overflow-sbr-u15-w.s
+#error: .*relocation truncated to fit: R_C6000_SBR_U15_W.*
--- /dev/null
+.text
+.nocmp
+ ldw .D2T2 *+b14(s),b1
--- /dev/null
+#name: C6X SB-relative relocations, global symbols
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld --defsym sw1=0x80 --defsym sw2=0x2007c --defsym sh1=0x80 --defsym sh2=0x1007e --defsym sb1=0x80 --defsym sb2=0x807f --defsym sb16a=0xffff8080 --defsym sb16b=0x807f --defsym sbw=0x123456f8 --defsym shw=0x2468ad70 --defsym sww=0x48d15a60
+#source: sbr-reloc-global.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+10000000 <[^>]*>:
+10000000:[ \t]+0080006e[ \t]+ldw \.D2T2 \*\+b14\(0\),b1
+10000004:[ \t]+00ffff6e[ \t]+ldw \.D2T2 \*\+b14\(131068\),b1
+10000008:[ \t]+0080004e[ \t]+ldh \.D2T2 \*\+b14\(0\),b1
+1000000c:[ \t]+00ffff4e[ \t]+ldh \.D2T2 \*\+b14\(65534\),b1
+10000010:[ \t]+0080002e[ \t]+ldb \.D2T2 \*\+b14\(0\),b1
+10000014:[ \t]+00ffff2e[ \t]+ldb \.D2T2 \*\+b14\(32767\),b1
+10000018:[ \t]+00c00028[ \t]+mvk \.S1 -32768,a1
+1000001c:[ \t]+00bfffa8[ \t]+mvk \.S1 32767,a1
+10000020:[ \t]+00ab3c28[ \t]+mvk \.S1 22136,a1
+10000024:[ \t]+00891a68[ \t]+mvkh \.S1 305397760,a1
+10000028:[ \t]+00ab3c28[ \t]+mvk \.S1 22136,a1
+1000002c:[ \t]+00891a68[ \t]+mvkh \.S1 305397760,a1
+10000030:[ \t]+00ab3c28[ \t]+mvk \.S1 22136,a1
+10000034:[ \t]+00891a68[ \t]+mvkh \.S1 305397760,a1
+[ \t]*\.\.\.
--- /dev/null
+.globl sw1
+.globl sw2
+.globl sh1
+.globl sh2
+.globl sb1
+.globl sb2
+.globl sb16a
+.globl sb16b
+.globl sbw
+.globl shw
+.globl sww
+.text
+.nocmp
+ ldw .D2T2 *+b14(sw1),b1
+ ldw .D2T2 *+b14(sw2),b1
+ ldh .D2T2 *+b14(sh1),b1
+ ldh .D2T2 *+b14(sh2),b1
+ ldb .D2T2 *+b14(sb1),b1
+ ldb .D2T2 *+b14(sb2),b1
+ mvk .S1 $dpr_byte(sb16a),a1
+ mvk .S1 $dpr_byte(sb16b),a1
+ mvkl .S1 $dpr_byte(sbw),a1
+ mvkh .S1 $dpr_byte(sbw),a1
+ mvkl .S1 $dpr_hword(shw),a1
+ mvkh .S1 $dpr_hword(shw),a1
+ mvkl .S1 $dpr_word(sww),a1
+ mvkh .S1 $dpr_word(sww),a1
--- /dev/null
+.text
+.nocmp
+ ldw .D2T2 *+b14(a),b1
+ ldw .D2T2 *+b14(b),b1
+ ldh .D2T2 *+b14(b),b1
+ ldh .D2T2 *+b14(c),b1
+ ldb .D2T2 *+b14(c),b1
+ ldb .D2T2 *+b14(d),b1
+ mvk .S1 $dpr_byte(d),a1
+ mvkl .S1 $dpr_byte(c),a1
+ mvkh .S1 $dpr_byte(d),a1
+ mvkl .S1 $dpr_hword(b),a1
+ mvkh .S1 $dpr_hword(c),a1
+ mvkl .S1 $dpr_word(a),a1
+ mvkh .S1 $dpr_word(b),a1
+.data
+a:
+ .word 0
+b:
+ .short 0
+c:
+ .byte 0
+d:
+ .byte 0
--- /dev/null
+.text
+.nocmp
+ ldw .D2T2 *+b14(e),b1
+ ldw .D2T2 *+b14(f),b1
+ ldh .D2T2 *+b14(f),b1
+ ldh .D2T2 *+b14(g),b1
+ ldb .D2T2 *+b14(g),b1
+ ldb .D2T2 *+b14(h),b1
+ mvk .S1 $dpr_byte(h),a1
+ mvkl .S1 $dpr_byte(g),a1
+ mvkh .S1 $dpr_byte(h),a1
+ mvkl .S1 $dpr_hword(f),a1
+ mvkh .S1 $dpr_hword(g),a1
+ mvkl .S1 $dpr_word(e),a1
+ mvkh .S1 $dpr_word(f),a1
+.data
+e:
+ .word 0
+f:
+ .short 0
+g:
+ .byte 0
+h:
+ .byte 0
--- /dev/null
+#name: C6X SB-relative relocations, local symbols, -r
+#as: -mlittle-endian
+#ld: -r -melf32_tic6x_le
+#source: sbr-reloc-local-1.s
+#source: sbr-reloc-local-2.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+0+ <[^>]*>:
+[ \t]*0:[ \t]+0080006e[ \t]+ldw \.D2T2 \*\+b14\(0\),b1
+[ \t]*0: R_C6000_SBR_U15_W[ \t]+\.data
+[ \t]*4:[ \t]+0080006e[ \t]+ldw \.D2T2 \*\+b14\(0\),b1
+[ \t]*4: R_C6000_SBR_U15_W[ \t]+\.data\+0x4
+[ \t]*8:[ \t]+0080004e[ \t]+ldh \.D2T2 \*\+b14\(0\),b1
+[ \t]*8: R_C6000_SBR_U15_H[ \t]+\.data\+0x4
+[ \t]*c:[ \t]+0080004e[ \t]+ldh \.D2T2 \*\+b14\(0\),b1
+[ \t]*c: R_C6000_SBR_U15_H[ \t]+\.data\+0x6
+[ \t]*10:[ \t]+0080002e[ \t]+ldb \.D2T2 \*\+b14\(0\),b1
+[ \t]*10: R_C6000_SBR_U15_B[ \t]+\.data\+0x6
+[ \t]*14:[ \t]+0080002e[ \t]+ldb \.D2T2 \*\+b14\(0\),b1
+[ \t]*14: R_C6000_SBR_U15_B[ \t]+\.data\+0x7
+[ \t]*18:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*18: R_C6000_SBR_S16[ \t]+\.data\+0x7
+[ \t]*1c:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*1c: R_C6000_SBR_L16_B[ \t]+\.data\+0x6
+[ \t]*20:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*20: R_C6000_SBR_H16_B[ \t]+\.data\+0x7
+[ \t]*24:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*24: R_C6000_SBR_L16_H[ \t]+\.data\+0x4
+[ \t]*28:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*28: R_C6000_SBR_H16_H[ \t]+\.data\+0x6
+[ \t]*2c:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*2c: R_C6000_SBR_L16_W[ \t]+\.data
+[ \t]*30:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*30: R_C6000_SBR_H16_W[ \t]+\.data\+0x4
+[ \t]*\.\.\.
+[ \t]*40:[ \t]+0080006e[ \t]+ldw \.D2T2 \*\+b14\(0\),b1
+[ \t]*40: R_C6000_SBR_U15_W[ \t]+\.data\+0x8
+[ \t]*44:[ \t]+0080006e[ \t]+ldw \.D2T2 \*\+b14\(0\),b1
+[ \t]*44: R_C6000_SBR_U15_W[ \t]+\.data\+0xc
+[ \t]*48:[ \t]+0080004e[ \t]+ldh \.D2T2 \*\+b14\(0\),b1
+[ \t]*48: R_C6000_SBR_U15_H[ \t]+\.data\+0xc
+[ \t]*4c:[ \t]+0080004e[ \t]+ldh \.D2T2 \*\+b14\(0\),b1
+[ \t]*4c: R_C6000_SBR_U15_H[ \t]+\.data\+0xe
+[ \t]*50:[ \t]+0080002e[ \t]+ldb \.D2T2 \*\+b14\(0\),b1
+[ \t]*50: R_C6000_SBR_U15_B[ \t]+\.data\+0xe
+[ \t]*54:[ \t]+0080002e[ \t]+ldb \.D2T2 \*\+b14\(0\),b1
+[ \t]*54: R_C6000_SBR_U15_B[ \t]+\.data\+0xf
+[ \t]*58:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*58: R_C6000_SBR_S16[ \t]+\.data\+0xf
+[ \t]*5c:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*5c: R_C6000_SBR_L16_B[ \t]+\.data\+0xe
+[ \t]*60:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*60: R_C6000_SBR_H16_B[ \t]+\.data\+0xf
+[ \t]*64:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*64: R_C6000_SBR_L16_H[ \t]+\.data\+0xc
+[ \t]*68:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*68: R_C6000_SBR_H16_H[ \t]+\.data\+0xe
+[ \t]*6c:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+[ \t]*6c: R_C6000_SBR_L16_W[ \t]+\.data\+0x8
+[ \t]*70:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*70: R_C6000_SBR_H16_W[ \t]+\.data\+0xc
+[ \t]*\.\.\.
--- /dev/null
+#name: C6X SB-relative relocations, local symbols
+#as: -mlittle-endian
+#ld: -melf32_tic6x_le -Tsbr.ld
+#source: sbr-reloc-local-1.s
+#source: sbr-reloc-local-2.s
+#objdump: -dr
+
+.*: *file format elf32-tic6x-le
+
+
+Disassembly of section \.text:
+
+10000000 <[^>]*>:
+10000000:[ \t]+0080006e[ \t]+ldw \.D2T2 \*\+b14\(0\),b1
+10000004:[ \t]+0080016e[ \t]+ldw \.D2T2 \*\+b14\(4\),b1
+10000008:[ \t]+0080024e[ \t]+ldh \.D2T2 \*\+b14\(4\),b1
+1000000c:[ \t]+0080034e[ \t]+ldh \.D2T2 \*\+b14\(6\),b1
+10000010:[ \t]+0080062e[ \t]+ldb \.D2T2 \*\+b14\(6\),b1
+10000014:[ \t]+0080072e[ \t]+ldb \.D2T2 \*\+b14\(7\),b1
+10000018:[ \t]+008003a8[ \t]+mvk \.S1 7,a1
+1000001c:[ \t]+00800328[ \t]+mvk \.S1 6,a1
+10000020:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+10000024:[ \t]+00800128[ \t]+mvk \.S1 2,a1
+10000028:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+1000002c:[ \t]+00800028[ \t]+mvk \.S1 0,a1
+10000030:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*\.\.\.
+10000040:[ \t]+0080026e[ \t]+ldw \.D2T2 \*\+b14\(8\),b1
+10000044:[ \t]+0080036e[ \t]+ldw \.D2T2 \*\+b14\(12\),b1
+10000048:[ \t]+0080064e[ \t]+ldh \.D2T2 \*\+b14\(12\),b1
+1000004c:[ \t]+0080074e[ \t]+ldh \.D2T2 \*\+b14\(14\),b1
+10000050:[ \t]+00800e2e[ \t]+ldb \.D2T2 \*\+b14\(14\),b1
+10000054:[ \t]+00800f2e[ \t]+ldb \.D2T2 \*\+b14\(15\),b1
+10000058:[ \t]+008007a8[ \t]+mvk \.S1 15,a1
+1000005c:[ \t]+00800728[ \t]+mvk \.S1 14,a1
+10000060:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+10000064:[ \t]+00800328[ \t]+mvk \.S1 6,a1
+10000068:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+1000006c:[ \t]+00800128[ \t]+mvk \.S1 2,a1
+10000070:[ \t]+00800068[ \t]+mvkh \.S1 0,a1
+[ \t]*\.\.\.
--- /dev/null
+EXTERN (__c6xabi_DSBT_BASE);
+SECTIONS
+{
+ . = 0x80;
+ .data : { PROVIDE_HIDDEN (__c6xabi_DSBT_BASE = .); *(.data*) }
+ . = 0x10000000;
+ .text : { *(.text*) }
+ /DISCARD/ : { *(*) }
+}
--- /dev/null
+if { [istarget tic6x-*-*] } {
+ foreach test [lsort [glob -nocomplain $srcdir/$subdir/*.d]] {
+ if { [runtest_file_p $runtests $test] } {
+ run_dump_test [file rootname $test]
+ }
+ }
+}
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
+ * Makefile.in: Regenerate.
+ * configure.in (bfd_tic6x_arch): New.
+ * configure: Regenerate.
+ * disassemble.c (ARCH_tic6x): Define if ARCH_all.
+ (disassembler): Handle TI C6X.
+ * tic6x-dis.c: New.
+
2010-03-24 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
tic4x-dis.c \
tic54x-dis.c \
tic54x-opc.c \
+ tic6x-dis.c \
tic80-dis.c \
tic80-opc.c \
v850-dis.c \
tic4x-dis.c \
tic54x-dis.c \
tic54x-opc.c \
+ tic6x-dis.c \
tic80-dis.c \
tic80-opc.c \
v850-dis.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic4x-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic54x-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic54x-opc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic6x-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic80-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic80-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v850-dis.Plo@am__quote@
bfd_tic30_arch) ta="$ta tic30-dis.lo" ;;
bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;;
bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;;
+ bfd_tic6x_arch) ta="$ta tic6x-dis.lo" ;;
bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;;
bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;;
bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;;
bfd_tic30_arch) ta="$ta tic30-dis.lo" ;;
bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;;
bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;;
+ bfd_tic6x_arch) ta="$ta tic6x-dis.lo" ;;
bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;;
bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;;
bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;;
/* Select disassembly routine for specified architecture.
Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
- 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+ 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
#define ARCH_tic30
#define ARCH_tic4x
#define ARCH_tic54x
+#define ARCH_tic6x
#define ARCH_tic80
#define ARCH_v850
#define ARCH_vax
disassemble = print_insn_tic54x;
break;
#endif
+#ifdef ARCH_tic6x
+ case bfd_arch_tic6x:
+ disassemble = print_insn_tic6x;
+ break;
+#endif
#ifdef ARCH_tic80
case bfd_arch_tic80:
disassemble = print_insn_tic80;
--- /dev/null
+/* TI C6X disassembler.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "dis-asm.h"
+#include "opcode/tic6x.h"
+#include "libiberty.h"
+
+/* Define the instruction format table. */
+const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max] =
+ {
+#define FMT(name, num_bits, cst_bits, mask, fields) \
+ { num_bits, cst_bits, mask, fields },
+#include "opcode/tic6x-insn-formats.h"
+#undef FMT
+ };
+
+/* Define the control register table. */
+const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max] =
+ {
+#define CTRL(name, isa, rw, crlo, crhi_mask) \
+ { \
+ STRINGX(name), \
+ CONCAT2(TIC6X_INSN_,isa), \
+ CONCAT2(tic6x_rw_,rw), \
+ crlo, \
+ crhi_mask \
+ },
+#include "opcode/tic6x-control-registers.h"
+#undef CTRL
+ };
+
+/* Define the opcode table. */
+const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max] =
+ {
+#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \
+ { \
+ STRINGX(name), \
+ CONCAT2(tic6x_func_unit_,func_unit), \
+ CONCAT4(tic6x_insn_format_,func_unit,_,format), \
+ CONCAT2(tic6x_pipeline_,type), \
+ CONCAT2(TIC6X_INSN_,isa), \
+ flags, \
+ fixed, \
+ ops, \
+ var \
+ },
+#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
+ { \
+ STRINGX(name), \
+ CONCAT2(tic6x_func_unit_,func_unit), \
+ CONCAT4(tic6x_insn_format_,func_unit,_,format), \
+ CONCAT2(tic6x_pipeline_,type), \
+ CONCAT2(TIC6X_INSN_,isa), \
+ flags, \
+ fixed, \
+ ops, \
+ var \
+ },
+#include "opcode/tic6x-opcode-table.h"
+#undef INSN
+#undef INSNE
+ };
+
+/* If instruction format FMT has a field FIELD, return a pointer to
+ the description of that field; otherwise return NULL. */
+
+const tic6x_insn_field *
+tic6x_field_from_fmt (const tic6x_insn_format *fmt, tic6x_insn_field_id field)
+{
+ unsigned int f;
+
+ for (f = 0; f < fmt->num_fields; f++)
+ if (fmt->fields[f].field_id == field)
+ return &fmt->fields[f];
+
+ return NULL;
+}
+
+/* Extract the bits corresponding to FIELD from OPCODE. */
+
+static unsigned int
+tic6x_field_bits (unsigned int opcode, const tic6x_insn_field *field)
+{
+ return (opcode >> field->low_pos) & ((1u << field->width) - 1);
+}
+
+/* Extract a 32-bit value read from the instruction stream. */
+
+static unsigned int
+tic6x_extract_32 (unsigned char *p, struct disassemble_info *info)
+{
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ return (p[0]) | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
+ else
+ return (p[3]) | (p[2] << 8) | (p[1] << 16) | (p[0] << 24);
+}
+
+/* Extract a 16-bit value read from the instruction stream. */
+
+static unsigned int
+tic6x_extract_16 (unsigned char *p, struct disassemble_info *info)
+{
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ return (p[0]) | (p[1] << 8);
+ else
+ return (p[1]) | (p[0] << 8);
+}
+
+/* FP points to a fetch packet. Return whether it is header-based; if
+ it is, fill in HEADER. */
+
+static bfd_boolean
+tic6x_check_fetch_packet_header (unsigned char *fp,
+ tic6x_fetch_packet_header *header,
+ struct disassemble_info *info)
+{
+ int i;
+
+ header->header = tic6x_extract_32 (fp + 28, info);
+ if ((header->header & 0xf0000000) != 0xe0000000)
+ return FALSE;
+
+ for (i = 0; i < 7; i++)
+ header->word_compact[i]
+ = (header->header & (1u << (21 + i))) ? TRUE : FALSE;
+
+ header->prot = (header->header & (1u << 20)) ? TRUE : FALSE;
+ header->rs = (header->header & (1u << 19)) ? TRUE : FALSE;
+ header->dsz = (header->header >> 16) & 0x7;
+ header->br = (header->header & (1u << 15)) ? TRUE : FALSE;
+ header->sat = (header->header & (1u << 14)) ? TRUE : FALSE;
+
+ for (i = 0; i < 14; i++)
+ header->p_bits[i]
+ = (header->header & (1u << i)) ? TRUE : FALSE;
+
+ return TRUE;
+}
+
+/* Disassemble the instruction at ADDR and print it using
+ INFO->FPRINTF_FUNC and INFO->STREAM, returning the number of bytes
+ consumed. */
+
+int
+print_insn_tic6x (bfd_vma addr, struct disassemble_info *info)
+{
+ int status;
+ bfd_vma fp_addr;
+ bfd_vma fp_offset;
+ unsigned char fp[32];
+ unsigned int opcode;
+ tic6x_opcode_id opcode_id;
+ bfd_boolean fetch_packet_header_based;
+ tic6x_fetch_packet_header header;
+ unsigned int num_bits;
+ bfd_boolean bad_offset = FALSE;
+
+ fp_offset = addr & 0x1f;
+ fp_addr = addr - fp_offset;
+ status = info->read_memory_func (fp_addr, fp, 32, info);
+ if (status)
+ {
+ info->memory_error_func (status, addr, info);
+ return -1;
+ }
+
+ fetch_packet_header_based
+ = tic6x_check_fetch_packet_header (fp, &header, info);
+ if (fetch_packet_header_based)
+ {
+ if (fp_offset & 0x1)
+ bad_offset = TRUE;
+ if ((fp_offset & 0x3) && (fp_offset >= 28
+ || !header.word_compact[fp_offset >> 2]))
+ bad_offset = TRUE;
+ if (fp_offset == 28)
+ {
+ info->bytes_per_chunk = 4;
+ info->fprintf_func (info->stream, "<fetch packet header 0x%.8x>",
+ header.header);
+ return 4;
+ }
+ num_bits = (header.word_compact[fp_offset >> 2] ? 16 : 32);
+ }
+ else
+ {
+ num_bits = 32;
+ if (fp_offset & 0x3)
+ bad_offset = TRUE;
+ }
+
+ if (bad_offset)
+ {
+ info->bytes_per_chunk = 1;
+ info->fprintf_func (info->stream, ".byte 0x%.2x", fp[fp_offset]);
+ return 1;
+ }
+
+ if (num_bits == 16)
+ {
+ /* The least-significant part of a 32-bit word comes logically
+ before the most-significant part. For big-endian, follow the
+ TI assembler in showing instructions in logical order by
+ pretending that the two halves of the word are in opposite
+ locations to where they actually are. */
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ opcode = tic6x_extract_16 (fp + fp_offset, info);
+ else
+ opcode = tic6x_extract_16 (fp + (fp_offset ^ 2), info);
+ }
+ else
+ opcode = tic6x_extract_32 (fp + fp_offset, info);
+
+ for (opcode_id = 0; opcode_id < tic6x_opcode_max; opcode_id++)
+ {
+ const tic6x_opcode *const opc = &tic6x_opcode_table[opcode_id];
+ const tic6x_insn_format *const fmt
+ = &tic6x_insn_format_table[opc->format];
+ const tic6x_insn_field *creg_field;
+ bfd_boolean p_bit;
+ const char *parallel;
+ const char *cond = "";
+ const char *func_unit;
+ char func_unit_buf[7];
+ unsigned int func_unit_side = 0;
+ unsigned int func_unit_data_side = 0;
+ unsigned int func_unit_cross = 0;
+ /* The maximum length of the text of a non-PC-relative operand
+ is 24 bytes (SPMASK masking all eight functional units, with
+ separating commas and trailing NUL). */
+ char operands[TIC6X_MAX_OPERANDS][24] = { { 0 } };
+ bfd_vma operands_addresses[TIC6X_MAX_OPERANDS] = { 0 };
+ bfd_boolean operands_text[TIC6X_MAX_OPERANDS] = { FALSE };
+ bfd_boolean operands_pcrel[TIC6X_MAX_OPERANDS] = { FALSE };
+ unsigned int fix;
+ unsigned int num_operands;
+ unsigned int op_num;
+ bfd_boolean fixed_ok;
+ bfd_boolean operands_ok;
+
+ if (opc->flags & TIC6X_FLAG_MACRO)
+ continue;
+ if (fmt->num_bits != num_bits)
+ continue;
+ if ((opcode & fmt->mask) != fmt->cst_bits)
+ continue;
+
+ /* If the format has a creg field, it is only a candidate for a
+ match if the creg and z fields have values indicating a valid
+ condition; reserved values indicate either an instruction
+ format without a creg field, or an invalid instruction. */
+ creg_field = tic6x_field_from_fmt (fmt, tic6x_field_creg);
+ if (creg_field)
+ {
+ const tic6x_insn_field *z_field;
+ unsigned int creg_value, z_value;
+ static const char *const conds[8][2] =
+ {
+ { "", NULL },
+ { "[b0] ", "[!b0] " },
+ { "[b1] ", "[!b1] " },
+ { "[b2] ", "[!b2] " },
+ { "[a1] ", "[!a1] " },
+ { "[a2] ", "[!a2] " },
+ { "[a0] ", "[!a0] " },
+ { NULL, NULL }
+ };
+
+ /* A creg field is not meaningful without a z field, so if
+ the z field is not present this is an error in the format
+ table. */
+ z_field = tic6x_field_from_fmt (fmt, tic6x_field_z);
+ if (!z_field)
+ abort ();
+
+ creg_value = tic6x_field_bits (opcode, creg_field);
+ z_value = tic6x_field_bits (opcode, z_field);
+ cond = conds[creg_value][z_value];
+ if (cond == NULL)
+ continue;
+ }
+
+ /* All fixed fields must have matching values; all fields with
+ restricted ranges must have values within those ranges. */
+ fixed_ok = TRUE;
+ for (fix = 0; fix < opc->num_fixed_fields; fix++)
+ {
+ unsigned int field_bits;
+ const tic6x_insn_field *const field
+ = tic6x_field_from_fmt (fmt, opc->fixed_fields[fix].field_id);
+
+ if (!field)
+ abort ();
+ field_bits = tic6x_field_bits (opcode, field);
+ if (field_bits < opc->fixed_fields[fix].min_val
+ || field_bits > opc->fixed_fields[fix].max_val)
+ {
+ fixed_ok = FALSE;
+ break;
+ }
+ }
+ if (!fixed_ok)
+ continue;
+
+ /* The instruction matches. */
+
+ /* The p-bit indicates whether this instruction is in parallel
+ with the *next* instruction, whereas the parallel bars
+ indicate the instruction is in parallel with the *previous*
+ instruction. Thus, we must find the p-bit for the previous
+ instruction. */
+ if (num_bits == 16 && (fp_offset & 0x2) == 2)
+ {
+ /* This is the logically second (most significant; second in
+ fp_offset terms because fp_offset relates to logical not
+ physical addresses) instruction of a compact pair; find
+ the p-bit for the first (least significant). */
+ p_bit = header.p_bits[(fp_offset >> 2) << 1];
+ }
+ else if (fp_offset >= 4)
+ {
+ /* Find the last instruction of the previous word in this
+ fetch packet. For compact instructions, this is the most
+ significant 16 bits. */
+ if (fetch_packet_header_based
+ && header.word_compact[(fp_offset >> 2) - 1])
+ p_bit = header.p_bits[(fp_offset >> 1) - 1];
+ else
+ {
+ unsigned int prev_opcode
+ = tic6x_extract_32 (fp + (fp_offset & 0x1c) - 4, info);
+ p_bit = (prev_opcode & 0x1) ? TRUE : FALSE;
+ }
+ }
+ else
+ {
+ /* Find the last instruction of the previous fetch
+ packet. */
+ unsigned char fp_prev[32];
+ status = info->read_memory_func (fp_addr - 32, fp_prev, 32, info);
+ if (status)
+ /* No previous instruction to be parallel with. */
+ p_bit = FALSE;
+ else
+ {
+ bfd_boolean prev_header_based;
+ tic6x_fetch_packet_header prev_header;
+
+ prev_header_based
+ = tic6x_check_fetch_packet_header (fp_prev, &prev_header, info);
+ if (prev_header_based && prev_header.word_compact[6])
+ p_bit = prev_header.p_bits[13];
+ else
+ {
+ unsigned int prev_opcode = tic6x_extract_32 (fp_prev + 28,
+ info);
+ p_bit = (prev_opcode & 0x1) ? TRUE : FALSE;
+ }
+ }
+ }
+ parallel = p_bit ? "|| " : "";
+
+ if (opc->func_unit == tic6x_func_unit_nfu)
+ func_unit = "";
+ else
+ {
+ unsigned int fld_num;
+ char func_unit_char;
+ const char *data_str;
+ bfd_boolean have_areg = FALSE;
+ bfd_boolean have_cross = FALSE;
+
+ func_unit_side = (opc->flags & TIC6X_FLAG_SIDE_B_ONLY) ? 2 : 0;
+ func_unit_cross = 0;
+ func_unit_data_side = (opc->flags & TIC6X_FLAG_SIDE_T2_ONLY) ? 2 : 0;
+
+ for (fld_num = 0; fld_num < opc->num_variable_fields; fld_num++)
+ {
+ const tic6x_coding_field *const enc = &opc->variable_fields[fld_num];
+ const tic6x_insn_field *field;
+ unsigned int fld_val;
+
+ field = tic6x_field_from_fmt (fmt, enc->field_id);
+ if (!field)
+ abort ();
+ fld_val = tic6x_field_bits (opcode, field);
+ switch (enc->coding_method)
+ {
+ case tic6x_coding_fu:
+ /* The side must be specified exactly once. */
+ if (func_unit_side)
+ abort ();
+ func_unit_side = (fld_val ? 2 : 1);
+ break;
+
+ case tic6x_coding_data_fu:
+ /* The data side must be specified exactly once. */
+ if (func_unit_data_side)
+ abort ();
+ func_unit_data_side = (fld_val ? 2 : 1);
+ break;
+
+ case tic6x_coding_xpath:
+ /* Cross path use must be specified exactly
+ once. */
+ if (have_cross)
+ abort ();
+ have_cross = TRUE;
+ func_unit_cross = fld_val;
+ break;
+
+ case tic6x_coding_areg:
+ have_areg = TRUE;
+ break;
+
+ default:
+ /* Don't relate to functional units. */
+ break;
+ }
+ }
+
+ /* The side of the functional unit used must now have been
+ determined either from the flags or from an instruction
+ field. */
+ if (func_unit_side != 1 && func_unit_side != 2)
+ abort ();
+
+ /* Cross paths are not applicable when sides are specified
+ for both address and data paths. */
+ if (func_unit_data_side && have_cross)
+ abort ();
+
+ /* Separate address and data paths are only applicable for
+ the D unit. */
+ if (func_unit_data_side && opc->func_unit != tic6x_func_unit_d)
+ abort ();
+
+ /* If an address register is being used but in ADDA rather
+ than a load or store, it uses a cross path for side-A
+ instructions, and the cross path use is not specified by
+ an instruction field. */
+ if (have_areg && !func_unit_data_side)
+ {
+ if (have_cross)
+ abort ();
+ func_unit_cross = (func_unit_side == 1 ? TRUE : FALSE);
+ }
+
+ switch (opc->func_unit)
+ {
+ case tic6x_func_unit_d:
+ func_unit_char = 'D';
+ break;
+
+ case tic6x_func_unit_l:
+ func_unit_char = 'L';
+ break;
+
+ case tic6x_func_unit_m:
+ func_unit_char = 'M';
+ break;
+
+ case tic6x_func_unit_s:
+ func_unit_char = 'S';
+ break;
+
+ default:
+ abort ();
+ }
+
+ switch (func_unit_data_side)
+ {
+ case 0:
+ data_str = "";
+ break;
+
+ case 1:
+ data_str = "T1";
+ break;
+
+ case 2:
+ data_str = "T2";
+ break;
+
+ default:
+ abort ();
+ }
+
+ snprintf (func_unit_buf, 7, " .%c%u%s%s", func_unit_char,
+ func_unit_side, (func_unit_cross ? "X" : ""), data_str);
+ func_unit = func_unit_buf;
+ }
+
+ /* For each operand there must be one or more fields set based
+ on that operand, that can together be used to derive the
+ operand value. */
+ operands_ok = TRUE;
+ num_operands = opc->num_operands;
+ for (op_num = 0; op_num < num_operands; op_num++)
+ {
+ unsigned int fld_num;
+ unsigned int mem_base_reg = 0;
+ bfd_boolean mem_base_reg_known = FALSE;
+ bfd_boolean mem_base_reg_known_long = FALSE;
+ unsigned int mem_offset = 0;
+ bfd_boolean mem_offset_known = FALSE;
+ bfd_boolean mem_offset_known_long = FALSE;
+ unsigned int mem_mode = 0;
+ bfd_boolean mem_mode_known = FALSE;
+ unsigned int mem_scaled = 0;
+ bfd_boolean mem_scaled_known = FALSE;
+ unsigned int crlo = 0;
+ bfd_boolean crlo_known = FALSE;
+ unsigned int crhi = 0;
+ bfd_boolean crhi_known = FALSE;
+ bfd_boolean spmask_skip_operand = FALSE;
+ unsigned int fcyc_bits = 0;
+ bfd_boolean prev_sploop_found = FALSE;
+
+ switch (opc->operand_info[op_num].form)
+ {
+ case tic6x_operand_retreg:
+ /* Fully determined by the functional unit. */
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%c3",
+ (func_unit_side == 2 ? 'b' : 'a'));
+ continue;
+
+ case tic6x_operand_irp:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "irp");
+ continue;
+
+ case tic6x_operand_nrp:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "nrp");
+ continue;
+
+ default:
+ break;
+ }
+
+ for (fld_num = 0; fld_num < opc->num_variable_fields; fld_num++)
+ {
+ const tic6x_coding_field *const enc
+ = &opc->variable_fields[fld_num];
+ const tic6x_insn_field *field;
+ unsigned int fld_val;
+ signed int signed_fld_val;
+
+ if (enc->operand_num != op_num)
+ continue;
+ field = tic6x_field_from_fmt (fmt, enc->field_id);
+ if (!field)
+ abort ();
+ fld_val = tic6x_field_bits (opcode, field);
+ switch (enc->coding_method)
+ {
+ case tic6x_coding_ucst:
+ case tic6x_coding_ulcst_dpr_byte:
+ case tic6x_coding_ulcst_dpr_half:
+ case tic6x_coding_ulcst_dpr_word:
+ case tic6x_coding_lcst_low16:
+ switch (opc->operand_info[op_num].form)
+ {
+ case tic6x_operand_asm_const:
+ case tic6x_operand_link_const:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%u", fld_val);
+ break;
+
+ case tic6x_operand_mem_long:
+ mem_offset = fld_val;
+ mem_offset_known_long = TRUE;
+ break;
+
+ default:
+ abort ();
+ }
+ break;
+
+ case tic6x_coding_lcst_high16:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%u", fld_val << 16);
+ break;
+
+ case tic6x_coding_scst:
+ operands_text[op_num] = TRUE;
+ signed_fld_val = (signed int) fld_val;
+ signed_fld_val ^= (1 << (field->width - 1));
+ signed_fld_val -= (1 << (field->width - 1));
+ snprintf (operands[op_num], 24, "%d", signed_fld_val);
+ break;
+
+ case tic6x_coding_ucst_minus_one:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%u", fld_val + 1);
+ break;
+
+ case tic6x_coding_pcrel:
+ case tic6x_coding_pcrel_half:
+ signed_fld_val = (signed int) fld_val;
+ signed_fld_val ^= (1 << (field->width - 1));
+ signed_fld_val -= (1 << (field->width - 1));
+ if (fetch_packet_header_based
+ && enc->coding_method == tic6x_coding_pcrel_half)
+ signed_fld_val *= 2;
+ else
+ signed_fld_val *= 4;
+ operands_pcrel[op_num] = TRUE;
+ operands_addresses[op_num] = fp_addr + signed_fld_val;
+ break;
+
+ case tic6x_coding_reg_shift:
+ fld_val <<= 1;
+ /* Fall through. */
+ case tic6x_coding_reg:
+ switch (opc->operand_info[op_num].form)
+ {
+ case tic6x_operand_reg:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%c%u",
+ (func_unit_side == 2 ? 'b' : 'a'), fld_val);
+ break;
+
+ case tic6x_operand_xreg:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%c%u",
+ (((func_unit_side == 2) ^ func_unit_cross)
+ ? 'b'
+ : 'a'), fld_val);
+ break;
+
+ case tic6x_operand_dreg:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%c%u",
+ (func_unit_data_side == 2 ? 'b' : 'a'),
+ fld_val);
+ break;
+
+ case tic6x_operand_regpair:
+ operands_text[op_num] = TRUE;
+ if (fld_val & 1)
+ operands_ok = FALSE;
+ snprintf (operands[op_num], 24, "%c%u:%c%u",
+ (func_unit_side == 2 ? 'b' : 'a'), fld_val + 1,
+ (func_unit_side == 2 ? 'b' : 'a'), fld_val);
+ break;
+
+ case tic6x_operand_xregpair:
+ operands_text[op_num] = TRUE;
+ if (fld_val & 1)
+ operands_ok = FALSE;
+ snprintf (operands[op_num], 24, "%c%u:%c%u",
+ (((func_unit_side == 2) ^ func_unit_cross)
+ ? 'b'
+ : 'a'), fld_val + 1,
+ (((func_unit_side == 2) ^ func_unit_cross)
+ ? 'b'
+ : 'a'), fld_val);
+ break;
+
+ case tic6x_operand_dregpair:
+ operands_text[op_num] = TRUE;
+ if (fld_val & 1)
+ operands_ok = FALSE;
+ snprintf (operands[op_num], 24, "%c%u:%c%u",
+ (func_unit_data_side == 2 ? 'b' : 'a'),
+ fld_val + 1,
+ (func_unit_data_side == 2 ? 'b' : 'a'),
+ fld_val);
+ break;
+
+ case tic6x_operand_mem_deref:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "*%c%u",
+ (func_unit_side == 2 ? 'b' : 'a'), fld_val);
+ break;
+
+ case tic6x_operand_mem_short:
+ case tic6x_operand_mem_ndw:
+ mem_base_reg = fld_val;
+ mem_base_reg_known = TRUE;
+ break;
+
+ default:
+ abort ();
+ }
+ break;
+
+ case tic6x_coding_areg:
+ switch (opc->operand_info[op_num].form)
+ {
+ case tic6x_operand_areg:
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "b%u",
+ fld_val ? 15u : 14u);
+ break;
+
+ case tic6x_operand_mem_long:
+ mem_base_reg = fld_val ? 15u : 14u;
+ mem_base_reg_known_long = TRUE;
+ break;
+
+ default:
+ abort ();
+ }
+ break;
+
+ case tic6x_coding_mem_offset:
+ case tic6x_coding_mem_offset_noscale:
+ mem_offset = fld_val;
+ mem_offset_known = TRUE;
+ break;
+
+ case tic6x_coding_mem_mode:
+ mem_mode = fld_val;
+ mem_mode_known = TRUE;
+ break;
+
+ case tic6x_coding_scaled:
+ mem_scaled = fld_val;
+ mem_scaled_known = TRUE;
+ break;
+
+ case tic6x_coding_crlo:
+ crlo = fld_val;
+ crlo_known = TRUE;
+ break;
+
+ case tic6x_coding_crhi:
+ crhi = fld_val;
+ crhi_known = TRUE;
+ break;
+
+ case tic6x_coding_fstg:
+ case tic6x_coding_fcyc:
+ if (!prev_sploop_found)
+ {
+ bfd_vma search_fp_addr = fp_addr;
+ bfd_vma search_fp_offset = fp_offset;
+ bfd_boolean search_fp_header_based
+ = fetch_packet_header_based;
+ tic6x_fetch_packet_header search_fp_header = header;
+ unsigned char search_fp[32];
+ unsigned int search_num_bits;
+ unsigned int search_opcode;
+ unsigned int sploop_ii = 0;
+ int i;
+
+ memcpy (search_fp, fp, 32);
+
+ /* To interpret these bits in an SPKERNEL
+ instruction, we must find the previous
+ SPLOOP-family instruction. It may come up to
+ 48 execute packets earlier. */
+ for (i = 0; i < 48 * 8; i++)
+ {
+ /* Find the previous instruction. */
+ if (search_fp_offset & 2)
+ search_fp_offset -= 2;
+ else if (search_fp_offset >= 4)
+ {
+ if (search_fp_header_based
+ && (search_fp_header.word_compact
+ [(search_fp_offset >> 2) - 1]))
+ search_fp_offset -= 2;
+ else
+ search_fp_offset -= 4;
+ }
+ else
+ {
+ search_fp_addr -= 32;
+ status = info->read_memory_func (search_fp_addr,
+ search_fp,
+ 32, info);
+ if (status)
+ /* No previous SPLOOP instruction. */
+ break;
+ search_fp_header_based
+ = (tic6x_check_fetch_packet_header
+ (search_fp, &search_fp_header, info));
+ if (search_fp_header_based)
+ search_fp_offset
+ = search_fp_header.word_compact[6] ? 26 : 24;
+ else
+ search_fp_offset = 28;
+ }
+
+ /* Extract the previous instruction. */
+ if (search_fp_header_based)
+ search_num_bits
+ = (search_fp_header.word_compact[search_fp_offset
+ >> 2]
+ ? 16
+ : 32);
+ else
+ search_num_bits = 32;
+ if (search_num_bits == 16)
+ {
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ search_opcode
+ = (tic6x_extract_16
+ (search_fp + search_fp_offset, info));
+ else
+ search_opcode
+ = (tic6x_extract_16
+ (search_fp + (search_fp_offset ^ 2),
+ info));
+ }
+ else
+ search_opcode
+ = tic6x_extract_32 (search_fp + search_fp_offset,
+ info);
+
+ /* Check whether it is an SPLOOP-family
+ instruction. */
+ if (search_num_bits == 32
+ && ((search_opcode & 0x003ffffe) == 0x00038000
+ || (search_opcode & 0x003ffffe) == 0x0003a000
+ || ((search_opcode & 0x003ffffe)
+ == 0x0003e000)))
+ {
+ prev_sploop_found = TRUE;
+ sploop_ii = ((search_opcode >> 23) & 0x1f) + 1;
+ }
+ else if (search_num_bits == 16
+ && (search_opcode & 0x3c7e) == 0x0c66)
+ {
+ prev_sploop_found = TRUE;
+ sploop_ii
+ = (((search_opcode >> 7) & 0x7)
+ | ((search_opcode >> 11) & 0x8)) + 1;
+ }
+ if (prev_sploop_found)
+ {
+ if (sploop_ii <= 0)
+ abort ();
+ else if (sploop_ii <= 1)
+ fcyc_bits = 0;
+ else if (sploop_ii <= 2)
+ fcyc_bits = 1;
+ else if (sploop_ii <= 4)
+ fcyc_bits = 2;
+ else if (sploop_ii <= 8)
+ fcyc_bits = 3;
+ else if (sploop_ii <= 14)
+ fcyc_bits = 4;
+ else
+ prev_sploop_found = FALSE;
+ }
+ if (prev_sploop_found)
+ break;
+ }
+ }
+ if (!prev_sploop_found)
+ {
+ operands_ok = FALSE;
+ operands_text[op_num] = TRUE;
+ break;
+ }
+ if (fcyc_bits > field->width)
+ abort ();
+ if (enc->coding_method == tic6x_coding_fstg)
+ {
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%u",
+ fld_val >> fcyc_bits);
+ }
+ else
+ {
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%u",
+ fld_val & ((1 << fcyc_bits) - 1));
+ }
+ break;
+
+ case tic6x_coding_spmask:
+ if (fld_val == 0)
+ spmask_skip_operand = TRUE;
+ else
+ {
+ char *p;
+ unsigned int i;
+
+ operands_text[op_num] = TRUE;
+ p = operands[op_num];
+ for (i = 0; i < 8; i++)
+ if (fld_val & (1 << i))
+ {
+ *p++ = "LSDM"[i/2];
+ *p++ = '1' + (i & 1);
+ *p++ = ',';
+ }
+ p[-1] = 0;
+ }
+ break;
+
+ case tic6x_coding_fu:
+ case tic6x_coding_data_fu:
+ case tic6x_coding_xpath:
+ /* Don't relate to operands, so operand number is
+ meaningless. */
+ break;
+
+ default:
+ abort ();
+ }
+
+ if (mem_base_reg_known_long && mem_offset_known_long)
+ {
+ if (operands_text[op_num] || operands_pcrel[op_num])
+ abort ();
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "*+b%u(%u)", mem_base_reg,
+ mem_offset * opc->operand_info[op_num].size);
+ }
+
+ if (mem_base_reg_known && mem_offset_known && mem_mode_known
+ && (mem_scaled_known
+ || (opc->operand_info[op_num].form
+ != tic6x_operand_mem_ndw)))
+ {
+ char side;
+ char base[4];
+ bfd_boolean offset_is_reg;
+ bfd_boolean offset_scaled;
+ char offset[4];
+ char offsetp[6];
+
+ if (operands_text[op_num] || operands_pcrel[op_num])
+ abort ();
+
+ side = func_unit_side == 2 ? 'b' : 'a';
+ snprintf (base, 4, "%c%u", side, mem_base_reg);
+
+ offset_is_reg = ((mem_mode & 4) ? TRUE : FALSE);
+ if (offset_is_reg)
+ {
+ snprintf (offset, 4, "%c%u", side, mem_offset);
+ if (opc->operand_info[op_num].form
+ == tic6x_operand_mem_ndw)
+ offset_scaled = mem_scaled ? TRUE : FALSE;
+ else
+ offset_scaled = TRUE;
+ }
+ else
+ {
+ if (opc->operand_info[op_num].form
+ == tic6x_operand_mem_ndw)
+ {
+ offset_scaled = mem_scaled ? TRUE : FALSE;
+ snprintf (offset, 4, "%u", mem_offset);
+ }
+ else
+ {
+ offset_scaled = FALSE;
+ snprintf (offset, 4, "%u",
+ (mem_offset
+ * opc->operand_info[op_num].size));
+ }
+ }
+
+ if (offset_scaled)
+ snprintf (offsetp, 6, "[%s]", offset);
+ else
+ snprintf (offsetp, 6, "(%s)", offset);
+
+ operands_text[op_num] = TRUE;
+ switch (mem_mode & ~4u)
+ {
+ case 0:
+ snprintf (operands[op_num], 24, "*-%s%s", base, offsetp);
+ break;
+
+ case 1:
+ snprintf (operands[op_num], 24, "*+%s%s", base, offsetp);
+ break;
+
+ case 2:
+ case 3:
+ operands_ok = FALSE;
+ break;
+
+ case 8:
+ snprintf (operands[op_num], 24, "*--%s%s", base,
+ offsetp);
+ break;
+
+ case 9:
+ snprintf (operands[op_num], 24, "*++%s%s", base,
+ offsetp);
+ break;
+
+ case 10:
+ snprintf (operands[op_num], 24, "*%s--%s", base,
+ offsetp);
+ break;
+
+ case 11:
+ snprintf (operands[op_num], 24, "*%s++%s", base,
+ offsetp);
+ break;
+
+ default:
+ abort ();
+ }
+ }
+
+ if (crlo_known && crhi_known)
+ {
+ tic6x_rw rw;
+ tic6x_ctrl_id crid;
+
+ if (operands_text[op_num] || operands_pcrel[op_num])
+ abort ();
+
+ rw = opc->operand_info[op_num].rw;
+ if (rw != tic6x_rw_read
+ && rw != tic6x_rw_write)
+ abort ();
+
+ for (crid = 0; crid < tic6x_ctrl_max; crid++)
+ {
+ if (crlo == tic6x_ctrl_table[crid].crlo
+ && (crhi & tic6x_ctrl_table[crid].crhi_mask) == 0
+ && (rw == tic6x_rw_read
+ ? (tic6x_ctrl_table[crid].rw == tic6x_rw_read
+ || (tic6x_ctrl_table[crid].rw
+ == tic6x_rw_read_write))
+ : (tic6x_ctrl_table[crid].rw == tic6x_rw_write
+ || (tic6x_ctrl_table[crid].rw
+ == tic6x_rw_read_write))))
+ break;
+ }
+ if (crid == tic6x_ctrl_max)
+ {
+ operands_text[op_num] = TRUE;
+ operands_ok = FALSE;
+ }
+ else
+ {
+ operands_text[op_num] = TRUE;
+ snprintf (operands[op_num], 24, "%s",
+ tic6x_ctrl_table[crid].name);
+ }
+ }
+
+ if (operands_text[op_num] || operands_pcrel[op_num]
+ || spmask_skip_operand)
+ break;
+ }
+ if (spmask_skip_operand)
+ {
+ /* SPMASK operands are only valid as the single operand
+ in the opcode table. */
+ if (num_operands != 1)
+ abort ();
+ num_operands = 0;
+ break;
+ }
+ /* The operand must by now have been decoded. */
+ if (!operands_text[op_num] && !operands_pcrel[op_num])
+ abort ();
+ }
+
+ if (!operands_ok)
+ continue;
+
+ info->bytes_per_chunk = num_bits / 8;
+ info->fprintf_func (info->stream, "%s%s%s%s", parallel, cond,
+ opc->name, func_unit);
+ for (op_num = 0; op_num < num_operands; op_num++)
+ {
+ info->fprintf_func (info->stream, "%c", (op_num == 0 ? ' ' : ','));
+ if (operands_pcrel[op_num])
+ info->print_address_func (operands_addresses[op_num], info);
+ else
+ info->fprintf_func (info->stream, "%s", operands[op_num]);
+ }
+ if (fetch_packet_header_based && header.prot)
+ info->fprintf_func (info->stream, " || nop 5");
+
+ return num_bits / 8;
+ }
+
+ info->bytes_per_chunk = num_bits / 8;
+ info->fprintf_func (info->stream, "<undefined instruction 0x%.*x>",
+ (int) num_bits / 4, opcode);
+ return num_bits / 8;
+}
projects / binutils-gdb.git / commitdiff