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[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A
authorRamana Radhakrishnan <ramana.radhakrishnan@arm.com>
Tue, 4 Jul 2017 15:18:47 +0000 (16:18 +0100)
committerRamana Radhakrishnan <ramana.radhakrishnan@arm.com>
Tue, 4 Jul 2017 15:18:47 +0000 (16:18 +0100)
This patch adds support mvfr2 control registers for armv8-a as
this was missed from the original port to armv8-a (documented
at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered
by an internal user of the GNU toolchain.

I'd like to backport this to the binutils 2.28 and binutils 2.29
release branch if possible (with suitable testing and basically
checking removing the armv8-r parts).

Tristan - are you ok with the backports ?

Applied to trunk.

regards Ramana

2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        * gas/config/tc-arm.c (arm_regs): Add MVFR2.
        (do_vmrs): Constraint for MVFR2 and armv8.
        (do_vmsr): Likewise.
        * gas/testsuite/gas/arm/armv8-a+fp.d: Update.
        * gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise.
        * gas/testsuite/gas/arm/armv8-r+fp.d: Likewise.
        * gas/testsuite/gas/arm/vfp-bad.s: Likewise.
        * gas/testsuite/gas/arm/vfp-bad.l: Likewise.
        * opcodes/arm-dis.c: Support MVFR2 in disassembly
        with vmrs and vmsr.

gas/config/tc-arm.c patch | blob | history
gas/testsuite/gas/arm/armv8-a+fp.d patch | blob | history
gas/testsuite/gas/arm/armv8-ar+fp.s patch | blob | history
gas/testsuite/gas/arm/armv8-r+fp.d patch | blob | history
gas/testsuite/gas/arm/vfp-bad.l patch | blob | history
gas/testsuite/gas/arm/vfp-bad.s patch | blob | history
opcodes/arm-dis.c patch | blob | history

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index f1d8fd09d9007f9dc9bf8ed42e921d4817ae82f2..e22ffe676f36912afd40f6ffa46cb4159ed91386 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -9142,6 +9142,11 @@ do_vmrs (void)
       return;
     }
 
+  /* MVFR2 is only valid at ARMv8-A.  */
+  if (inst.operands[1].reg == 5)
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+               _(BAD_FPU));
+
   /* APSR_ sets isvec. All other refs to PC are illegal.  */
   if (!inst.operands[0].isvec && Rt == REG_PC)
     {
@@ -9168,6 +9173,11 @@ do_vmsr (void)
       return;
     }
 
+  /* MVFR2 is only valid for ARMv8-A.  */
+  if (inst.operands[0].reg == 5)
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+               _(BAD_FPU));
+
   /* If we get through parsing the register name, we just insert the number
      generated into the instruction without further validation.  */
   inst.instruction |= (inst.operands[0].reg << 16);
@@ -18910,6 +18920,7 @@ static const struct reg_entry reg_names[] =
   REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
   REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
   REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
+  REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
 
   /* Maverick DSP coprocessor registers.  */
   REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index 1b6c7434d5d4e95f035a33366de8e8ba986be4c8..3e71624244b3ab93a22965101d4d0f8ff666faf7 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -115,3 +115,7 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> eef2 0b60   vcvtb.f64.f16   d16, s1
 0[0-9a-f]+ <[^>]+> eeb2 fbcf   vcvtt.f64.f16   d15, s30
 0[0-9a-f]+ <[^>]+> eef2 fb6f   vcvtb.f64.f16   d31, s31
+0[0-9a-f]+ <[^>]+> eef5 9a10   vmrs    r9, mvfr2
+0[0-9a-f]+ <[^>]+> eee5 7a10   vmsr    mvfr2, r7
+0[0-9a-f]+ <[^>]+> eef5 4a10   vmrs    r4, mvfr2
+0[0-9a-f]+ <[^>]+> eee5 5a10   vmsr    mvfr2, r5
\ No newline at end of file
diff --git a/gas/testsuite/gas/arm/armv8-ar+fp.s b/gas/testsuite/gas/arm/armv8-ar+fp.s
index a3b21c7f647a2e5b7f9b724fa58f8d17bc208970..92d3813c315d3648e0fcf387c4b3b2467fdc1d52 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-ar+fp.s
+++ b/gas/testsuite/gas/arm/armv8-ar+fp.s
@@ -113,3 +113,8 @@
        vcvtb.f64.f16   d16, s1
        vcvtt.f64.f16   d15, s30
        vcvtb.f64.f16   d31, s31
+       vmrs            r9, MVFR2
+       vmsr            MVFR2, r7
+       vmrs            r4, mvfr2
+       vmsr            mvfr2, r5
+
diff --git a/gas/testsuite/gas/arm/armv8-r+fp.d b/gas/testsuite/gas/arm/armv8-r+fp.d
index 34cfd34e1559088bfe6ac204174318a343994e0f..52fdbec4c6436ac9f67f9491f22df39ef9e6ade4 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-r+fp.d
+++ b/gas/testsuite/gas/arm/armv8-r+fp.d
@@ -115,3 +115,7 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> eef2 0b60   vcvtb.f64.f16   d16, s1
 0[0-9a-f]+ <[^>]+> eeb2 fbcf   vcvtt.f64.f16   d15, s30
 0[0-9a-f]+ <[^>]+> eef2 fb6f   vcvtb.f64.f16   d31, s31
+0[0-9a-f]+ <[^>]+> eef5 9a10   vmrs    r9, mvfr2
+0[0-9a-f]+ <[^>]+> eee5 7a10   vmsr    mvfr2, r7
+0[0-9a-f]+ <[^>]+> eef5 4a10   vmrs    r4, mvfr2
+0[0-9a-f]+ <[^>]+> eee5 5a10   vmsr    mvfr2, r5
\ No newline at end of file
diff --git a/gas/testsuite/gas/arm/vfp-bad.l b/gas/testsuite/gas/arm/vfp-bad.l
index 7726e63180b15acd9282852169272b6d02eb948b..a1479f484fefe9ee3f33b3635e8954e3cc5437cd 100644 (file)
--- a/gas/testsuite/gas/arm/vfp-bad.l
+++ b/gas/testsuite/gas/arm/vfp-bad.l
@@ -7,3 +7,5 @@
 [^:]*:9: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!'
 [^:]*:10: Error: instruction does not support writeback -- `flds s0,\[r0\],#8'
 [^:]*:11: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!'
+[^:]*:12: Error: selected FPU does not support instruction -- `vmrs r0,MVFR2'
+[^:]*:13: Error: selected FPU does not support instruction -- `vmsr MVFR2,r2'
diff --git a/gas/testsuite/gas/arm/vfp-bad.s b/gas/testsuite/gas/arm/vfp-bad.s
index ac44371773f16f54beabdfd3ac8f5e0f0008589b..1a446fee936be3cca99b6c28dc20928ef72a1bb1 100644 (file)
--- a/gas/testsuite/gas/arm/vfp-bad.s
+++ b/gas/testsuite/gas/arm/vfp-bad.s
@@ -9,3 +9,5 @@ entry:
        fldd    d0, [r0, #-8]!
        flds    s0, [r0], #8
        flds    s0, [r0, #-8]!
+       vmrs    r0, MVFR2
+       vmsr    MVFR2, r2
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 582383440192a1cd38bd4c508703b4ccc38df7c4..25000046d9fa5b2e4d20133c51eb22c998e0d60a 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -503,6 +503,8 @@ static const struct opcode32 coprocessor_opcodes[] =
     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
+  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+    0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
@@ -515,6 +517,8 @@ static const struct opcode32 coprocessor_opcodes[] =
     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
+  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+    0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),