ctr mode not needed, just use unconditional CTR dec

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py
index cfaa35344b8b75d7183d369d986a815754e53442..5e1f1a1d5d21ffa320896765aa7ee72145baf00f 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py
@@ -247,7 +247,7 @@ class DecoderTestCase(FHDLTestCase):
             [
             "setvl 1, 0, %d, 0, 1, 1" % maxvl, # VL (and r1) = MIN(CTR,MAXVL=4)
             "add 2, 2, 1",            # for fun accumulate r1 (VL) into r2
-            "sv.bc/ctr/all 16, *0, -0x8", # branch, test CTR, reducing by VL
+            "sv.bc/all 16, *0, -0x8", # branch, test CTR, reducing by VL
             ]
             )
         lst = list(lst)