platforms/kc705: use XC3SProg

diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py
index b749acb9ee986e0212b064d7791b6dcbb1ebb337..4bfc13a82d6559770bee0be7d29be4ca0b170c35 100644 (file)
--- a/mibuild/platforms/kc705.py
+++ b/mibuild/platforms/kc705.py
@@ -3,6 +3,7 @@ from mibuild.crg import SimpleCRG
 from mibuild.xilinx_common import CRG_DS
 from mibuild.xilinx_ise import XilinxISEPlatform
 from mibuild.xilinx_vivado import XilinxVivadoPlatform
+from mibuild.programmer import XC3SProg
 
 _io = [
        ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
@@ -129,6 +130,9 @@ def Platform(*args, toolchain="vivado", **kwargs):
                def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
                        xilinx_platform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory)
 
+               def create_programmer(self):
+                       return XC3SProg("jtaghs1", "bscan_spi_kc705.bit")
+
                def do_finalize(self, fragment):
                        try:
                                self.add_period_constraint(self.lookup_request("clk156").p, 6.4)