+2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (parse_real_register): Return AVX register
+ only if AVX is enabled.
+
2008-04-07 Kaz Kojima <kkojima@rr.iij4u.or.jp>
PR gas/6043
if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
return (const reg_entry *) NULL;
+ if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
+ return (const reg_entry *) NULL;
+
/* Don't allow fake index register unless allow_index_reg isn't 0. */
if (!allow_index_reg
&& (r->reg_num == RegEiz || r->reg_num == RegRiz))
+2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/att-regs.s: Add AVX register test.
+ * gas/i386/intel-regs.s: Likewise.
+
+ * gas/i386/att-regs.d: Updated.
+ * gas/i386/intel-regs.d: Likewise.
+
2008-04-07 Kaz Kojima <kkojima@rr.iij4u.or.jp>
PR gas/6043
.*:[ ]+dd c0[ ]+ffree[ ]+%st(\(0\))?
.*:[ ]+0f ef c0[ ]+pxor[ ]+%mm0,%mm0
.*:[ ]+0f 57 c0[ ]+xorps[ ]+%xmm0,%xmm0
+.*:[ ]+c5 fc 57 c0[ ]+vxorps[ ]+%ymm0,%ymm0,%ymm0
.*:[ ]+44[ ]+inc %esp
.*:[ ]+88 c0[ ]+mov[ ]+%al,%al
.*:[ ]+66 44[ ]+inc[ ]+%sp
.arch .sse
xorps xmm0, xmm0
+ .arch .avx
+ vxorps ymm0, ymm0, ymm0
+
.arch generic64
.code64
mov r8b, axl
.*:[ ]+dd c0[ ]+ffree[ ]+%st(\(0\))?
.*:[ ]+0f ef c0[ ]+pxor[ ]+%mm0,%mm0
.*:[ ]+0f 57 c0[ ]+xorps[ ]+%xmm0,%xmm0
+.*:[ ]+c5 fc 57 c0[ ]+vxorps[ ]+%ymm0,%ymm0,%ymm0
.*:[ ]+44[ ]+inc %esp
.*:[ ]+88 c0[ ]+mov[ ]+%al,%al
.*:[ ]+66 44[ ]+inc[ ]+%sp
.arch .sse
xorps xmm0, xmm0
+ .arch .avx
+ vxorps ymm0, ymm0, ymm0
+
.arch generic64
.code64
mov axl, r8b