targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 91206fa2927872ddbfed418a167d86ca5b3d1d4d..5830f35e895baf6769bd2e6450ff374f4b77c1dd 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -8,6 +8,8 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.io import DDROutput
+
 from litex.boards.platforms import de0nano
 
 from litex.soc.cores.clock import CycloneIVPLL
@@ -38,7 +40,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
 
         # SDRAM clock
-        self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
+        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
 
 # BaseSoC ------------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 408ed442c0063f1c5dc6595e6c47f6d01c680491..638d28d18ba12fcc359016121a5646204043f0bf 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -12,6 +12,7 @@ from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.build.io import DDROutput
+
 from litex.boards.platforms import minispartan6
 
 from litex.soc.cores.clock import *
@@ -37,7 +38,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90)
 
         # SDRAM clock
-        self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys_ps"))
+        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
@@ -53,7 +54,7 @@ class BaseSoC(SoCCore):
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cmd_latency=2)
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
             self.add_sdram("sdram",
                 phy                     = self.sdrphy,
                 module                  = AS4C16M16(sys_clk_freq, "1:1"),

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 98a5f30a2e2c64aedb0842d08cafa1683fcf4748..e42c92b02624b73bff8a33b7593a467b64ac3f5c 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -10,6 +10,8 @@ import sys
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.io import DDROutput
+
 from litex.boards.platforms import ulx3s
 
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
@@ -45,7 +47,7 @@ class _CRG(Module):
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
 
         # SDRAM clock
-        self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
+        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
 
         # Prevent ESP32 from resetting FPGA
         self.comb += platform.request("wifi_gpio0").eq(1)