LiteEthMini is a subset of LiteEth intended to be used with a CPU and a software stack.
+++ /dev/null
-Unless otherwise noted, LiteEth is copyright (C) 2015 Florent Kermarrec.
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
-Other authors retain ownership of their contributions. If a submission can
-reasonably be considered independently copyrightable, it's yours and we
-encourage you to claim it with appropriate copyright notices. This submission
-then falls under the "otherwise noted" category. All submissions are strongly
-encouraged to use the two-clause BSD license reproduced above.
+++ /dev/null
- __ _ __ ______ __
- / / (_) /____ / __/ /_/ /
- / /__/ / __/ -_) _// __/ _ \
- /____/_/\__/\__/___/\__/_//_/
-
- Copyright 2012-2015 / EnjoyDigital / M-Labs Ltd
-
- A small footprint and configurable Ethernet core
- with UDP/IP hw stack and Etherbone frontend
- powered by Migen
-
-[> Doc
----------
-HTML : www.enjoy-digital.fr/liteeth/
-PDF : www.enjoy-digital.fr/liteeth.pdf
-
-[> Intro
----------
-LiteEth provides a small footprint and configurable Ethernet core.
-
-LiteEth is part of MiSoC libraries whose aims are to lower entry level of
-complex FPGA cores by providing simple, elegant and efficient implementations
-ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
-
-The core uses simple and specific streaming buses and will provides in the future
-adapters to use standardized AXI or Avalon-ST streaming buses.
-
-Since Python is used to describe the HDL, the core is highly and easily
-configurable.
-
-LiteEth uses technologies developed in partnership with M-Labs Ltd:
- - Migen enables generating HDL with Python in an efficient way.
- - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
-
-LiteEth can be used as MiSoC library or can be integrated with your standard
-design flow by generating the verilog rtl that you will use as a standard core.
-
-[> Features
------------
-- Ethernet MAC with various interfaces and various PHYs (GMII, MII, Loopback)
-- Hardware UDP/IP stack with ARP and ICMP
-
-[> Possible improvements
--------------------------
-- add standardized interfaces (AXI, Avalon-ST)
-- add DMA interface to MAC
-- add RGMII/SGMII PHYs
-- ... See below Support and consulting :)
-
-If you want to support these features, please contact us at florent [AT]
-enjoy-digital.fr. You can also contact our partner on the public mailing list
-devel [AT] lists.m-labs.hk.
-
-
-[> Getting started
-------------------
-1. Install Python3 and your vendor's software
-
-2. Obtain Migen and install it:
- git clone https://github.com/m-labs/migen
- cd migen
- python3 setup.py install
- cd ..
-
-3. Obtain MiSoC:
- git clone https://github.com/m-labs/misoc --recursive
-
-4. Build and load UDP loopback design (only for KC705 for now):
- go to misoclib/com/liteeth/example_designs/
- run ./make.py -t udp all load-bitstream
-
-5. Test design (only for KC705 for now):
- try to ping 192.168.0.42
- go to [..]/example_designs/test/
- run ./make.py test_udp
-
-6. Build and load Etherbone design (only for KC705 for now):
- python3 make.py -t etherbone all load-bitstream
-
-7. Test design (only for KC705 for now):
- try to ping 192.168.0.42
- go to [..]/example_designs/test/
- run ./make.py test_etherbone
-
-[> Simulations:
- Simulations are available in misoclib/com/liteeth/test/:
- - mac_core_tb
- - mac_wishbone_tb
- - arp_tb
- - ip_tb
- - icmp_tb
- - udp_tb
- All ethernet layers have their own model tested against real ethernet dumps (dumps.py)
- To run a simulation, move to misoclib/com/liteeth/test/ and run:
- make simulation_name
-
-[> Tests :
- An Etherbone example with Wishbone SRAM and an UDP loopback example are provided.
- Please goto to Getting Started section to see how to run the tests.
-
-[> License
------------
-LiteEth is released under the very permissive two-clause BSD license. Under
-the terms of this license, you are authorized to use LiteEth for closed-source
-proprietary designs.
-Even though we do not require you to do so, those things are awesome, so please
-do them if possible:
- - tell us that you are using LiteEth
- - cite LiteEth in publications related to research it has helped
- - send us feedback and suggestions for improvements
- - send us bug reports when something goes wrong
- - send us the modifications and improvements you have done to LiteEth.
-
-[> Support and consulting
---------------------------
-We love open-source hardware and like sharing our designs with others.
-
-LiteEth is mainly developed and maintained by EnjoyDigital.
-
-If you would like to know more about LiteEth or if you are already a happy
-user and would like to extend it for your needs, EnjoyDigital can provide standard
-commercial support as well as consulting services.
-
-So feel free to contact us, we'd love to work with you! (and eventually shorten
-the list of the possible improvements :)
-
-[> Contact
-E-mail: florent [AT] enjoy-digital.fr
\ No newline at end of file
+++ /dev/null
-import math
-from collections import OrderedDict
-
-from migen.fhdl.std import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.record import *
-from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, WaitTimer
-from migen.flow.actor import *
-from migen.actorlib.structuring import Converter, Pipeline
-from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
-from migen.actorlib.packet import *
-from migen.bank.description import *
-
-class Port:
- def connect(self, port):
- r = [
- Record.connect(self.source, port.sink),
- Record.connect(port.source, self.sink)
- ]
- return r
-
-eth_mtu = 1532
-eth_min_len = 46
-eth_interpacket_gap = 12
-eth_preamble = 0xD555555555555555
-buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
-
-ethernet_type_ip = 0x800
-ethernet_type_arp = 0x806
-
-mac_header_length = 14
-mac_header_fields = {
- "target_mac": HeaderField(0, 0, 48),
- "sender_mac": HeaderField(6, 0, 48),
- "ethernet_type": HeaderField(12, 0, 16)
-}
-mac_header = Header(mac_header_fields,
- mac_header_length,
- swap_field_bytes=True)
-
-arp_hwtype_ethernet = 0x0001
-arp_proto_ip = 0x0800
-arp_opcode_request = 0x0001
-arp_opcode_reply = 0x0002
-
-arp_header_length = 28
-arp_header_fields = {
- "hwtype": HeaderField(0, 0, 16),
- "proto": HeaderField(2, 0, 16),
- "hwsize": HeaderField(4, 0, 8),
- "protosize": HeaderField(5, 0, 8),
- "opcode": HeaderField(6, 0, 16),
- "sender_mac": HeaderField(8, 0, 48),
- "sender_ip": HeaderField(14, 0, 32),
- "target_mac": HeaderField(18, 0, 48),
- "target_ip": HeaderField(24, 0, 32)
-}
-arp_header = Header(arp_header_fields,
- arp_header_length,
- swap_field_bytes=True)
-
-
-ipv4_header_length = 20
-ipv4_header_fields = {
- "ihl": HeaderField(0, 0, 4),
- "version": HeaderField(0, 4, 4),
- "total_length": HeaderField(2, 0, 16),
- "identification": HeaderField(4, 0, 16),
- "ttl": HeaderField(8, 0, 8),
- "protocol": HeaderField(9, 0, 8),
- "checksum": HeaderField(10, 0, 16),
- "sender_ip": HeaderField(12, 0, 32),
- "target_ip": HeaderField(16, 0, 32)
-}
-ipv4_header = Header(ipv4_header_fields,
- ipv4_header_length,
- swap_field_bytes=True)
-
-icmp_protocol = 0x01
-
-icmp_header_length = 8
-icmp_header_fields = {
- "msgtype": HeaderField(0, 0, 8),
- "code": HeaderField(1, 0, 8),
- "checksum": HeaderField(2, 0, 16),
- "quench": HeaderField(4, 0, 32)
-}
-icmp_header = Header(icmp_header_fields,
- icmp_header_length,
- swap_field_bytes=True)
-
-udp_protocol = 0x11
-
-udp_header_length = 8
-udp_header_fields = {
- "src_port": HeaderField(0, 0, 16),
- "dst_port": HeaderField(2, 0, 16),
- "length": HeaderField(4, 0, 16),
- "checksum": HeaderField(6, 0, 16)
-}
-udp_header = Header(udp_header_fields,
- udp_header_length,
- swap_field_bytes=True)
-
-
-etherbone_magic = 0x4e6f
-etherbone_version = 1
-etherbone_packet_header_length = 8
-etherbone_packet_header_fields = {
- "magic": HeaderField(0, 0, 16),
-
- "version": HeaderField(2, 4, 4),
- "nr": HeaderField(2, 2, 1),
- "pr": HeaderField(2, 1, 1),
- "pf": HeaderField(2, 0, 1),
-
- "addr_size": HeaderField(3, 4, 4),
- "port_size": HeaderField(3, 0, 4)
-}
-etherbone_packet_header = Header(etherbone_packet_header_fields,
- etherbone_packet_header_length,
- swap_field_bytes=True)
-
-etherbone_record_header_length = 4
-etherbone_record_header_fields = {
- "bca": HeaderField(0, 0, 1),
- "rca": HeaderField(0, 1, 1),
- "rff": HeaderField(0, 2, 1),
- "cyc": HeaderField(0, 4, 1),
- "wca": HeaderField(0, 5, 1),
- "wff": HeaderField(0, 6, 1),
-
- "byte_enable": HeaderField(1, 0, 8),
-
- "wcount": HeaderField(2, 0, 8),
-
- "rcount": HeaderField(3, 0, 8)
-}
-etherbone_record_header = Header(etherbone_record_header_fields,
- etherbone_record_header_length,
- swap_field_bytes=True)
-
-
-# layouts
-def _remove_from_layout(layout, *args):
- r = []
- for f in layout:
- remove = False
- for arg in args:
- if f[0] == arg:
- remove = True
- if not remove:
- r.append(f)
- return r
-
-
-def eth_phy_description(dw):
- payload_layout = [
- ("data", dw),
- ("last_be", dw//8),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, packetized=True)
-
-
-def eth_mac_description(dw):
- payload_layout = mac_header.get_layout() + [
- ("data", dw),
- ("last_be", dw//8),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, packetized=True)
-
-
-def eth_arp_description(dw):
- param_layout = arp_header.get_layout()
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-arp_table_request_layout = [
- ("ip_address", 32)
-]
-
-arp_table_response_layout = [
- ("failed", 1),
- ("mac_address", 48)
-]
-
-
-def eth_ipv4_description(dw):
- param_layout = ipv4_header.get_layout()
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_ipv4_user_description(dw):
- param_layout = [
- ("length", 16),
- ("protocol", 8),
- ("ip_address", 32)
- ]
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def convert_ip(s):
- ip = 0
- for e in s.split("."):
- ip = ip << 8
- ip += int(e)
- return ip
-
-
-def eth_icmp_description(dw):
- param_layout = icmp_header.get_layout()
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_icmp_user_description(dw):
- param_layout = icmp_header.get_layout() + [
- ("ip_address", 32),
- ("length", 16)
- ]
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_udp_description(dw):
- param_layout = udp_header.get_layout()
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_udp_user_description(dw):
- param_layout = [
- ("src_port", 16),
- ("dst_port", 16),
- ("ip_address", 32),
- ("length", 16)
- ]
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_etherbone_packet_description(dw):
- param_layout = etherbone_packet_header.get_layout()
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_etherbone_packet_user_description(dw):
- param_layout = etherbone_packet_header.get_layout()
- param_layout = _remove_from_layout(param_layout,
- "magic",
- "portsize",
- "addrsize",
- "version")
- param_layout += eth_udp_user_description(dw).param_layout
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_etherbone_record_description(dw):
- param_layout = etherbone_record_header.get_layout()
- payload_layout = [
- ("data", dw),
- ("error", dw//8)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_etherbone_mmap_description(dw):
- param_layout = [
- ("we", 1),
- ("count", 8),
- ("base_addr", 32),
- ("be", dw//8)
- ]
- payload_layout = [
- ("addr", 32),
- ("data", dw)
- ]
- return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-
-def eth_tty_description(dw):
- payload_layout = [("data", dw)]
- return EndpointDescription(payload_layout, packetized=False)
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac import LiteEthMAC
-from misoclib.com.liteeth.core.arp import LiteEthARP
-from misoclib.com.liteeth.core.ip import LiteEthIP
-from misoclib.com.liteeth.core.udp import LiteEthUDP
-from misoclib.com.liteeth.core.icmp import LiteEthICMP
-
-
-class LiteEthIPCore(Module, AutoCSR):
- def __init__(self, phy, mac_address, ip_address, clk_freq, with_icmp=True):
- self.submodules.mac = LiteEthMAC(phy, 8, interface="crossbar", with_preamble_crc=True)
- self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, clk_freq)
- self.submodules.ip = LiteEthIP(self.mac, mac_address, ip_address, self.arp.table)
- if with_icmp:
- self.submodules.icmp = LiteEthICMP(self.ip, ip_address)
-
-
-class LiteEthUDPIPCore(LiteEthIPCore):
- def __init__(self, phy, mac_address, ip_address, clk_freq, with_icmp=True):
- LiteEthIPCore.__init__(self, phy, mac_address, ip_address, clk_freq, with_icmp)
- self.submodules.udp = LiteEthUDP(self.ip, ip_address)
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-_arp_table_layout = [
- ("reply", 1),
- ("request", 1),
- ("ip_address", 32),
- ("mac_address", 48)
- ]
-
-
-class LiteEthARPPacketizer(Packetizer):
- def __init__(self):
- Packetizer.__init__(self,
- eth_arp_description(8),
- eth_mac_description(8),
- arp_header)
-
-
-class LiteEthARPTX(Module):
- def __init__(self, mac_address, ip_address):
- self.sink = sink = Sink(_arp_table_layout)
- self.source = source = Source(eth_mac_description(8))
-
- # # #
-
- self.submodules.packetizer = packetizer = LiteEthARPPacketizer()
-
- counter = Counter(max=max(arp_header.length, eth_min_len))
- self.submodules += counter
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- sink.ack.eq(1),
- counter.reset.eq(1),
- If(sink.stb,
- sink.ack.eq(0),
- NextState("SEND")
- )
- )
- self.comb += [
- packetizer.sink.sop.eq(counter.value == 0),
- packetizer.sink.eop.eq(counter.value == max(arp_header.length, eth_min_len)-1),
- packetizer.sink.hwtype.eq(arp_hwtype_ethernet),
- packetizer.sink.proto.eq(arp_proto_ip),
- packetizer.sink.hwsize.eq(6),
- packetizer.sink.protosize.eq(4),
- packetizer.sink.sender_mac.eq(mac_address),
- packetizer.sink.sender_ip.eq(ip_address),
- If(sink.reply,
- packetizer.sink.opcode.eq(arp_opcode_reply),
- packetizer.sink.target_mac.eq(sink.mac_address),
- packetizer.sink.target_ip.eq(sink.ip_address)
- ).Elif(sink.request,
-
- packetizer.sink.opcode.eq(arp_opcode_request),
- packetizer.sink.target_mac.eq(0xffffffffffff),
- packetizer.sink.target_ip.eq(sink.ip_address)
- )
- ]
- fsm.act("SEND",
- packetizer.sink.stb.eq(1),
- Record.connect(packetizer.source, source),
- source.target_mac.eq(packetizer.sink.target_mac),
- source.sender_mac.eq(mac_address),
- source.ethernet_type.eq(ethernet_type_arp),
- If(source.stb & source.ack,
- counter.ce.eq(1),
- If(source.eop,
- sink.ack.eq(1),
- NextState("IDLE")
- )
- )
- )
-
-
-class LiteEthARPDepacketizer(Depacketizer):
- def __init__(self):
- Depacketizer.__init__(self,
- eth_mac_description(8),
- eth_arp_description(8),
- arp_header)
-
-
-class LiteEthARPRX(Module):
- def __init__(self, mac_address, ip_address):
- self.sink = sink = Sink(eth_mac_description(8))
- self.source = source = Source(_arp_table_layout)
-
- # # #
-
- self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer()
- self.comb += Record.connect(sink, depacketizer.sink)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb & depacketizer.source.sop,
- depacketizer.source.ack.eq(0),
- NextState("CHECK")
- )
- )
- valid = Signal()
- self.sync += valid.eq(
- depacketizer.source.stb &
- (depacketizer.source.hwtype == arp_hwtype_ethernet) &
- (depacketizer.source.proto == arp_proto_ip) &
- (depacketizer.source.hwsize == 6) &
- (depacketizer.source.protosize == 4) &
- (depacketizer.source.target_ip == ip_address)
- )
- reply = Signal()
- request = Signal()
- self.comb += Case(depacketizer.source.opcode, {
- arp_opcode_request: [request.eq(1)],
- arp_opcode_reply: [reply.eq(1)],
- "default": []
- })
- self.comb += [
- source.ip_address.eq(depacketizer.source.sender_ip),
- source.mac_address.eq(depacketizer.source.sender_mac)
- ]
- fsm.act("CHECK",
- If(valid,
- source.stb.eq(1),
- source.reply.eq(reply),
- source.request.eq(request)
- ),
- NextState("TERMINATE")
- ),
- fsm.act("TERMINATE",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb & depacketizer.source.eop,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthARPTable(Module):
- def __init__(self, clk_freq, max_requests=8):
- self.sink = sink = Sink(_arp_table_layout) # from arp_rx
- self.source = source = Source(_arp_table_layout) # to arp_tx
-
- # Request/Response interface
- self.request = request = Sink(arp_table_request_layout)
- self.response = response = Source(arp_table_response_layout)
-
- # # #
-
- request_timer = WaitTimer(clk_freq//10)
- request_counter = Counter(max=max_requests)
- request_pending = FlipFlop()
- request_ip_address = FlipFlop(32)
- self.submodules += request_timer, request_counter, request_pending, request_ip_address
- self.comb += [
- request_timer.wait.eq(request_pending.q & ~request_counter.ce),
- request_pending.d.eq(1),
- request_ip_address.d.eq(request.ip_address)
- ]
-
- # Note: Store only 1 IP/MAC couple, can be improved with a real
- # table in the future to improve performance when packets are
- # targeting multiple destinations.
- update = Signal()
- cached_valid = Signal()
- cached_ip_address = Signal(32)
- cached_mac_address = Signal(48)
- cached_timer = WaitTimer(clk_freq*10)
- self.submodules += cached_timer
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- # Note: for simplicicy, if APR table is busy response from arp_rx
- # is lost. This is compensated by the protocol (retries)
- If(sink.stb & sink.request,
- NextState("SEND_REPLY")
- ).Elif(sink.stb & sink.reply & request_pending.q,
- NextState("UPDATE_TABLE"),
- ).Elif(request_counter.value == max_requests-1,
- NextState("PRESENT_RESPONSE")
- ).Elif(request.stb | (request_pending.q & request_timer.done),
- NextState("CHECK_TABLE")
- )
- )
- fsm.act("SEND_REPLY",
- source.stb.eq(1),
- source.reply.eq(1),
- source.ip_address.eq(sink.ip_address),
- source.mac_address.eq(sink.mac_address),
- If(source.ack,
- NextState("IDLE")
- )
- )
- fsm.act("UPDATE_TABLE",
- request_pending.reset.eq(1),
- update.eq(1),
- NextState("CHECK_TABLE")
- )
- self.sync += \
- If(update,
- cached_valid.eq(1),
- cached_ip_address.eq(sink.ip_address),
- cached_mac_address.eq(sink.mac_address),
- ).Else(
- If(cached_timer.done,
- cached_valid.eq(0)
- )
- )
- self.comb += cached_timer.wait.eq(~update)
- found = Signal()
- fsm.act("CHECK_TABLE",
- If(cached_valid,
- If(request_ip_address.q == cached_ip_address,
- request_ip_address.reset.eq(1),
- NextState("PRESENT_RESPONSE"),
- ).Elif(request.ip_address == cached_ip_address,
- request.ack.eq(request.stb),
- NextState("PRESENT_RESPONSE"),
- ).Else(
- request_ip_address.ce.eq(request.stb),
- NextState("SEND_REQUEST")
- )
- ).Else(
- request_ip_address.ce.eq(request.stb),
- NextState("SEND_REQUEST")
- )
- )
- fsm.act("SEND_REQUEST",
- source.stb.eq(1),
- source.request.eq(1),
- source.ip_address.eq(request_ip_address.q),
- If(source.ack,
- request_counter.reset.eq(request.stb),
- request_counter.ce.eq(1),
- request_pending.ce.eq(1),
- request.ack.eq(1),
- NextState("IDLE")
- )
- )
- self.comb += [
- If(request_counter == max_requests-1,
- response.failed.eq(1),
- request_counter.reset.eq(1),
- request_pending.reset.eq(1)
- ),
- response.mac_address.eq(cached_mac_address)
- ]
- fsm.act("PRESENT_RESPONSE",
- response.stb.eq(1),
- If(response.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthARP(Module):
- def __init__(self, mac, mac_address, ip_address, clk_freq):
- self.submodules.tx = tx = LiteEthARPTX(mac_address, ip_address)
- self.submodules.rx = rx = LiteEthARPRX(mac_address, ip_address)
- self.submodules.table = table = LiteEthARPTable(clk_freq)
- self.comb += [
- Record.connect(rx.source, table.sink),
- Record.connect(table.source, tx.sink)
- ]
- mac_port = mac.crossbar.get_port(ethernet_type_arp)
- self.comb += [
- Record.connect(tx.source, mac_port.sink),
- Record.connect(mac_port.source, rx.sink)
- ]
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthICMPPacketizer(Packetizer):
- def __init__(self):
- Packetizer.__init__(self,
- eth_icmp_description(8),
- eth_ipv4_user_description(8),
- icmp_header)
-
-
-class LiteEthICMPTX(Module):
- def __init__(self, ip_address):
- self.sink = sink = Sink(eth_icmp_user_description(8))
- self.source = source = Source(eth_ipv4_user_description(8))
-
- # # #
-
- self.submodules.packetizer = packetizer = LiteEthICMPPacketizer()
- self.comb += [
- packetizer.sink.stb.eq(sink.stb),
- packetizer.sink.sop.eq(sink.sop),
- packetizer.sink.eop.eq(sink.eop),
- sink.ack.eq(packetizer.sink.ack),
- packetizer.sink.msgtype.eq(sink.msgtype),
- packetizer.sink.code.eq(sink.code),
- packetizer.sink.checksum.eq(sink.checksum),
- packetizer.sink.quench.eq(sink.quench),
- packetizer.sink.data.eq(sink.data)
- ]
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- packetizer.source.ack.eq(1),
- If(packetizer.source.stb & packetizer.source.sop,
- packetizer.source.ack.eq(0),
- NextState("SEND")
- )
- )
- fsm.act("SEND",
- Record.connect(packetizer.source, source),
- source.length.eq(sink.length + icmp_header.length),
- source.protocol.eq(icmp_protocol),
- source.ip_address.eq(sink.ip_address),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthICMPDepacketizer(Depacketizer):
- def __init__(self):
- Depacketizer.__init__(self,
- eth_ipv4_user_description(8),
- eth_icmp_description(8),
- icmp_header)
-
-
-class LiteEthICMPRX(Module):
- def __init__(self, ip_address):
- self.sink = sink = Sink(eth_ipv4_user_description(8))
- self.source = source = Source(eth_icmp_user_description(8))
-
- # # #
-
- self.submodules.depacketizer = depacketizer = LiteEthICMPDepacketizer()
- self.comb += Record.connect(sink, depacketizer.sink)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb & depacketizer.source.sop,
- depacketizer.source.ack.eq(0),
- NextState("CHECK")
- )
- )
- valid = Signal()
- self.sync += valid.eq(
- depacketizer.source.stb &
- (sink.protocol == icmp_protocol)
- )
- fsm.act("CHECK",
- If(valid,
- NextState("PRESENT")
- ).Else(
- NextState("DROP")
- )
- )
- self.comb += [
- source.sop.eq(depacketizer.source.sop),
- source.eop.eq(depacketizer.source.eop),
- source.msgtype.eq(depacketizer.source.msgtype),
- source.code.eq(depacketizer.source.code),
- source.checksum.eq(depacketizer.source.checksum),
- source.quench.eq(depacketizer.source.quench),
- source.ip_address.eq(sink.ip_address),
- source.length.eq(sink.length - icmp_header.length),
- source.data.eq(depacketizer.source.data),
- source.error.eq(depacketizer.source.error)
- ]
- fsm.act("PRESENT",
- source.stb.eq(depacketizer.source.stb),
- depacketizer.source.ack.eq(source.ack),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
- fsm.act("DROP",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb &
- depacketizer.source.eop &
- depacketizer.source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthICMPEcho(Module):
- def __init__(self):
- self.sink = sink = Sink(eth_icmp_user_description(8))
- self.source = source = Source(eth_icmp_user_description(8))
-
- # # #
-
- self.submodules.buffer = Buffer(eth_icmp_user_description(8), 128, 2)
- self.comb += [
- Record.connect(sink, self.buffer.sink),
- Record.connect(self.buffer.source, source),
- self.source.msgtype.eq(0x0),
- self.source.checksum.eq(~((~self.buffer.source.checksum)-0x0800))
- ]
-
-
-class LiteEthICMP(Module):
- def __init__(self, ip, ip_address):
- self.submodules.tx = tx = LiteEthICMPTX(ip_address)
- self.submodules.rx = rx = LiteEthICMPRX(ip_address)
- self.submodules.echo = echo = LiteEthICMPEcho()
- self.comb += [
- Record.connect(rx.source, echo.sink),
- Record.connect(echo.source, tx.sink)
- ]
- ip_port = ip.crossbar.get_port(icmp_protocol)
- self.comb += [
- Record.connect(tx.source, ip_port.sink),
- Record.connect(ip_port.source, rx.sink)
- ]
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.ip.checksum import *
-from misoclib.com.liteeth.core.ip.crossbar import *
-
-
-class LiteEthIPV4Packetizer(Packetizer):
- def __init__(self):
- Packetizer.__init__(self,
- eth_ipv4_description(8),
- eth_mac_description(8),
- ipv4_header)
-
-
-class LiteEthIPTX(Module):
- def __init__(self, mac_address, ip_address, arp_table):
- self.sink = sink = Sink(eth_ipv4_user_description(8))
- self.source = source = Source(eth_mac_description(8))
- self.target_unreachable = Signal()
-
- # # #
-
- self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
- self.comb += [
- checksum.ce.eq(sink.stb & sink.sop),
- checksum.reset.eq(source.stb & source.eop & source.ack)
- ]
-
- self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer()
- self.comb += [
- packetizer.sink.stb.eq(sink.stb & checksum.done),
- packetizer.sink.sop.eq(sink.sop),
- packetizer.sink.eop.eq(sink.eop),
- sink.ack.eq(packetizer.sink.ack & checksum.done),
- packetizer.sink.target_ip.eq(sink.ip_address),
- packetizer.sink.protocol.eq(sink.protocol),
- packetizer.sink.total_length.eq(sink.length + (0x5*4)),
- packetizer.sink.version.eq(0x4), # ipv4
- packetizer.sink.ihl.eq(0x5), # 20 bytes
- packetizer.sink.identification.eq(0),
- packetizer.sink.ttl.eq(0x80),
- packetizer.sink.sender_ip.eq(ip_address),
- packetizer.sink.data.eq(sink.data),
- checksum.header.eq(packetizer.header),
- packetizer.sink.checksum.eq(checksum.value)
- ]
-
- target_mac = Signal(48)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- packetizer.source.ack.eq(1),
- If(packetizer.source.stb & packetizer.source.sop,
- packetizer.source.ack.eq(0),
- NextState("SEND_MAC_ADDRESS_REQUEST")
- )
- )
- self.comb += arp_table.request.ip_address.eq(sink.ip_address)
- fsm.act("SEND_MAC_ADDRESS_REQUEST",
- arp_table.request.stb.eq(1),
- If(arp_table.request.stb & arp_table.request.ack,
- NextState("WAIT_MAC_ADDRESS_RESPONSE")
- )
- )
- fsm.act("WAIT_MAC_ADDRESS_RESPONSE",
- If(arp_table.response.stb,
- arp_table.response.ack.eq(1),
- If(arp_table.response.failed,
- self.target_unreachable.eq(1),
- NextState("DROP"),
- ).Else(
- NextState("SEND")
- )
- )
- )
- self.sync += \
- If(arp_table.response.stb,
- target_mac.eq(arp_table.response.mac_address)
- )
- fsm.act("SEND",
- Record.connect(packetizer.source, source),
- source.ethernet_type.eq(ethernet_type_ip),
- source.target_mac.eq(target_mac),
- source.sender_mac.eq(mac_address),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
- fsm.act("DROP",
- packetizer.source.ack.eq(1),
- If(packetizer.source.stb &
- packetizer.source.eop &
- packetizer.source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthIPV4Depacketizer(Depacketizer):
- def __init__(self):
- Depacketizer.__init__(self,
- eth_mac_description(8),
- eth_ipv4_description(8),
- ipv4_header)
-
-
-class LiteEthIPRX(Module):
- def __init__(self, mac_address, ip_address):
- self.sink = sink = Sink(eth_mac_description(8))
- self.source = source = Source(eth_ipv4_user_description(8))
-
- # # #
-
- self.submodules.depacketizer = depacketizer = LiteEthIPV4Depacketizer()
- self.comb += Record.connect(sink, depacketizer.sink)
-
- self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=False)
- self.comb += [
- checksum.header.eq(depacketizer.header),
- checksum.reset.eq(~(depacketizer.source.stb & depacketizer.source.sop)),
- checksum.ce.eq(1)
- ]
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb & depacketizer.source.sop,
- depacketizer.source.ack.eq(0),
- NextState("CHECK")
- )
- )
- valid = Signal()
- self.sync += valid.eq(
- depacketizer.source.stb &
- (depacketizer.source.target_ip == ip_address) &
- (depacketizer.source.version == 0x4) &
- (depacketizer.source.ihl == 0x5) &
- (checksum.value == 0)
- )
-
- fsm.act("CHECK",
- If(checksum.done,
- If(valid,
- NextState("PRESENT")
- ).Else(
- NextState("DROP")
- )
- )
- )
- self.comb += [
- source.sop.eq(depacketizer.source.sop),
- source.eop.eq(depacketizer.source.eop),
- source.length.eq(depacketizer.source.total_length - (0x5*4)),
- source.protocol.eq(depacketizer.source.protocol),
- source.ip_address.eq(depacketizer.source.sender_ip),
- source.data.eq(depacketizer.source.data),
- source.error.eq(depacketizer.source.error)
- ]
- fsm.act("PRESENT",
- source.stb.eq(depacketizer.source.stb),
- depacketizer.source.ack.eq(source.ack),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
- fsm.act("DROP",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb &
- depacketizer.source.eop &
- depacketizer.source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthIP(Module):
- def __init__(self, mac, mac_address, ip_address, arp_table):
- self.submodules.tx = tx = LiteEthIPTX(mac_address, ip_address, arp_table)
- self.submodules.rx = rx = LiteEthIPRX(mac_address, ip_address)
- mac_port = mac.crossbar.get_port(ethernet_type_ip)
- self.comb += [
- Record.connect(tx.source, mac_port.sink),
- Record.connect(mac_port.source, rx.sink)
- ]
- self.submodules.crossbar = crossbar = LiteEthIPV4Crossbar()
- self.comb += [
- Record.connect(crossbar.master.source, tx.sink),
- Record.connect(rx.source, crossbar.master.sink)
- ]
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthIPV4Checksum(Module):
- def __init__(self, words_per_clock_cycle=1, skip_checksum=False):
- self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog
- self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog
- self.header = Signal(ipv4_header.length*8)
- self.value = Signal(16)
- self.done = Signal()
-
- # # #
-
- s = Signal(17)
- r = Signal(17)
- n_cycles = 0
- for i in range(ipv4_header.length//2):
- if skip_checksum and (i == ipv4_header.fields["checksum"].byte//2):
- pass
- else:
- s_next = Signal(17)
- r_next = Signal(17)
- self.comb += s_next.eq(r + self.header[i*16:(i+1)*16])
- r_next_eq = r_next.eq(Cat(s_next[:16]+s_next[16], Signal()))
- if (i%words_per_clock_cycle) != 0:
- self.comb += r_next_eq
- else:
- self.sync += \
- If(self.reset,
- r_next.eq(0)
- ).Elif(self.ce & ~self.done,
- r_next_eq
- )
- n_cycles += 1
- s, r = s_next, r_next
- self.comb += self.value.eq(~Cat(r[8:16], r[:8]))
-
- if not skip_checksum:
- n_cycles += 1
- self.submodules.counter = counter = Counter(max=n_cycles+1)
- self.comb += [
- counter.reset.eq(self.reset),
- counter.ce.eq(self.ce & ~self.done),
- self.done.eq(counter.value == n_cycles)
- ]
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.crossbar import LiteEthCrossbar
-
-
-class LiteEthIPV4MasterPort:
- def __init__(self, dw):
- self.dw = dw
- self.source = Source(eth_ipv4_user_description(dw))
- self.sink = Sink(eth_ipv4_user_description(dw))
-
-
-class LiteEthIPV4SlavePort:
- def __init__(self, dw):
- self.dw = dw
- self.sink = Sink(eth_ipv4_user_description(dw))
- self.source = Source(eth_ipv4_user_description(dw))
-
-
-class LiteEthIPV4UserPort(LiteEthIPV4SlavePort):
- def __init__(self, dw):
- LiteEthIPV4SlavePort.__init__(self, dw)
-
-
-class LiteEthIPV4Crossbar(LiteEthCrossbar):
- def __init__(self):
- LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol")
-
- def get_port(self, protocol):
- if protocol in self.users.keys():
- raise ValueError("Protocol {0:#x} already assigned".format(protocol))
- port = LiteEthIPV4UserPort(8)
- self.users[protocol] = port
- return port
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac.common import *
-from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
-from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface
-
-
-class LiteEthMAC(Module, AutoCSR):
- def __init__(self, phy, dw,
- interface="crossbar",
- endianness="big",
- with_preamble_crc=True):
- self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
- self.csrs = []
- if interface == "crossbar":
- self.submodules.crossbar = LiteEthMACCrossbar()
- self.submodules.packetizer = LiteEthMACPacketizer()
- self.submodules.depacketizer = LiteEthMACDepacketizer()
- self.comb += [
- Record.connect(self.crossbar.master.source, self.packetizer.sink),
- Record.connect(self.packetizer.source, self.core.sink),
- Record.connect(self.core.source, self.depacketizer.sink),
- Record.connect(self.depacketizer.source, self.crossbar.master.sink)
- ]
- elif interface == "wishbone":
- self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
- self.comb += Port.connect(self.interface, self.core)
- self.ev, self.bus = self.interface.sram.ev, self.interface.bus
- self.csrs = self.interface.get_csrs() + self.core.get_csrs()
- else:
- raise NotImplementedError
-
- def get_csrs(self):
- return self.csrs
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.crossbar import LiteEthCrossbar
-
-
-class LiteEthMACDepacketizer(Depacketizer):
- def __init__(self):
- Depacketizer.__init__(self,
- eth_phy_description(8),
- eth_mac_description(8),
- mac_header)
-
-
-class LiteEthMACPacketizer(Packetizer):
- def __init__(self):
- Packetizer.__init__(self,
- eth_mac_description(8),
- eth_phy_description(8),
- mac_header)
-
-
-class LiteEthMACMasterPort:
- def __init__(self, dw):
- self.source = Source(eth_mac_description(dw))
- self.sink = Sink(eth_mac_description(dw))
-
-
-class LiteEthMACSlavePort:
- def __init__(self, dw):
- self.sink = Sink(eth_mac_description(dw))
- self.source = Source(eth_mac_description(dw))
-
-
-class LiteEthMACUserPort(LiteEthMACSlavePort):
- def __init__(self, dw):
- LiteEthMACSlavePort.__init__(self, dw)
-
-
-class LiteEthMACCrossbar(LiteEthCrossbar):
- def __init__(self):
- LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type")
-
- def get_port(self, ethernet_type):
- port = LiteEthMACUserPort(8)
- if ethernet_type in self.users.keys():
- raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type))
- self.users[ethernet_type] = port
- return port
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be
-from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
-from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
-
-
-class LiteEthMACCore(Module, AutoCSR):
- def __init__(self, phy, dw, endianness="big",
- with_preamble_crc=True,
- with_padding=True):
- if dw < phy.dw:
- raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw))
-
- rx_pipeline = [phy]
- tx_pipeline = [phy]
-
- # Interpacket gap
- tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
- rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
- self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx")
- self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx")
-
- tx_pipeline += [tx_gap_inserter]
- rx_pipeline += [rx_gap_checker]
-
- # Preamble / CRC
- if isinstance(phy, LiteEthPHYSim):
- # In simulation, avoid CRC/Preamble to enable direct connection
- # to the Ethernet tap.
- self._preamble_crc = CSRStatus(reset=1)
- elif with_preamble_crc:
- self._preamble_crc = CSRStatus(reset=1)
- # Preamble insert/check
- preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
- preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
- self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
- self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
-
- # CRC insert/check
- crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
- crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
- self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
- self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
-
- tx_pipeline += [preamble_inserter, crc32_inserter]
- rx_pipeline += [preamble_checker, crc32_checker]
-
- # Padding
- if with_padding:
- padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
- padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
- self.submodules += RenameClockDomains(padding_inserter, "eth_tx")
- self.submodules += RenameClockDomains(padding_checker, "eth_rx")
-
- tx_pipeline += [padding_inserter]
- rx_pipeline += [padding_checker]
-
- # Delimiters
- if dw != 8:
- tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
- rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
- self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
- self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
-
- tx_pipeline += [tx_last_be]
- rx_pipeline += [rx_last_be]
-
- # Converters
- if dw != phy.dw:
- reverse = endianness == "big"
- tx_converter = Converter(eth_phy_description(dw),
- eth_phy_description(phy.dw),
- reverse=reverse)
- rx_converter = Converter(eth_phy_description(phy.dw),
- eth_phy_description(dw),
- reverse=reverse)
- self.submodules += RenameClockDomains(tx_converter, "eth_tx")
- self.submodules += RenameClockDomains(rx_converter, "eth_rx")
-
- tx_pipeline += [tx_converter]
- rx_pipeline += [rx_converter]
-
- # Cross Domain Crossing
- if isinstance(phy, LiteEthPHYMII):
- fifo_depth = 8
- else:
- fifo_depth = 64
- tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
- rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
- self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
- self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
-
- tx_pipeline += [tx_cdc]
- rx_pipeline += [rx_cdc]
-
- # Graph
- self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline))
- self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
-
- self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthMACCRCEngine(Module):
- """Cyclic Redundancy Check Engine
-
- Compute next CRC value from last CRC value and data input using
- an optimized asynchronous LFSR.
-
- Parameters
- ----------
- data_width : int
- Width of the data bus.
- width : int
- Width of the CRC.
- polynom : int
- Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
-
- Attributes
- ----------
- data : in
- Data input.
- last : in
- last CRC value.
- next :
- next CRC value.
- """
- def __init__(self, data_width, width, polynom):
- self.data = Signal(data_width)
- self.last = Signal(width)
- self.next = Signal(width)
-
- # # #
-
- def _optimize_eq(l):
- """
- Replace even numbers of XORs in the equation
- with an equivalent XOR
- """
- d = OrderedDict()
- for e in l:
- if e in d:
- d[e] += 1
- else:
- d[e] = 1
- r = []
- for key, value in d.items():
- if value%2 != 0:
- r.append(key)
- return r
-
- # compute and optimize CRC's LFSR
- curval = [[("state", i)] for i in range(width)]
- for i in range(data_width):
- feedback = curval.pop() + [("din", i)]
- for j in range(width-1):
- if (polynom & (1<<(j+1))):
- curval[j] += feedback
- curval[j] = _optimize_eq(curval[j])
- curval.insert(0, feedback)
-
- # implement logic
- for i in range(width):
- xors = []
- for t, n in curval[i]:
- if t == "state":
- xors += [self.last[n]]
- elif t == "din":
- xors += [self.data[n]]
- self.comb += self.next[i].eq(optree("^", xors))
-
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class LiteEthMACCRC32(Module):
- """IEEE 802.3 CRC
-
- Implement an IEEE 802.3 CRC generator/checker.
-
- Parameters
- ----------
- data_width : int
- Width of the data bus.
-
- Attributes
- ----------
- d : in
- Data input.
- value : out
- CRC value (used for generator).
- error : out
- CRC error (used for checker).
- """
- width = 32
- polynom = 0x04C11DB7
- init = 2**width-1
- check = 0xC704DD7B
- def __init__(self, data_width):
- self.data = Signal(data_width)
- self.value = Signal(self.width)
- self.error = Signal()
-
- # # #
-
- self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
- reg = Signal(self.width, reset=self.init)
- self.sync += reg.eq(self.engine.next)
- self.comb += [
- self.engine.data.eq(self.data),
- self.engine.last.eq(reg),
-
- self.value.eq(~reg[::-1]),
- self.error.eq(self.engine.next != self.check)
- ]
-
-
-class LiteEthMACCRCInserter(Module):
- """CRC Inserter
-
- Append a CRC at the end of each packet.
-
- Parameters
- ----------
- description : description
- description of the dataflow.
-
- Attributes
- ----------
- sink : in
- Packets input without CRC.
- source : out
- Packets output with CRC.
- """
- def __init__(self, crc_class, description):
- self.sink = sink = Sink(description)
- self.source = source = Source(description)
- self.busy = Signal()
-
- # # #
-
- dw = flen(sink.data)
- crc = crc_class(dw)
- fsm = FSM(reset_state="IDLE")
- self.submodules += crc, fsm
-
- fsm.act("IDLE",
- crc.reset.eq(1),
- sink.ack.eq(1),
- If(sink.stb & sink.sop,
- sink.ack.eq(0),
- NextState("COPY"),
- )
- )
- fsm.act("COPY",
- crc.ce.eq(sink.stb & source.ack),
- crc.data.eq(sink.data),
- Record.connect(sink, source),
- source.eop.eq(0),
- If(sink.stb & sink.eop & source.ack,
- NextState("INSERT"),
- )
- )
- ratio = crc.width//dw
- if ratio > 1:
- cnt = Signal(max=ratio, reset=ratio-1)
- cnt_done = Signal()
- fsm.act("INSERT",
- source.stb.eq(1),
- chooser(crc.value, cnt, source.data, reverse=True),
- If(cnt_done,
- source.eop.eq(1),
- If(source.ack, NextState("IDLE"))
- )
- )
- self.comb += cnt_done.eq(cnt == 0)
- self.sync += \
- If(fsm.ongoing("IDLE"),
- cnt.eq(cnt.reset)
- ).Elif(fsm.ongoing("INSERT") & ~cnt_done,
- cnt.eq(cnt - source.ack)
- )
- else:
- fsm.act("INSERT",
- source.stb.eq(1),
- source.eop.eq(1),
- source.data.eq(crc.value),
- If(source.ack, NextState("IDLE"))
- )
- self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
-
-
-class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter):
- def __init__(self, description):
- LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, description)
-
-
-class LiteEthMACCRCChecker(Module):
- """CRC Checker
-
- Check CRC at the end of each packet.
-
- Parameters
- ----------
- description : description
- description of the dataflow.
-
- Attributes
- ----------
- sink : in
- Packets input with CRC.
- source : out
- Packets output without CRC and "error" set to 0
- on eop when CRC OK / set to 1 when CRC KO.
- """
- def __init__(self, crc_class, description):
- self.sink = sink = Sink(description)
- self.source = source = Source(description)
- self.busy = Signal()
-
- # # #
-
- dw = flen(sink.data)
- crc = crc_class(dw)
- self.submodules += crc
- ratio = crc.width//dw
-
- error = Signal()
- fifo = InsertReset(SyncFIFO(description, ratio + 1))
- self.submodules += fifo
-
- fsm = FSM(reset_state="RESET")
- self.submodules += fsm
-
- fifo_in = Signal()
- fifo_out = Signal()
- fifo_full = Signal()
-
- self.comb += [
- fifo_full.eq(fifo.fifo.level == ratio),
- fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
- fifo_out.eq(source.stb & source.ack),
-
- Record.connect(sink, fifo.sink),
- fifo.sink.stb.eq(fifo_in),
- self.sink.ack.eq(fifo_in),
-
- source.stb.eq(sink.stb & fifo_full),
- source.sop.eq(fifo.source.sop),
- source.eop.eq(sink.eop),
- fifo.source.ack.eq(fifo_out),
- source.payload.eq(fifo.source.payload),
-
- source.error.eq(sink.error | crc.error),
- ]
-
- fsm.act("RESET",
- crc.reset.eq(1),
- fifo.reset.eq(1),
- NextState("IDLE"),
- )
- self.comb += crc.data.eq(sink.data)
- fsm.act("IDLE",
- If(sink.stb & sink.sop & sink.ack,
- crc.ce.eq(1),
- NextState("COPY")
- )
- )
- fsm.act("COPY",
- If(sink.stb & sink.ack,
- crc.ce.eq(1),
- If(sink.eop,
- NextState("RESET")
- )
- )
- )
- self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
-
-
-class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):
- def __init__(self, description):
- LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, description)
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-class LiteEthMACGap(Module):
- def __init__(self, dw, ack_on_gap=False):
- self.sink = sink = Sink(eth_phy_description(dw))
- self.source = source = Source(eth_phy_description(dw))
-
- # # #
-
- gap = math.ceil(eth_interpacket_gap/(dw//8))
- self.submodules.counter = counter = Counter(max=gap)
-
- self.submodules.fsm = fsm = FSM(reset_state="COPY")
- fsm.act("COPY",
- counter.reset.eq(1),
- Record.connect(sink, source),
- If(sink.stb & sink.eop & sink.ack,
- NextState("GAP")
- )
- )
- fsm.act("GAP",
- counter.ce.eq(1),
- sink.ack.eq(int(ack_on_gap)),
- If(counter.value == (gap-1),
- NextState("COPY")
- )
- )
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthMACTXLastBE(Module):
- def __init__(self, dw):
- self.sink = sink = Sink(eth_phy_description(dw))
- self.source = source = Source(eth_phy_description(dw))
-
- # # #
-
- ongoing = Signal()
- self.sync += \
- If(sink.stb & sink.ack,
- If(sink.sop,
- ongoing.eq(1)
- ).Elif(sink.last_be,
- ongoing.eq(0)
- )
- )
- self.comb += [
- source.stb.eq(sink.stb & (sink.sop | ongoing)),
- source.sop.eq(sink.sop),
- source.eop.eq(sink.last_be),
- source.data.eq(sink.data),
- sink.ack.eq(source.ack)
- ]
-
-
-class LiteEthMACRXLastBE(Module):
- def __init__(self, dw):
- self.sink = sink = Sink(eth_phy_description(dw))
- self.source = source = Source(eth_phy_description(dw))
-
- # # #
-
- self.comb += [
- source.stb.eq(sink.stb),
- source.sop.eq(sink.sop),
- source.eop.eq(sink.eop),
- source.data.eq(sink.data),
- source.last_be.eq(sink.eop),
- sink.ack.eq(source.ack)
- ]
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthMACPaddingInserter(Module):
- def __init__(self, dw, padding):
- self.sink = sink = Sink(eth_phy_description(dw))
- self.source = source = Source(eth_phy_description(dw))
-
- # # #
-
- padding_limit = math.ceil(padding/(dw/8))-1
-
- self.submodules.counter = counter = Counter(16, reset=1)
- counter_done = Signal()
- self.comb += [
- counter.reset.eq(sink.stb & sink.sop & sink.ack),
- counter.ce.eq(source.stb & source.ack),
- counter_done.eq(counter.value >= padding_limit),
- ]
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- Record.connect(sink, source),
- If(source.stb & source.ack,
- counter.ce.eq(1),
- If(sink.eop,
- If(~counter_done,
- source.eop.eq(0),
- NextState("PADDING")
- )
- )
- )
- )
- fsm.act("PADDING",
- source.stb.eq(1),
- source.eop.eq(counter_done),
- source.data.eq(0),
- If(source.ack,
- If(counter_done,
- NextState("IDLE")
- )
- )
- )
-
-
-class LiteEthMACPaddingChecker(Module):
- def __init__(self, dw, packet_min_length):
- self.sink = sink = Sink(eth_phy_description(dw))
- self.source = source = Source(eth_phy_description(dw))
-
- # # #
-
- # XXX see if we should drop the packet when
- # payload size < minimum ethernet payload size
- self.comb += Record.connect(sink, source)
-
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthMACPreambleInserter(Module):
- def __init__(self, dw):
- self.sink = Sink(eth_phy_description(dw))
- self.source = Source(eth_phy_description(dw))
-
- # # #
-
- preamble = Signal(64, reset=eth_preamble)
- cnt_max = (64//dw)-1
- cnt = Signal(max=cnt_max+1)
- clr_cnt = Signal()
- inc_cnt = Signal()
-
- self.sync += \
- If(clr_cnt,
- cnt.eq(0)
- ).Elif(inc_cnt,
- cnt.eq(cnt+1)
- )
-
- fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- self.sink.ack.eq(1),
- clr_cnt.eq(1),
- If(self.sink.stb & self.sink.sop,
- self.sink.ack.eq(0),
- NextState("INSERT"),
- )
- )
- fsm.act("INSERT",
- self.source.stb.eq(1),
- self.source.sop.eq(cnt == 0),
- chooser(preamble, cnt, self.source.data),
- If(cnt == cnt_max,
- If(self.source.ack, NextState("COPY"))
- ).Else(
- inc_cnt.eq(self.source.ack)
- )
- )
-
- self.comb += [
- self.source.data.eq(self.sink.data),
- self.source.last_be.eq(self.sink.last_be)
- ]
- fsm.act("COPY",
- Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
- self.source.sop.eq(0),
-
- If(self.sink.stb & self.sink.eop & self.source.ack,
- NextState("IDLE"),
- )
- )
-
-
-class LiteEthMACPreambleChecker(Module):
- def __init__(self, dw):
- self.sink = Sink(eth_phy_description(dw))
- self.source = Source(eth_phy_description(dw))
-
- # # #
-
- preamble = Signal(64, reset=eth_preamble)
- cnt_max = (64//dw) - 1
- cnt = Signal(max=cnt_max+1)
- clr_cnt = Signal()
- inc_cnt = Signal()
-
- self.sync += \
- If(clr_cnt,
- cnt.eq(0)
- ).Elif(inc_cnt,
- cnt.eq(cnt+1)
- )
-
- discard = Signal()
- clr_discard = Signal()
- set_discard = Signal()
-
- self.sync += \
- If(clr_discard,
- discard.eq(0)
- ).Elif(set_discard,
- discard.eq(1)
- )
-
- sop = Signal()
- clr_sop = Signal()
- set_sop = Signal()
- self.sync += \
- If(clr_sop,
- sop.eq(0)
- ).Elif(set_sop,
- sop.eq(1)
- )
-
- ref = Signal(dw)
- match = Signal()
- self.comb += [
- chooser(preamble, cnt, ref),
- match.eq(self.sink.data == ref)
- ]
-
- fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
-
- fsm.act("IDLE",
- self.sink.ack.eq(1),
- clr_cnt.eq(1),
- clr_discard.eq(1),
- If(self.sink.stb & self.sink.sop,
- clr_cnt.eq(0),
- inc_cnt.eq(1),
- clr_discard.eq(0),
- set_discard.eq(~match),
- NextState("CHECK"),
- )
- )
- fsm.act("CHECK",
- self.sink.ack.eq(1),
- If(self.sink.stb,
- set_discard.eq(~match),
- If(cnt == cnt_max,
- If(discard | (~match),
- NextState("IDLE")
- ).Else(
- set_sop.eq(1),
- NextState("COPY")
- )
- ).Else(
- inc_cnt.eq(1)
- )
- )
- )
- self.comb += [
- self.source.data.eq(self.sink.data),
- self.source.last_be.eq(self.sink.last_be)
- ]
- fsm.act("COPY",
- Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
- self.source.sop.eq(sop),
- clr_sop.eq(self.source.stb & self.source.ack),
-
- If(self.source.stb & self.source.eop & self.source.ack,
- NextState("IDLE"),
- )
- )
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-from migen.bank.description import *
-from migen.bank.eventmanager import *
-
-
-class LiteEthMACSRAMWriter(Module, AutoCSR):
- def __init__(self, dw, depth, nslots=2):
- self.sink = sink = Sink(eth_phy_description(dw))
- self.crc_error = Signal()
-
- slotbits = max(log2_int(nslots), 1)
- lengthbits = log2_int(depth*4) # length in bytes
-
- self._slot = CSRStatus(slotbits)
- self._length = CSRStatus(lengthbits)
-
- self.submodules.ev = EventManager()
- self.ev.available = EventSourceLevel()
- self.ev.finalize()
-
- # # #
-
- # packet dropped if no slot available
- sink.ack.reset = 1
-
- # length computation
- increment = Signal(3)
- self.comb += \
- If(sink.last_be[3],
- increment.eq(1)
- ).Elif(sink.last_be[2],
- increment.eq(2)
- ).Elif(sink.last_be[1],
- increment.eq(3)
- ).Else(
- increment.eq(4)
- )
- counter = Counter(lengthbits, increment=increment)
- self.submodules += counter
-
- # slot computation
- slot = Counter(slotbits)
- self.submodules += slot
-
- ongoing = Signal()
-
- # status fifo
- fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
- self.submodules += fifo
-
- # fsm
- fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
-
- fsm.act("IDLE",
- If(sink.stb & sink.sop,
- If(fifo.sink.ack,
- ongoing.eq(1),
- counter.ce.eq(1),
- NextState("WRITE")
- )
- )
- )
- fsm.act("WRITE",
- counter.ce.eq(sink.stb),
- ongoing.eq(1),
- If(sink.stb & sink.eop,
- If((sink.error & sink.last_be) != 0,
- NextState("DISCARD")
- ).Else(
- NextState("TERMINATE")
- )
- )
- )
- fsm.act("DISCARD",
- counter.reset.eq(1),
- NextState("IDLE")
- )
- self.comb += [
- fifo.sink.slot.eq(slot.value),
- fifo.sink.length.eq(counter.value)
- ]
- fsm.act("TERMINATE",
- counter.reset.eq(1),
- slot.ce.eq(1),
- fifo.sink.stb.eq(1),
- NextState("IDLE")
- )
- self.comb += [
- fifo.source.ack.eq(self.ev.available.clear),
- self.ev.available.trigger.eq(fifo.source.stb),
- self._slot.status.eq(fifo.source.slot),
- self._length.status.eq(fifo.source.length),
- ]
-
- # memory
- mems = [None]*nslots
- ports = [None]*nslots
- for n in range(nslots):
- mems[n] = Memory(dw, depth)
- ports[n] = mems[n].get_port(write_capable=True)
- self.specials += ports[n]
- self.mems = mems
-
- cases = {}
- for n, port in enumerate(ports):
- cases[n] = [
- ports[n].adr.eq(counter.value[2:]),
- ports[n].dat_w.eq(sink.data),
- If(sink.stb & ongoing,
- ports[n].we.eq(0xf)
- )
- ]
- self.comb += Case(slot.value, cases)
-
-
-class LiteEthMACSRAMReader(Module, AutoCSR):
- def __init__(self, dw, depth, nslots=2):
- self.source = source = Source(eth_phy_description(dw))
-
- slotbits = max(log2_int(nslots), 1)
- lengthbits = log2_int(depth*4) # length in bytes
- self.lengthbits = lengthbits
-
- self._start = CSR()
- self._ready = CSRStatus()
- self._slot = CSRStorage(slotbits)
- self._length = CSRStorage(lengthbits)
-
- self.submodules.ev = EventManager()
- self.ev.done = EventSourcePulse()
- self.ev.finalize()
-
- # # #
-
- # command fifo
- fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
- self.submodules += fifo
- self.comb += [
- fifo.sink.stb.eq(self._start.re),
- fifo.sink.slot.eq(self._slot.storage),
- fifo.sink.length.eq(self._length.storage),
- self._ready.status.eq(fifo.sink.ack)
- ]
-
- # length computation
- self.submodules.counter = counter = Counter(lengthbits, increment=4)
-
- # fsm
- first = Signal()
- last = Signal()
- last_d = Signal()
-
- fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
-
- fsm.act("IDLE",
- counter.reset.eq(1),
- If(fifo.source.stb,
- NextState("CHECK")
- )
- )
- fsm.act("CHECK",
- If(~last_d,
- NextState("SEND"),
- ).Else(
- NextState("END"),
- )
- )
- length_lsb = fifo.source.length[0:2]
- self.comb += [
- If(last,
- If(length_lsb == 3,
- source.last_be.eq(0b0010)
- ).Elif(length_lsb == 2,
- source.last_be.eq(0b0100)
- ).Elif(length_lsb == 1,
- source.last_be.eq(0b1000)
- ).Else(
- source.last_be.eq(0b0001)
- )
- )
- ]
- fsm.act("SEND",
- source.stb.eq(1),
- source.sop.eq(first),
- source.eop.eq(last),
- If(source.ack,
- counter.ce.eq(~last),
- NextState("CHECK")
- )
- )
- fsm.act("END",
- fifo.source.ack.eq(1),
- self.ev.done.trigger.eq(1),
- NextState("IDLE")
- )
-
- # first/last computation
- self.sync += [
- If(fsm.ongoing("IDLE"),
- first.eq(1)
- ).Elif(source.stb & source.ack,
- first.eq(0)
- )
- ]
- self.comb += last.eq((counter.value + 4) >= fifo.source.length)
- self.sync += last_d.eq(last)
-
- # memory
- rd_slot = fifo.source.slot
-
- mems = [None]*nslots
- ports = [None]*nslots
- for n in range(nslots):
- mems[n] = Memory(dw, depth)
- ports[n] = mems[n].get_port()
- self.specials += ports[n]
- self.mems = mems
-
- cases = {}
- for n, port in enumerate(ports):
- self.comb += ports[n].adr.eq(counter.value[2:])
- cases[n] = [source.data.eq(port.dat_r)]
- self.comb += Case(rd_slot, cases)
-
-
-class LiteEthMACSRAM(Module, AutoCSR):
- def __init__(self, dw, depth, nrxslots, ntxslots):
- self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots)
- self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots)
- self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
- self.sink, self.source = self.writer.sink, self.reader.source
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac.frontend import sram
-
-from migen.bus import wishbone
-from migen.fhdl.simplify import FullMemoryWE
-
-
-class LiteEthMACWishboneInterface(Module, AutoCSR):
- def __init__(self, dw, nrxslots=2, ntxslots=2):
- self.sink = Sink(eth_phy_description(dw))
- self.source = Source(eth_phy_description(dw))
- self.bus = wishbone.Interface()
-
- # # #
-
- # storage in SRAM
- sram_depth = buffer_depth//(dw//8)
- self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots)
- self.comb += [
- Record.connect(self.sink, self.sram.sink),
- Record.connect(self.sram.source, self.source)
- ]
-
- # Wishbone interface
- wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True)
- for n in range(nrxslots)]
- # TODO: FullMemoryWE should move to Mibuild
- wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
- for n in range(ntxslots)]
- wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
-
- wb_slaves = []
- decoderoffset = log2_int(sram_depth)
- decoderbits = log2_int(len(wb_sram_ifs))
- for n, wb_sram_if in enumerate(wb_sram_ifs):
- def slave_filter(a, v=n):
- return a[decoderoffset:decoderoffset+decoderbits] == v
- wb_slaves.append((slave_filter, wb_sram_if.bus))
- self.submodules += wb_sram_if
- wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
- self.submodules += wb_con
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.udp.crossbar import *
-
-
-class LiteEthUDPPacketizer(Packetizer):
- def __init__(self):
- Packetizer.__init__(self,
- eth_udp_description(8),
- eth_ipv4_user_description(8),
- udp_header)
-
-
-class LiteEthUDPTX(Module):
- def __init__(self, ip_address):
- self.sink = sink = Sink(eth_udp_user_description(8))
- self.source = source = Source(eth_ipv4_user_description(8))
-
- # # #
-
- self.submodules.packetizer = packetizer = LiteEthUDPPacketizer()
- self.comb += [
- packetizer.sink.stb.eq(sink.stb),
- packetizer.sink.sop.eq(sink.sop),
- packetizer.sink.eop.eq(sink.eop),
- sink.ack.eq(packetizer.sink.ack),
- packetizer.sink.src_port.eq(sink.src_port),
- packetizer.sink.dst_port.eq(sink.dst_port),
- packetizer.sink.length.eq(sink.length + udp_header.length),
- packetizer.sink.checksum.eq(0), # Disabled (MAC CRC is enough)
- packetizer.sink.data.eq(sink.data)
- ]
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- packetizer.source.ack.eq(1),
- If(packetizer.source.stb & packetizer.source.sop,
- packetizer.source.ack.eq(0),
- NextState("SEND")
- )
- )
- fsm.act("SEND",
- Record.connect(packetizer.source, source),
- source.length.eq(packetizer.sink.length),
- source.protocol.eq(udp_protocol),
- source.ip_address.eq(sink.ip_address),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthUDPDepacketizer(Depacketizer):
- def __init__(self):
- Depacketizer.__init__(self,
- eth_ipv4_user_description(8),
- eth_udp_description(8),
- udp_header)
-
-
-class LiteEthUDPRX(Module):
- def __init__(self, ip_address):
- self.sink = sink = Sink(eth_ipv4_user_description(8))
- self.source = source = Source(eth_udp_user_description(8))
-
- # # #
-
- self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer()
- self.comb += Record.connect(sink, depacketizer.sink)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb & depacketizer.source.sop,
- depacketizer.source.ack.eq(0),
- NextState("CHECK")
- )
- )
- valid = Signal()
- self.sync += valid.eq(
- depacketizer.source.stb &
- (sink.protocol == udp_protocol)
- )
-
- fsm.act("CHECK",
- If(valid,
- NextState("PRESENT")
- ).Else(
- NextState("DROP")
- )
- )
- self.comb += [
- source.sop.eq(depacketizer.source.sop),
- source.eop.eq(depacketizer.source.eop),
- source.src_port.eq(depacketizer.source.src_port),
- source.dst_port.eq(depacketizer.source.dst_port),
- source.ip_address.eq(sink.ip_address),
- source.length.eq(depacketizer.source.length - udp_header.length),
- source.data.eq(depacketizer.source.data),
- source.error.eq(depacketizer.source.error)
- ]
- fsm.act("PRESENT",
- source.stb.eq(depacketizer.source.stb),
- depacketizer.source.ack.eq(source.ack),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
- fsm.act("DROP",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb &
- depacketizer.source.eop &
- depacketizer.source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthUDP(Module):
- def __init__(self, ip, ip_address):
- self.submodules.tx = tx = LiteEthUDPTX(ip_address)
- self.submodules.rx = rx = LiteEthUDPRX(ip_address)
- ip_port = ip.crossbar.get_port(udp_protocol)
- self.comb += [
- Record.connect(tx.source, ip_port.sink),
- Record.connect(ip_port.source, rx.sink)
- ]
- self.submodules.crossbar = crossbar = LiteEthUDPCrossbar()
- self.comb += [
- Record.connect(crossbar.master.source, tx.sink),
- Record.connect(rx.source, crossbar.master.sink)
- ]
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.crossbar import LiteEthCrossbar
-
-
-class LiteEthUDPMasterPort:
- def __init__(self, dw):
- self.dw = dw
- self.source = Source(eth_udp_user_description(dw))
- self.sink = Sink(eth_udp_user_description(dw))
-
-
-class LiteEthUDPSlavePort:
- def __init__(self, dw):
- self.dw = dw
- self.sink = Sink(eth_udp_user_description(dw))
- self.source = Source(eth_udp_user_description(dw))
-
-
-class LiteEthUDPUserPort(LiteEthUDPSlavePort):
- def __init__(self, dw):
- LiteEthUDPSlavePort.__init__(self, dw)
-
-
-class LiteEthUDPCrossbar(LiteEthCrossbar):
- def __init__(self):
- LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port")
-
- def get_port(self, udp_port, dw=8):
- if udp_port in self.users.keys():
- raise ValueError("Port {0:#x} already assigned".format(udp_port))
- user_port = LiteEthUDPUserPort(dw)
- internal_port = LiteEthUDPUserPort(8)
- if dw != 8:
- converter = Converter(eth_udp_user_description(user_port.dw),
- eth_udp_user_description(8))
- self.submodules += converter
- self.comb += [
- Record.connect(user_port.sink, converter.sink),
- Record.connect(converter.source, internal_port.sink)
- ]
- converter = Converter(eth_udp_user_description(8),
- eth_udp_user_description(user_port.dw))
- self.submodules += converter
- self.comb += [
- Record.connect(internal_port.source, converter.sink),
- Record.connect(converter.source, user_port.source)
- ]
- self.users[udp_port] = internal_port
- else:
- self.users[udp_port] = user_port
- return user_port
+++ /dev/null
-from collections import OrderedDict
-
-from misoclib.com.liteeth.common import *
-
-class LiteEthCrossbar(Module):
- def __init__(self, master_port, dispatch_param):
- self.users = OrderedDict()
- self.master = master_port(8)
- self.dispatch_param = dispatch_param
-
- # overload this in derived classes
- def get_port(self, *args, **kwargs):
- pass
-
- def do_finalize(self):
- # TX arbitrate
- sinks = [port.sink for port in self.users.values()]
- self.submodules.arbiter = Arbiter(sinks, self.master.source)
-
- # RX dispatch
- sources = [port.source for port in self.users.values()]
- self.submodules.dispatcher = Dispatcher(self.master.sink,
- sources,
- one_hot=True)
- cases = {}
- cases["default"] = self.dispatcher.sel.eq(0)
- for i, (k, v) in enumerate(self.users.items()):
- cases[k] = self.dispatcher.sel.eq(2**i)
- self.comb += \
- Case(getattr(self.master.sink, self.dispatch_param), cases)
+++ /dev/null
-*.diff
-*.pyc
-*~
-*.bc
-*.md
-
-# Ignore generated files
-build/
+++ /dev/null
-# Makefile for Sphinx documentation
-#
-
-# You can set these variables from the command line.
-SPHINXOPTS =
-SPHINXBUILD = sphinx-build
-PAPER =
-BUILDDIR = build
-
-# User-friendly check for sphinx-build
-ifeq ($(shell which $(SPHINXBUILD) >/dev/null 2>&1; echo $$?), 1)
-$(error The '$(SPHINXBUILD)' command was not found. Make sure you have Sphinx installed, then set the SPHINXBUILD environment variable to point to the full path of the '$(SPHINXBUILD)' executable. Alternatively you can add the directory with the executable to your PATH. If you don't have Sphinx installed, grab it from http://sphinx-doc.org/)
-endif
-
-# Internal variables.
-PAPEROPT_a4 = -D latex_paper_size=a4
-PAPEROPT_letter = -D latex_paper_size=letter
-ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source
-# the i18n builder cannot share the environment and doctrees with the others
-I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source
-
-.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext
-
-help:
- @echo "Please use \`make <target>' where <target> is one of"
- @echo " html to make standalone HTML files"
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- @echo " singlehtml to make a single large HTML file"
- @echo " pickle to make pickle files"
- @echo " json to make JSON files"
- @echo " htmlhelp to make HTML files and a HTML help project"
- @echo " epub to make an epub"
- @echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
- @echo " latexpdf to make LaTeX files and run them through pdflatex"
- @echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx"
- @echo " text to make text files"
- @echo " man to make manual pages"
- @echo " texinfo to make Texinfo files"
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- @echo " doctest to run all doctests embedded in the documentation (if enabled)"
-
-clean:
- rm -rf $(BUILDDIR)/*
-
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- $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
- @echo
- @echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
-
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- $(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
- @echo
- @echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
-
-singlehtml:
- $(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
- @echo
- @echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
-
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- $(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
- @echo
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- @echo
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- $(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
- @echo
- @echo "Build finished; now you can run HTML Help Workshop with the" \
- ".hhp project file in $(BUILDDIR)/htmlhelp."
-
-epub:
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- @echo
- @echo "Build finished. The epub file is in $(BUILDDIR)/epub."
-
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- $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
- @echo
- @echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
- @echo "Run \`make' in that directory to run these through (pdf)latex" \
- "(use \`make latexpdf' here to do that automatically)."
-
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- $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
- @echo "Running LaTeX files through pdflatex..."
- $(MAKE) -C $(BUILDDIR)/latex all-pdf
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-
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- $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
- @echo "Running LaTeX files through platex and dvipdfmx..."
- $(MAKE) -C $(BUILDDIR)/latex all-pdf-ja
- @echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
-
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- @echo
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-
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-
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- @echo "Run \`make' in that directory to run these through makeinfo" \
- "(use \`make info' here to do that automatically)."
-
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- @echo "Running Texinfo files through makeinfo..."
- make -C $(BUILDDIR)/texinfo info
- @echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo."
-
-gettext:
- $(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale
- @echo
- @echo "Build finished. The message catalogs are in $(BUILDDIR)/locale."
-
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- @echo
- @echo "The overview file is in $(BUILDDIR)/changes."
-
-linkcheck:
- $(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
- @echo
- @echo "Link check complete; look for any errors in the above output " \
- "or in $(BUILDDIR)/linkcheck/output.txt."
-
-doctest:
- $(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
- @echo "Testing of doctests in the sources finished, look at the " \
- "results in $(BUILDDIR)/doctest/output.txt."
-
-xml:
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-
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- @echo
- @echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."
+++ /dev/null
-@ECHO OFF
-
-REM Command file for Sphinx documentation
-
-if "%SPHINXBUILD%" == "" (
- set SPHINXBUILD=sphinx-build
-)
-set BUILDDIR=build
-set ALLSPHINXOPTS=-d %BUILDDIR%/doctrees %SPHINXOPTS% source
-set I18NSPHINXOPTS=%SPHINXOPTS% source
-if NOT "%PAPER%" == "" (
- set ALLSPHINXOPTS=-D latex_paper_size=%PAPER% %ALLSPHINXOPTS%
- set I18NSPHINXOPTS=-D latex_paper_size=%PAPER% %I18NSPHINXOPTS%
-)
-
-if "%1" == "" goto help
-
-if "%1" == "help" (
- :help
- echo.Please use `make ^<target^>` where ^<target^> is one of
- echo. html to make standalone HTML files
- echo. dirhtml to make HTML files named index.html in directories
- echo. singlehtml to make a single large HTML file
- echo. pickle to make pickle files
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- echo. htmlhelp to make HTML files and a HTML help project
- echo. epub to make an epub
- echo. latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter
- echo. text to make text files
- echo. man to make manual pages
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- echo. gettext to make PO message catalogs
- echo. changes to make an overview over all changed/added/deprecated items
- echo. xml to make Docutils-native XML files
- echo. pseudoxml to make pseudoxml-XML files for display purposes
- echo. linkcheck to check all external links for integrity
- echo. doctest to run all doctests embedded in the documentation if enabled
- goto end
-)
-
-if "%1" == "clean" (
- for /d %%i in (%BUILDDIR%\*) do rmdir /q /s %%i
- del /q /s %BUILDDIR%\*
- goto end
-)
-
-
-%SPHINXBUILD% 2> nul
-if errorlevel 9009 (
- echo.
- echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
- echo.installed, then set the SPHINXBUILD environment variable to point
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-if "%1" == "html" (
- %SPHINXBUILD% -b html %ALLSPHINXOPTS% %BUILDDIR%/html
- if errorlevel 1 exit /b 1
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- echo.Build finished. The HTML pages are in %BUILDDIR%/html.
- goto end
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-if "%1" == "dirhtml" (
- %SPHINXBUILD% -b dirhtml %ALLSPHINXOPTS% %BUILDDIR%/dirhtml
- if errorlevel 1 exit /b 1
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-if "%1" == "latex" (
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- if errorlevel 1 exit /b 1
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- if errorlevel 1 exit /b 1
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- echo.Build finished. The message catalogs are in %BUILDDIR%/locale.
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-
-if "%1" == "changes" (
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- if errorlevel 1 exit /b 1
- echo.
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-)
-
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-)
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-if "%1" == "xml" (
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-
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-
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-
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-
-VERSION = (0, 1, 6)
-
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-__version_full__ = __version__
-
-
-def get_html_theme_path():
- """Return list of HTML theme paths."""
- cur_dir = os.path.abspath(os.path.dirname(os.path.dirname(__file__)))
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+++ /dev/null
-<div role="navigation" aria-label="breadcrumbs navigation">
-
- <div class="breadcrumb-box">
- <a class="breadcrumb-box-item" href="{{ pathto(master_doc) }}">Home</a>
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- <a class="breadcrumb-box-item" href="{{ doc.link|e }}">» {{ doc.title }}</a>
- {% endfor %}
- <div class="breadcrumb-box-item">» {{ title }}</div>
- </div>
-
-</div>
\ No newline at end of file
+++ /dev/null
-<footer>
- {% if next or prev %}
- <div class="rst-footer-buttons" role="navigation" aria-label="footer navigation">
- {% if next %}
- <a href="{{ next.link|e }}" class="btn btn-neutral float-right" title="{{ next.title|striptags|e }}"/>Next <span class="fa fa-arrow-circle-right"></span></a>
- {% endif %}
- {% if prev %}
- <a href="{{ prev.link|e }}" class="btn btn-neutral" title="{{ prev.title|striptags|e }}"><span class="fa fa-arrow-circle-left"></span> Previous</a>
- {% endif %}
- </div>
- {% endif %}
-
-
- <!--begin hamishw addition -->
-
-
-
- <!-- -->
-
- <!--Footer important links
- If no such page exists then nav item is not created. CSS defines which of the long or short version is
- displayed. -->
-
-
- {% set footer_links = [
- ('docs/getting_started/bug_reports', 'Report Bug', 'Report Bug'),
- ('docs/introducing_liteeth/license', 'Licensing', 'Licensing'),
- ('docs/contributing/contributing', 'Contributing', 'Contributing'),
- ('docs/introducing_liteeth/release_notes', 'Release notes', 'Release notes'),
- ('docs/introducing_liteeth/community', 'Help', 'Contact'),
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- <div class="footer-options">
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-
-
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-
-
-
-<!-- end section moved here by hamishw -->
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- <!-- section moved here by hamishw - needs tidying, which is why it is still in breadcrumbs mode -->
- <ul class="wy-breadcrumbs">
- <li class="wy-breadcrumbs-aside">
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- </li>
-
- </ul>
-
- <p>
- {%- if show_copyright %}
- {%- if hasdoc('copyright') %}
- {% trans path=pathto('copyright'), copyright=copyright|e %}© <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
- {%- else %}
- <!-- {% trans copyright=copyright|e %}© Copyright {{ copyright }}.{% endtrans %} -->
- © Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">EnjoyDigital and M-Labs Contributors</a>.
- <!-- update theme to remove the translation stuff here - it was breaking due to link to AUTHORS file. This is a cludge to allow specific link to my authors file -->
- {%- endif %}
- {%- endif %}
-
- {%- if last_updated %}
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+++ /dev/null
-{# TEMPLATE VAR SETTINGS #}
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-
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-<head>
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- <meta name="viewport" content="width=device-width, initial-scale=1.0">
- {% block htmltitle %}
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-
- {# FAVICON #}
- {% if favicon %}
- <link rel="shortcut icon" href="{{ pathto('_static/' + favicon, 1) }}"/>
- {% endif %}
-
- {# CSS #}
- <link href='https://fonts.googleapis.com/css?family=Lato:400,700|Roboto+Slab:400,700|Inconsolata:400,700' rel='stylesheet' type='text/css'>
-
- {# OPENSEARCH #}
- {% if not embedded %}
- {% if use_opensearch %}
- <link rel="search" type="application/opensearchdescription+xml" title="{% trans docstitle=docstitle|e %}Search within {{ docstitle }}{% endtrans %}" href="{{ pathto('_static/opensearch.xml', 1) }}"/>
- {% endif %}
-
- {% endif %}
-
- {# RTD hosts this file, so just load on non RTD builds #}
- {% if not READTHEDOCS %}
- <link rel="stylesheet" href="{{ pathto('_static/' + style, 1) }}" type="text/css" />
- {% endif %}
-
- {% for cssfile in css_files %}
- <link rel="stylesheet" href="{{ pathto(cssfile, 1) }}" type="text/css" />
- {% endfor %}
-
- {%- block linktags %}
- {%- if hasdoc('about') %}
- <link rel="author" title="{{ _('About these documents') }}"
- href="{{ pathto('about') }}"/>
- {%- endif %}
- {%- if hasdoc('genindex') %}
- <link rel="index" title="{{ _('Index') }}"
- href="{{ pathto('genindex') }}"/>
- {%- endif %}
- {%- if hasdoc('search') %}
- <link rel="search" title="{{ _('Search') }}" href="{{ pathto('search') }}"/>
- {%- endif %}
- {%- if hasdoc('copyright') %}
- <link rel="copyright" title="{{ _('Copyright') }}" href="{{ pathto('copyright') }}"/>
- {%- endif %}
- <link rel="top" title="{{ docstitle|e }}" href="{{ pathto('index') }}"/>
- {%- if parents %}
- <link rel="up" title="{{ parents[-1].title|striptags|e }}" href="{{ parents[-1].link|e }}"/>
- {%- endif %}
- {%- if next %}
- <link rel="next" title="{{ next.title|striptags|e }}" href="{{ next.link|e }}"/>
- {%- endif %}
- {%- if prev %}
- <link rel="prev" title="{{ prev.title|striptags|e }}" href="{{ prev.link|e }}"/>
- {%- endif %}
- {%- endblock %}
- {%- block extrahead %} {% endblock %}
-
- {# Keep modernizr in head - http://modernizr.com/docs/#installing #}
- <script src="https://cdnjs.cloudflare.com/ajax/libs/modernizr/2.6.2/modernizr.min.js"></script>
-
-</head>
-
-<body class="wy-body-for-nav" role="document">
-
-
-<div class="grid-to-center-rtd-theme">
-
- <div class="wy-grid-for-nav">
-
-
-
- {# SIDE NAV, TOGGLES ON MOBILE #}
- <nav data-toggle="wy-nav-shift" class="wy-nav-side">
- <div class="wy-side-nav-search">
- <!-- <a href="{{ pathto(master_doc) }}" class="fa fa-home"> {{ project }}</a> -->
- <a href="{{ pathto(master_doc) }}"> <img src="{{ url_root }}/_static/{{ logo }}" alt="Logo" /> </a>
-
- {% include "searchbox.html" %}
- </div>
-
- <div class="wy-menu wy-menu-vertical" data-spy="affix" role="navigation" aria-label="main navigation">
-
- {% set toctree = toctree(maxdepth=4, collapse=False, includehidden=True) %}
- {% if toctree %}
- {{ toctree }}
- <a class="toctree-l1" title="Index" href="{{ pathto('genindex') }}">Index</a>
- {% else %}
- <!-- Local TOC -->
- <div class="local-toc">{{ toc }}</div>
- {% endif %}
- </div>
-
- </nav>
-
- <section data-toggle="wy-nav-shift" class="wy-nav-content-wrap">
-
- {# MOBILE NAV, TRIGGLES SIDE NAV ON TOGGLE #}
- <nav class="wy-nav-top" role="navigation" aria-label="top navigation">
- <i data-toggle="wy-nav-top" class="fa fa-bars"></i>
- <!-- <a href="{{ pathto(master_doc) }}">{{ project }}</a> -->
- <a href="{{ pathto(master_doc) }}"> <img src="{{ url_root }}/_static/{{ logo }}" alt="Logo" /> </a>
- </nav>
-
-
-
- {# PAGE CONTENT #}
- <div class="wy-nav-content">
- <div class="rst-content">
-
- <!--begin hamishw addition -->
-
- <!--Nav bar defined as a document followed by short version of nav text and long version
- If no such page exists then nav item is not created. CSS defines which of the long or short version is
- displayed. -->
- {% set navigation_bar = [
- ('docs/index', 'Docs', 'Documentation'),
- ('docs/getting_started/downloads', 'SDK', 'Downloads'),
- ('docs/introducing_liteeth/community', 'Help', 'Community'),
- ('https://github.com/enjoy-digital/liteeth', 'Github', 'Github Project')
-] -%}
-
-
- <div class="main-nav-bar" style="">
-
- <!-- the layout of the menu options - centered with left and right alignment of the first and last loop items respectively.
- This is VERY UGLY as I'm adding to the CSS in the code to force the alignment. Would be better just to have the elements here and have the CSS in the CSS file. This could be done with a CSS selector, but not worked out how yet. -->
-
- <ul id="menu-options">
- {% for document, shorttext, longtext in navigation_bar %}
- {%- if hasdoc(document) %}
- <li{%- if loop.first %} style="text-align:left;" {%- endif %}{%- if loop.last %} style="text-align:right;" {%- endif %}><a class="navlink-short" title="{{ shorttext }}" href="{{ pathto(document) }}">{{ shorttext }}</a><a class="navlink-long" title="{{ longtext }}" href="{{ pathto(document) }}">{{ longtext }}</a></li>
- {%- elif document | truncate(4, True, end='') == 'http' %}
- <li{%- if loop.first %} style="text-align:left;" {%- endif %}{%- if loop.last %} style="text-align:right;" {%- endif %}><a class="navlink-short external" href="{{ document }}">{{ shorttext }}</a><a class="navlink-long external" href="{{ document }}">{{ longtext }}</a></li>
- {%- endif %}
- {% endfor %}
- </ul>
- <!-- <div style="clear:both;"></div> -->
- {% include "breadcrumbs.html" %}
-
- </div>
-
-
-
- <!--end hamishw addition -->
-
- <!--HamishW move {% include "breadcrumbs.html" %} -->
- <div role="main">
- {% block body %}{% endblock %}
- </div>
- {% include "footer.html" %}
- </div>
- </div>
-
- </section>
-
- </div>
- {% include "versions.html" %}
-
- {% if not embedded %}
-
- <script type="text/javascript">
- var DOCUMENTATION_OPTIONS = {
- URL_ROOT:'{{ url_root }}',
- VERSION:'{{ release|e }}',
- COLLAPSE_INDEX:false,
- FILE_SUFFIX:'{{ '' if no_search_suffix else file_suffix }}',
- HAS_SOURCE: {{ has_source|lower }}
- };
- </script>
- {%- for scriptfile in script_files %}
- <script type="text/javascript" src="{{ pathto(scriptfile, 1) }}"></script>
- {%- endfor %}
-
- {% endif %}
-
- {# RTD hosts this file, so just load on non RTD builds #}
- {% if not READTHEDOCS %}
- <script type="text/javascript" src="{{ pathto('_static/js/theme.js', 1) }}"></script>
- {% endif %}
-
- {# STICKY NAVIGATION #}
- {% if theme_sticky_navigation %}
- <script type="text/javascript">
- jQuery(function () {
- SphinxRtdTheme.StickyNav.enable();
- });
- </script>
- {% endif %}
-
- {%- block footer %} {% endblock %}
-</div>
-</body>
-</html>
+++ /dev/null
-{#
- basic/layout.html
- ~~~~~~~~~~~~~~~~~
-
- Master layout template for Sphinx themes.
-
- :copyright: Copyright 2007-2013 by the Sphinx team, see AUTHORS.
- :license: BSD, see LICENSE for details.
-#}
-{%- block doctype -%}
-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
- "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
-{%- endblock %}
-{%- set reldelim1 = reldelim1 is not defined and ' »' or reldelim1 %}
-{%- set reldelim2 = reldelim2 is not defined and ' |' or reldelim2 %}
-{%- set render_sidebar = (not embedded) and (not theme_nosidebar|tobool) and
- (sidebars != []) %}
-{%- set url_root = pathto('', 1) %}
-{# XXX necessary? #}
-{%- if url_root == '#' %}{% set url_root = '' %}{% endif %}
-{%- if not embedded and docstitle %}
- {%- set titlesuffix = " — "|safe + docstitle|e %}
-{%- else %}
- {%- set titlesuffix = "" %}
-{%- endif %}
-
-{%- macro relbar() %}
- <div class="related">
- <h3>{{ _('Navigation') }}</h3>
- <ul>
- {%- for rellink in rellinks %}
- <li class="right" {% if loop.first %}style="margin-right: 10px"{% endif %}>
- <a href="{{ pathto(rellink[0]) }}" title="{{ rellink[1]|striptags|e }}"
- {{ accesskey(rellink[2]) }}>{{ rellink[3] }}</a>
- {%- if not loop.first %}{{ reldelim2 }}{% endif %}</li>
- {%- endfor %}
- {%- block rootrellink %}
- <li><a href="{{ pathto(master_doc) }}">{{ shorttitle|e }}</a>{{ reldelim1 }}</li>
- {%- endblock %}
- {%- for parent in parents %}
- <li><a href="{{ parent.link|e }}" {% if loop.last %}{{ accesskey("U") }}{% endif %}>{{ parent.title }}</a>{{ reldelim1 }}</li>
- {%- endfor %}
- {%- block relbaritems %} {% endblock %}
- </ul>
- </div>
-{%- endmacro %}
-
-{%- macro sidebar() %}
- {%- if render_sidebar %}
- <div class="sphinxsidebar">
- <div class="sphinxsidebarwrapper">
- {%- block sidebarlogo %}
- {%- if logo %}
- <p class="logo"><a href="{{ pathto(master_doc) }}">
- <img class="logo" src="{{ pathto('_static/' + logo, 1) }}" alt="Logo"/>
- </a></p>
- {%- endif %}
- {%- endblock %}
- {%- if sidebars != None %}
- {#- new style sidebar: explicitly include/exclude templates #}
- {%- for sidebartemplate in sidebars %}
- {%- include sidebartemplate %}
- {%- endfor %}
- {%- else %}
- {#- old style sidebars: using blocks -- should be deprecated #}
- {%- block sidebartoc %}
- {%- include "localtoc.html" %}
- {%- endblock %}
- {%- block sidebarrel %}
- {%- include "relations.html" %}
- {%- endblock %}
- {%- block sidebarsourcelink %}
- {%- include "sourcelink.html" %}
- {%- endblock %}
- {%- if customsidebar %}
- {%- include customsidebar %}
- {%- endif %}
- {%- block sidebarsearch %}
- {%- include "searchbox.html" %}
- {%- endblock %}
- {%- endif %}
- </div>
- </div>
- {%- endif %}
-{%- endmacro %}
-
-{%- macro script() %}
- <script type="text/javascript">
- var DOCUMENTATION_OPTIONS = {
- URL_ROOT: '{{ url_root }}',
- VERSION: '{{ release|e }}',
- COLLAPSE_INDEX: false,
- FILE_SUFFIX: '{{ '' if no_search_suffix else file_suffix }}',
- HAS_SOURCE: {{ has_source|lower }}
- };
- </script>
- {%- for scriptfile in script_files %}
- <script type="text/javascript" src="{{ pathto(scriptfile, 1) }}"></script>
- {%- endfor %}
-{%- endmacro %}
-
-{%- macro css() %}
- <link rel="stylesheet" href="{{ pathto('_static/' + style, 1) }}" type="text/css" />
- <link rel="stylesheet" href="{{ pathto('_static/pygments.css', 1) }}" type="text/css" />
- {%- for cssfile in css_files %}
- <link rel="stylesheet" href="{{ pathto(cssfile, 1) }}" type="text/css" />
- {%- endfor %}
-{%- endmacro %}
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <meta http-equiv="Content-Type" content="text/html; charset={{ encoding }}" />
- {{ metatags }}
- {%- block htmltitle %}
- <title>{{ title|striptags|e }}{{ titlesuffix }}</title>
- {%- endblock %}
- {{ css() }}
- {%- if not embedded %}
- {{ script() }}
- {%- if use_opensearch %}
- <link rel="search" type="application/opensearchdescription+xml"
- title="{% trans docstitle=docstitle|e %}Search within {{ docstitle }}{% endtrans %}"
- href="{{ pathto('_static/opensearch.xml', 1) }}"/>
- {%- endif %}
- {%- if favicon %}
- <link rel="shortcut icon" href="{{ pathto('_static/' + favicon, 1) }}"/>
- {%- endif %}
- {%- endif %}
-{%- block linktags %}
- {%- if hasdoc('about') %}
- <link rel="author" title="{{ _('About these documents') }}" href="{{ pathto('about') }}" />
- {%- endif %}
- {%- if hasdoc('genindex') %}
- <link rel="index" title="{{ _('Index') }}" href="{{ pathto('genindex') }}" />
- {%- endif %}
- {%- if hasdoc('search') %}
- <link rel="search" title="{{ _('Search') }}" href="{{ pathto('search') }}" />
- {%- endif %}
- {%- if hasdoc('copyright') %}
- <link rel="copyright" title="{{ _('Copyright') }}" href="{{ pathto('copyright') }}" />
- {%- endif %}
- <link rel="top" title="{{ docstitle|e }}" href="{{ pathto('index') }}" />
- {%- if parents %}
- <link rel="up" title="{{ parents[-1].title|striptags|e }}" href="{{ parents[-1].link|e }}" />
- {%- endif %}
- {%- if next %}
- <link rel="next" title="{{ next.title|striptags|e }}" href="{{ next.link|e }}" />
- {%- endif %}
- {%- if prev %}
- <link rel="prev" title="{{ prev.title|striptags|e }}" href="{{ prev.link|e }}" />
- {%- endif %}
-{%- endblock %}
-{%- block extrahead %} {% endblock %}
- </head>
- <body>
-{%- block header %}{% endblock %}
-
-{%- block relbar1 %}{{ relbar() }}{% endblock %}
-
-{%- block content %}
- {%- block sidebar1 %} {# possible location for sidebar #} {% endblock %}
-
- <div class="document">
- {%- block document %}
- <div class="documentwrapper">
- {%- if render_sidebar %}
- <div class="bodywrapper">
- {%- endif %}
- <div class="body">
- {% block body %} {% endblock %}
- </div>
- {%- if render_sidebar %}
- </div>
- {%- endif %}
- </div>
- {%- endblock %}
-
- {%- block sidebar2 %}{{ sidebar() }}{% endblock %}
- <div class="clearer"></div>
- </div>
-{%- endblock %}
-
-{%- block relbar2 %}{{ relbar() }}{% endblock %}
-
-{%- block footer %}
- <div class="footer">
- {%- if show_copyright %}
- {%- if hasdoc('copyright') %}
- {% trans path=pathto('copyright'), copyright=copyright|e %}© <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
- {%- else %}
- {% trans copyright=copyright|e %}© Copyright {{ copyright }}.{% endtrans %}
- {%- endif %}
- {%- endif %}
- {%- if last_updated %}
- {% trans last_updated=last_updated|e %}Last updated on {{ last_updated }}.{% endtrans %}
- {%- endif %}
- {%- if show_sphinx %}
- {% trans sphinx_version=sphinx_version|e %}Created using <a href="http://sphinx-doc.org/">Sphinx</a> {{ sphinx_version }}.{% endtrans %}
- {%- endif %}
- </div>
- <p>asdf asdf asdf asdf 22</p>
-{%- endblock %}
- </body>
-</html>
-
+++ /dev/null
-{#
- basic/search.html
- ~~~~~~~~~~~~~~~~~
-
- Template for the search page.
-
- :copyright: Copyright 2007-2013 by the Sphinx team, see AUTHORS.
- :license: BSD, see LICENSE for details.
-#}
-{%- extends "layout.html" %}
-{% set title = _('Search') %}
-{% set script_files = script_files + ['_static/searchtools.js'] %}
-{% block footer %}
- <script type="text/javascript">
- jQuery(function() { Search.loadIndex("{{ pathto('searchindex.js', 1) }}"); });
- </script>
- {# this is used when loading the search index using $.ajax fails,
- such as on Chrome for documents on localhost #}
- <script type="text/javascript" id="searchindexloader"></script>
- {{ super() }}
-{% endblock %}
-{% block body %}
- <noscript>
- <div id="fallback" class="admonition warning">
- <p class="last">
- {% trans %}Please activate JavaScript to enable the search
- functionality.{% endtrans %}
- </p>
- </div>
- </noscript>
-
- {% if search_performed %}
- <h2>{{ _('Search Results') }}</h2>
- {% if not search_results %}
- <p>{{ _('Your search did not match any documents. Please make sure that all words are spelled correctly and that you\'ve selected enough categories.') }}</p>
- {% endif %}
- {% endif %}
- <div id="search-results">
- {% if search_results %}
- <ul>
- {% for href, caption, context in search_results %}
- <li>
- <a href="{{ pathto(item.href) }}">{{ caption }}</a>
- <p class="context">{{ context|e }}</p>
- </li>
- {% endfor %}
- </ul>
- {% endif %}
- </div>
-{% endblock %}
+++ /dev/null
-<div role="search">
- <form id ="rtd-search-form" class="wy-form" action="{{ pathto('search') }}" method="get">
- <input type="text" name="q" placeholder="Search docs" />
- <input type="hidden" name="check_keywords" value="yes" />
- <input type="hidden" name="area" value="default" />
- </form>
-</div>
+++ /dev/null
-.fa:before{-webkit-font-smoothing:antialiased}.clearfix{*zoom:1}.clearfix:before,.clearfix:after{display:table;content:""}.clearfix:after{clear:both}@font-face{font-family:FontAwesome;font-weight:normal;font-style:normal;src:url("../font/fontawesome_webfont.eot");src:url("../font/fontawesome_webfont.eot?#iefix") format("embedded-opentype"),url("../font/fontawesome_webfont.woff") format("woff"),url("../font/fontawesome_webfont.ttf") format("truetype"),url("../font/fontawesome_webfont.svg#FontAwesome") format("svg")}.fa:before{display:inline-block;font-family:FontAwesome;font-style:normal;font-weight:normal;line-height:1;text-decoration:inherit}a .fa{display:inline-block;text-decoration:inherit}li .fa{display:inline-block}li .fa-large:before,li .fa-large:before{width:1.875em}ul.fas{list-style-type:none;margin-left:2em;text-indent:-0.8em}ul.fas li .fa{width:0.8em}ul.fas li .fa-large:before,ul.fas li .fa-large:before{vertical-align:baseline}.fa-book:before{content:"\f02d"}.icon-book:before{content:"\f02d"}.fa-caret-down:before{content:"\f0d7"}.icon-caret-down:before{content:"\f0d7"}.fa-caret-up:before{content:"\f0d8"}.icon-caret-up:before{content:"\f0d8"}.fa-caret-left:before{content:"\f0d9"}.icon-caret-left:before{content:"\f0d9"}.fa-caret-right:before{content:"\f0da"}.icon-caret-right:before{content:"\f0da"}.rst-versions{position:fixed;bottom:0;left:0;width:300px;color:#fcfcfc;background:#1f1d1d;border-top:solid 10px #343131;font-family:"Lato","proxima-nova","Helvetica Neue",Arial,sans-serif;z-index:400}.rst-versions a{color:#2980b9;text-decoration:none}.rst-versions .rst-badge-small{display:none}.rst-versions .rst-current-version{padding:12px;background-color:#272525;display:block;text-align:right;font-size:90%;cursor:pointer;color:#27ae60;*zoom:1}.rst-versions .rst-current-version:before,.rst-versions .rst-current-version:after{display:table;content:""}.rst-versions .rst-current-version:after{clear:both}.rst-versions .rst-current-version .fa{color:#fcfcfc}.rst-versions .rst-current-version .fa-book{float:left}.rst-versions .rst-current-version .icon-book{float:left}.rst-versions .rst-current-version.rst-out-of-date{background-color:#e74c3c;color:#fff}.rst-versions .rst-current-version.rst-active-old-version{background-color:#f1c40f;color:#000}.rst-versions.shift-up .rst-other-versions{display:block}.rst-versions .rst-other-versions{font-size:90%;padding:12px;color:gray;display:none}.rst-versions .rst-other-versions hr{display:block;height:1px;border:0;margin:20px 0;padding:0;border-top:solid 1px #413d3d}.rst-versions .rst-other-versions dd{display:inline-block;margin:0}.rst-versions .rst-other-versions dd a{display:inline-block;padding:6px;color:#fcfcfc}.rst-versions.rst-badge{width:auto;bottom:20px;right:20px;left:auto;border:none;max-width:300px}.rst-versions.rst-badge .icon-book{float:none}.rst-versions.rst-badge .fa-book{float:none}.rst-versions.rst-badge.shift-up .rst-current-version{text-align:right}.rst-versions.rst-badge.shift-up .rst-current-version .fa-book{float:left}.rst-versions.rst-badge.shift-up .rst-current-version .icon-book{float:left}.rst-versions.rst-badge .rst-current-version{width:auto;height:30px;line-height:30px;padding:0 6px;display:block;text-align:center}@media screen and (max-width: 768px){.rst-versions{width:85%;display:none}.rst-versions.shift{display:block}img{width:100%;height:auto}}
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- .wy-breadcrumbs li a:first-child{padding-left:0}.wy-breadcrumbs-extra{margin-bottom:0;color:#b3b3b3;font-size:80%;display:inline-block}
-
- @media screen and (max-width: 480px)
- {.wy-breadcrumbs-extra{display:none}.wy-breadcrumbs li.wy-breadcrumbs-aside{display:none}}@media print{.wy-breadcrumbs li.wy-breadcrumbs-aside{display:none}}.wy-affix{position:fixed;top:1.618em}.wy-menu a:hover{text-decoration:none}.wy-menu-horiz{*zoom:1}.wy-menu-horiz:before,.wy-menu-horiz:after{display:table;content:""}.wy-menu-horiz:after{clear:both}.wy-menu-horiz ul,.wy-menu-horiz li{display:inline-block}.wy-menu-horiz li:hover{background:rgba(255,255,255,0.1)}.wy-menu-horiz li.divide-left{border-left:solid 1px #404040}.wy-menu-horiz li.divide-right{border-right:solid 1px #404040}.wy-menu-horiz a{height:32px;display:inline-block;line-height:32px;padding:0 16px}.wy-menu-vertical header{height:32px;display:inline-block;line-height:32px;padding:0 1.618em;display:block;font-weight:bold;text-transform:uppercase;font-size:80%;color:#2980b9;white-space:nowrap}.wy-menu-vertical ul{margin-bottom:0}.wy-menu-vertical li.divide-top{border-top:solid 1px #404040}.wy-menu-vertical li.divide-bottom{border-bottom:solid 1px #404040}.wy-menu-vertical li.current{background:#e3e3e3}
-
- .wy-menu-vertical li.current a{
- color:gray;
- border-right:solid 1px #c9c9c9;
- padding:0.4045em 2.427em
- }
-
- .wy-menu-vertical li.current a:hover{background:#d6d6d6}
-
- .wy-menu-vertical li.on a {
- color:#404040;
- padding:0.4045em 1.618em;
- font-weight:bold;
- position:relative;
- background:#fcfcfc;
- border:none;
- border-bottom:solid 1px #c9c9c9;
- border-top:solid 1px #c9c9c9;
- padding-left:1.618em -4px
- }
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-
-.wy-menu-vertical li.current>a {
- color:#404040;
- padding:0.4045em 1.618em;
- font-weight:bold;
- position:relative;
- background:#fcfcfc;
- border:none;
- border-bottom:solid 1px #c9c9c9;
- border-top:solid 1px #c9c9c9;
- padding-left:1.618em -4px
- }
-
- .wy-menu-vertical li.on a:hover,.wy-menu-vertical li.current>a:hover{background:#fcfcfc}
- .wy-menu-vertical li.toctree-l2.current>a{background:#c9c9c9;padding:0.4045em 2.427em}.wy-menu-vertical li.current ul{display:block}.wy-menu-vertical li ul{margin-bottom:0;display:none}.wy-menu-vertical .local-toc li ul{display:block}.wy-menu-vertical li ul li a{margin-bottom:0;color:#b3b3b3;font-weight:normal}.wy-menu-vertical a{display:inline-block;line-height:18px;padding:0.4045em 1.618em;display:block;position:relative;font-size:90%;color:#b3b3b3}.wy-menu-vertical a:hover{background-color:#4e4a4a;cursor:pointer}.wy-menu-vertical a:active{background-color:#2980b9;cursor:pointer;color:#fff}
-
- .wy-side-nav-search {z-index:200;
- background-color:#2980b9;
- text-align:center;
- /* padding:0.809em; */
- /* padding-top: 0.809em;*/
- padding-right: 0.809em;
- padding-bottom: 0.809em;
- padding-left: 0.809em;
- display:block;
- color:#fcfcfc;
- margin-bottom:0.809em
- }
-
- .wy-side-nav-search input[type=text]{width:100%;border-radius:50px;padding:6px 12px;border-color:#2472a4}
-
-
- .wy-side-nav-search img{
- display:block;
- margin:auto auto 0.809em auto;
- /*height:45px;*/
- /*width:45px;*/
- width:200px;
- /*background-color:#2980b9;*/
- padding:5px;
- /*border-radius:100%*/
- }
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- .wy-side-nav-search>a,.wy-side-nav-search .wy-dropdown>a {
- color:#fcfcfc;
- font-size:100%;
- font-weight:bold;
- display:inline-block;
- padding-top: 4px;
- padding-right: 6px;
- /*padding-bottom: 4px;*/
- padding-left: 6px;
- /* margin-bottom:0.809em */
- }
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- .wy-side-nav-search>a:hover,.wy-side-nav-search .wy-dropdown>a:hover{background:rgba(255,255,255,0.1)}.wy-nav .wy-menu-vertical header{color:#2980b9}.wy-nav .wy-menu-vertical a{color:#b3b3b3}.wy-nav .wy-menu-vertical a:hover{background-color:#2980b9;color:#fff}[data-menu-wrap]{-webkit-transition:all 0.2s ease-in;-moz-transition:all 0.2s ease-in;transition:all 0.2s ease-in;position:absolute;opacity:1;width:100%;opacity:0}[data-menu-wrap].move-center{left:0;right:auto;opacity:1}[data-menu-wrap].move-left{right:auto;left:-100%;opacity:0}[data-menu-wrap].move-right{right:-100%;left:auto;opacity:0}
-
- .wy-body-for-nav{
- /* background:left repeat-y #F1F0F0; */
- /*
- background:left repeat-y rgb(97, 6, 6);
- background-size:300px 1px
- */ /* This is deep red colour - removed */
- /* background-image:url(data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAEAAAABCAIAAACQd1PeAAAAGXRFWHRTb2Z0d2FyZQBBZG9iZSBJbWFnZVJlYWR5ccllPAAAAyRpVFh0WE1MOmNvbS5hZG9iZS54bXAAAAAAADw/eHBhY2tldCBiZWdpbj0i77u/IiBpZD0iVzVNME1wQ2VoaUh6cmVTek5UY3prYzlkIj8+IDx4OnhtcG1ldGEgeG1sbnM6eD0iYWRvYmU6bnM6bWV0YS8iIHg6eG1wdGs9IkFkb2JlIFhNUCBDb3JlIDUuMy1jMDExIDY2LjE0NTY2MSwgMjAxMi8wMi8wNi0xNDo1NjoyNyAgICAgICAgIj4gPHJkZjpSREYgeG1sbnM6cmRmPSJodHRwOi8vd3d3LnczLm9yZy8xOTk5LzAyLzIyLXJkZi1zeW50YXgtbnMjIj4gPHJkZjpEZXNjcmlwdGlvbiByZGY6YWJvdXQ9IiIgeG1sbnM6eG1wPSJodHRwOi8vbnMuYWRvYmUuY29tL3hhcC8xLjAvIiB4bWxuczp4bXBNTT0iaHR0cDovL25zLmFkb2JlLmNvbS94YXAvMS4wL21tLyIgeG1sbnM6c3RSZWY9Imh0dHA6Ly9ucy5hZG9iZS5jb20veGFwLzEuMC9zVHlwZS9SZXNvdXJjZVJlZiMiIHhtcDpDcmVhdG9yVG9vbD0iQWRvYmUgUGhvdG9zaG9wIENTNiAoTWFjaW50b3NoKSIgeG1wTU06SW5zdGFuY2VJRD0ieG1wLmlpZDoxOERBMTRGRDBFMUUxMUUzODUwMkJCOThDMEVFNURFMCIgeG1wTU06RG9jdW1lbnRJRD0ieG1wLmRpZDoxOERBMTRGRTBFMUUxMUUzODUwMkJCOThDMEVFNURFMCI+IDx4bXBNTTpEZXJpdmVkRnJvbSBzdFJlZjppbnN0YW5jZUlEPSJ4bXAuaWlkOjE4REExNEZCMEUxRTExRTM4NTAyQkI5OEMwRUU1REUwIiBzdFJlZjpkb2N1bWVudElEPSJ4bXAuZGlkOjE4REExNEZDMEUxRTExRTM4NTAyQkI5OEMwRUU1REUwIi8+IDwvcmRmOkRlc2NyaXB0aW9uPiA8L3JkZjpSREY+IDwveDp4bXBtZXRhPiA8P3hwYWNrZXQgZW5kPSJyIj8+EwrlwAAAAA5JREFUeNpiMDU0BAgwAAE2AJgB9BnaAAAAAElFTkSuQmCC); */
-
- }
-
- .wy-grid-for-nav {
- /* position:absolute; */
- position:relative; /* Make left column full length */
- width:100%;
- height:100%
- }
-
- .wy-nav-side{position:absolute;top:0;left:0;width:300px;overflow:hidden;min-height:100%;background:#343131;z-index:200}
-
- .wy-nav-top{
- display:none;
- background:#2980b9;
- color:#fff;
- padding:0.4045em 0.809em;
- position:relative;
- line-height:50px;
- text-align:center;
- font-size:100%;
- *zoom:1}
-
- .wy-nav-top:before,.wy-nav-top:after{display:table;content:""}
-
- .wy-nav-top:after{clear:both}.wy-nav-top a{color:#fff;font-weight:bold}
-
- .wy-nav-top img{
- margin-right:12px;
- /*height:45px; */
- /*width:45px;*/
- width:200px;
- background-color:#2980b9;
- padding:5px;
- /*border-radius:100%*/
- }
-
- .wy-nav-top i{font-size:30px;float:left;cursor:pointer}
- .wy-nav-content-wrap{
- margin-left:300px;
- /* background:#fcfcfc; */
- min-height:100%
- }
-
- .wy-nav-content{
- /* padding:1.618em 3.236em; */
- /* padding-top: 1.618em; */
- padding-right: 3.236em;
- padding-bottom: 1.618em;
- padding-left: 3.236em;
- height:100%;
- min-height: 100vh; /* ensure is always full height of browser window */
- max-width:800px;
- /* margin:auto; */
- margin-left:0px;
- background: #fcfcfc;
- }
-
- .wy-body-mask{position:fixed;width:100%;height:100%;background:rgba(0,0,0,0.2);display:none;z-index:499}.wy-body-mask.on{display:block}footer{color:#999}footer p{margin-bottom:12px}.rst-footer-buttons{*zoom:1}.rst-footer-buttons:before,.rst-footer-buttons:after{display:table;content:""}.rst-footer-buttons:after{clear:both}#search-results .search li{margin-bottom:24px;border-bottom:solid 1px #e1e4e5;padding-bottom:24px}#search-results .search li:first-child{border-top:solid 1px #e1e4e5;padding-top:24px}#search-results .search li a{font-size:120%;margin-bottom:12px;display:inline-block}#search-results .context{color:gray;font-size:90%}
-
- @media screen and (max-width: 768px){
- .wy-body-for-nav{background:#fcfcfc}
- .wy-nav-top{display:block}.wy-nav-side{left:-300px}
- .wy-nav-side.shift{width:85%;left:0}
- .wy-nav-content-wrap{margin-left:0}
- .wy-nav-content-wrap .wy-nav-content {
- /* padding:1.618em */
- /* padding-top: 1.618em; */
- padding-right: 1.618em;
- padding-bottom: 1.618em;
- padding-left: 1.618em;
- }
- .wy-nav-content-wrap.shift{
- position:relative; /* position:fixed; */
- min-width:100%;
- left:85%;
- top:0;height:100%;
- overflow:hidden
- }
- }
-
- @media screen and (min-width: 1400px) {
- /* .wy-nav-content-wrap{background:rgba(0,0,0,0.05)} */
- .wy-nav-content{
- /* margin:0; */
- background:#fcfcfc}
- }
-
- @media print{.wy-nav-side{display:none}.wy-nav-content-wrap{margin-left:0}}nav.stickynav{position:absolute/* previously fixed hamishw */ ;top:0}.rst-versions{position:fixed;bottom:0;left:0;width:300px;color:#fcfcfc;background:#1f1d1d;border-top:solid 10px #343131;font-family:"Lato","proxima-nova","Helvetica Neue",Arial,sans-serif;z-index:400}.rst-versions a{color:#2980b9;text-decoration:none}.rst-versions .rst-badge-small{display:none}.rst-versions .rst-current-version{padding:12px;background-color:#272525;display:block;text-align:right;font-size:90%;cursor:pointer;color:#27ae60;*zoom:1}.rst-versions .rst-current-version:before,.rst-versions .rst-current-version:after{display:table;content:""}.rst-versions .rst-current-version:after{clear:both}.rst-versions .rst-current-version .fa,.rst-versions .rst-current-version .rst-content .admonition-title,.rst-content .rst-versions .rst-current-version .admonition-title,.rst-versions .rst-current-version .rst-content h1 .headerlink,.rst-content h1 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h2 .headerlink,.rst-content h2 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h3 .headerlink,.rst-content h3 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h4 .headerlink,.rst-content h4 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h5 .headerlink,.rst-content h5 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h6 .headerlink,.rst-content h6 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content dl dt .headerlink,.rst-content dl dt .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .icon{color:#fcfcfc}.rst-versions .rst-current-version .fa-book,.rst-versions .rst-current-version .icon-book{float:left}.rst-versions .rst-current-version .icon-book{float:left}.rst-versions .rst-current-version.rst-out-of-date{background-color:#e74c3c;color:#fff}.rst-versions .rst-current-version.rst-active-old-version{background-color:#f1c40f;color:#000}.rst-versions.shift-up .rst-other-versions{display:block}.rst-versions .rst-other-versions{font-size:90%;padding:12px;color:gray;display:none}.rst-versions .rst-other-versions hr{display:block;height:1px;border:0;margin:20px 0;padding:0;border-top:solid 1px #413d3d}.rst-versions .rst-other-versions dd{display:inline-block;margin:0}.rst-versions .rst-other-versions dd a{display:inline-block;padding:6px;color:#fcfcfc}.rst-versions.rst-badge{width:auto;bottom:20px;right:20px;left:auto;border:none;max-width:300px}.rst-versions.rst-badge .icon-book{float:none}.rst-versions.rst-badge .fa-book,.rst-versions.rst-badge .icon-book{float:none}.rst-versions.rst-badge.shift-up .rst-current-version{text-align:right}.rst-versions.rst-badge.shift-up .rst-current-version .fa-book,.rst-versions.rst-badge.shift-up .rst-current-version .icon-book{float:left}.rst-versions.rst-badge.shift-up .rst-current-version .icon-book{float:left}.rst-versions.rst-badge .rst-current-version{width:auto;height:30px;line-height:30px;padding:0 6px;display:block;text-align:center}
-
- @media screen and (max-width: 768px){
- .rst-versions{width:85%;display:none}.rst-versions.shift{display:block}img{width:100%;height:auto}}.rst-content img{max-width:100%;height:auto !important}.rst-content div.figure{margin-bottom:24px}.rst-content div.figure.align-center{text-align:center}.rst-content .section>img{margin-bottom:24px}.rst-content blockquote{margin-left:24px;line-height:24px;margin-bottom:24px}.rst-content .note .last,.rst-content .attention .last,.rst-content .caution .last,.rst-content .danger .last,.rst-content .error .last,.rst-content .hint .last,.rst-content .important .last,.rst-content .tip .last,.rst-content .warning .last,.rst-content .seealso .last{margin-bottom:0}.rst-content .admonition-title:before{margin-right:4px}.rst-content .admonition table{border-color:rgba(0,0,0,0.1)}.rst-content .admonition table td,.rst-content .admonition table th{background:transparent !important;border-color:rgba(0,0,0,0.1) !important}.rst-content .section ol.loweralpha,.rst-content .section ol.loweralpha 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dt:first-child{margin-top:0}.rst-content dl:not(.docutils) tt{font-weight:bold}.rst-content dl:not(.docutils) tt.descname,.rst-content dl:not(.docutils) tt.descclassname{background-color:transparent;border:none;padding:0;font-size:100% !important}.rst-content dl:not(.docutils) tt.descname{font-weight:bold}.rst-content dl:not(.docutils) .optional{display:inline-block;padding:0 4px;color:#000;font-weight:bold}.rst-content dl:not(.docutils) .property{display:inline-block;padding-right:8px}.rst-content .viewcode-link,.rst-content .viewcode-back{display:inline-block;color:#27ae60;font-size:80%;padding-left:24px}.rst-content .viewcode-back{display:block;float:right}
-
- @media screen and (max-width: 480px){
- .rst-content .sidebar{width:100%}}span[id*='MathJax-Span']{color:#404040}
-/*!
- * HamishW - some CSS for nav bar
- */
-
-.main-nav-bar {
- display:block;
- max-width: 1100px;
- border-bottom: solid;
- border-bottom-width: thin;
- padding-bottom: 10px;
- margin-bottom:20px;
- padding-top: 10px;
-}
-
-
-#menu-options {
- display: table;
- /* background-color:#F8F8F8; */
- /*height: 87px;*/
-
- width: 100%;
-}
-
-#menu-options li {
- display: table-cell;
- /* padding-left: 5px;
- padding-right: 5px; */
- padding-top: 10px;
- padding-bottom: 10px;
- width: 5.0%; /*(100 / numItems)% */
- text-align: center;
- font-weight:bold;
- /*background: #ddd;*/
- white-space: nowrap;
-}
-
-
-
-.navlink-long {
- display:inline-block;
- vertical-align: top;
- padding:5px;
-}
-
-.navlink-short {
- display:none;
- vertical-align: top;
- padding:5px;
-}
-
-
-.footer-nav-bar {
- display:block;
- background-color:#F8F8F8;
- max-width: 1100px;
- /*border-bottom: solid;*/
- padding-bottom: 10px;
- margin-top:15px;
- border-top:solid;
- /* border-top-width:thin; */
-}
-
-.footer-options {
-/* display:block;
-width:inherit;
-font-size:0.8em;
-font-weight:normal;
-*/
-display:block;
-text-align:justify;
-font-size:0.8em;
-width:inherit;
-}
-
-.footer-navlink-long {
- display: inline-block;
- vertical-align: top;
- padding:5px;
-}
-
-.footer-navlink-short {
- display:none;
- padding:5px;
-}
-
-.footer-options:after {
- content: "";
- width: 100%;
- line-height:1px;
- line-spacing:1px;
- display: inline-block;
- }
-
-.copyright-box {
- border-top:solid;
- border-top-width:thin;
- margin-top:10px;
- background-color:#F8F8F8;
- padding-bottom:5px;
-
-}
-
-.copyright-box p {
- font-size:0.8em;
-}
-
-
-
-/* HamishW - Attempt to wrap table columns/remove the "responsive" behaviour on some tables. */
-table.wrap-table-content td, table.wrap-table-content th {
- white-space: normal;
-}
-
-
-
-/* HamishW - add clear markup for external links */
-
-a.external:after {
- content: "";
- display: inline-block;
- background-image: url(data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAAV0lEQVR4Xq2QwQ2AAAwC3cmd2Kk7sRP64CEJ9qOX8OPatMc/QKppnEPhTmJh23CLiwAqIw21CybKQ28qQi37WGFYBJcwfJQpP8LlEHKyZMF0IdmF13zlAjZ/6H4wb+mUAAAAAElFTkSuQmCC);
- background-repeat: no-repeat;
- background-position: right top;
- background-origin: border-box;
- width: 12px;
- height: 16px;
-}
-
-
-/* HamishW - some CSS for the breadcrumb (make elements inline blocks) */
-
-
-.breadcrumb-box {
- margin-top:10px;
- font-size:0.8em;
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+++ /dev/null
-$( document ).ready(function() {
- // Shift nav in mobile when clicking the menu.
- $(document).on('click', "[data-toggle='wy-nav-top']", function() {
- $("[data-toggle='wy-nav-shift']").toggleClass("shift");
- $("[data-toggle='rst-versions']").toggleClass("shift");
- });
- // Close menu when you click a link.
- $(document).on('click', ".wy-menu-vertical .current ul li a", function() {
- $("[data-toggle='wy-nav-shift']").removeClass("shift");
- $("[data-toggle='rst-versions']").toggleClass("shift");
- });
- $(document).on('click', "[data-toggle='rst-current-version']", function() {
- $("[data-toggle='rst-versions']").toggleClass("shift-up");
- });
- // Make tables responsive
- $("table.docutils:not(.field-list)").wrap("<div class='wy-table-responsive'></div>");
-});
-
-window.SphinxRtdTheme = (function (jquery) {
- var stickyNav = (function () {
- var navBar,
- win,
- stickyNavCssClass = 'stickynav',
- applyStickNav = function () {
- if (navBar.height() <= win.height()) {
- navBar.addClass(stickyNavCssClass);
- } else {
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- applyStickNav();
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- init = function () {
- navBar = jquery('nav.wy-nav-side:first');
- win = jquery(window);
- };
- jquery(init);
- return {
- enable : enable
- };
- }());
- return {
- StickyNav : stickyNav
- };
-}($));
+++ /dev/null
-[theme]
-inherit = basic
-stylesheet = css/theme.css
-
-[options]
-typekit_id = hiw1hhg
-analytics_id =
-sticky_navigation = True
-
+++ /dev/null
-{% if READTHEDOCS %}
-{# Add rst-badge after rst-versions for small badge style. #}
- <div class="rst-versions" data-toggle="rst-versions" role="note" aria-label="versions">
- <span class="rst-current-version" data-toggle="rst-current-version">
- <span class="fa fa-book"> Read the Docs</span>
- v: {{ current_version }}
- <span class="fa fa-caret-down"></span>
- </span>
- <div class="rst-other-versions">
- <dl>
- <dt>Versions</dt>
- {% for slug, url in versions %}
- <dd><a href="{{ url }}">{{ slug }}</a></dd>
- {% endfor %}
- </dl>
- <dl>
- <dt>Downloads</dt>
- {% for type, url in downloads %}
- <dd><a href="{{ url }}">{{ type }}</a></dd>
- {% endfor %}
- </dl>
- <dl>
- <dt>On Read the Docs</dt>
- <dd>
- <a href="//{{ PRODUCTION_DOMAIN }}/projects/{{ slug }}/?fromdocs={{ slug }}">Project Home</a>
- </dd>
- <dd>
- <a href="//{{ PRODUCTION_DOMAIN }}/builds/{{ slug }}/?fromdocs={{ slug }}">Builds</a>
- </dd>
- </dl>
- <hr/>
- Free document hosting provided by <a href="http://www.readthedocs.org">Read the Docs</a>.
-
- </div>
- </div>
-{% endif %}
-
+++ /dev/null
-# -*- coding: utf-8 -*-
-#
-# LiteEth documentation build configuration file, created by
-# sphinx-quickstart on Tue Jul 01 09:20:29 2014.
-#
-# This file is execfile()d with the current directory set to its
-# containing dir.
-#
-# Note that not all possible configuration values are present in this
-# autogenerated file.
-#
-# All configuration values have a default; values that are commented out
-# serve to show the default.
-
-import sys
-import os
-
-
-# At the top. #HamishW https://pypi.python.org/pypi/sphinx-bootstrap-theme/ ...
-#import sphinx_bootstrap_theme
-
-
-# At the top. #HamishW http://sphinx-better-theme.readthedocs.org/en/latest/installation.html easy_install sphinx_better_theme
-#from better import better_theme_path
-#html_theme_path = [better_theme_path]
-
-
-# At the top. #HamishW https://github.com/snide/sphinx_rtd_theme easy_install sphinx_rtd_theme
-#import sphinx_rtd_theme
-#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
-
-html_theme_path = ['_themes',]
-
-
-
-
-
-
-
-# If extensions (or modules to document with autodoc) are in another directory,
-# add these directories to sys.path here. If the directory is relative to the
-# documentation root, use os.path.abspath to make it absolute, like shown here.
-#sys.path.insert(0, os.path.abspath('.'))
-
-
-# -- General configuration ------------------------------------------------
-
-# If your documentation needs a minimal Sphinx version, state it here.
-#needs_sphinx = '1.0'
-
-# Add any Sphinx extension module names here, as strings. They can be
-# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
-# ones.
-extensions = [
- 'sphinx.ext.autodoc',
- 'sphinx.ext.doctest',
- 'sphinx.ext.intersphinx',
- 'sphinx.ext.todo',
- 'sphinx.ext.coverage',
- 'sphinx.ext.ifconfig',
- 'sphinx.ext.viewcode',
- # 'breathe', #added by HamishW
-]
-
-
-#Build "Todo" notes into the source
-#todo_include_todos = 'True'
-
-# Add any paths that contain templates here, relative to this directory.
-templates_path = ['_templates']
-
-# The suffix of source filenames.
-source_suffix = '.rst'
-
-# The encoding of source files.
-#source_encoding = 'utf-8-sig'
-
-# The master toctree document.
-master_doc = 'index'
-
-# General information about the project.
-project = u'LiteEth'
-copyright = u'2015, '
- # Note, theme was modified to allow this to display (fix breaks the translation code, which was breaking the above link and rendering it as text).
- # Also so I could link to specific copyright page.
-
-
-# The version info for the project you're documenting, acts as replacement for
-# |version| and |release|, also used in various other places throughout the
-# built documents.
-#
-
-liteeth_version = open(os.path.abspath(os.path.join(os.path.dirname(os.path.dirname(os.path.dirname(__file__))), 'liteeth-version.txt'))).read().strip()
-
-# The short X.Y version.
-version = liteeth_version[:liteeth_version.rindex('.')]
-# The full version, including alpha/beta/rc tags.
-release = liteeth_version
-
-# The language for content autogenerated by Sphinx. Refer to documentation
-# for a list of supported languages.
-#language = None
-
-# There are two options for replacing |today|: either, you set today to some
-# non-false value, then it is used:
-#today = ''
-# Else, today_fmt is used as the format for a strftime call.
-#today_fmt = '%B %d, %Y'
-
-# List of patterns, relative to source directory, that match files and
-# directories to ignore when looking for source files.
-exclude_patterns = []
-
-# The reST default role (used for this markup: `text`) to use for all
-# documents.
-#default_role = None
-
-# If true, '()' will be appended to :func: etc. cross-reference text.
-#add_function_parentheses = True
-
-# If true, the current module name will be prepended to all description
-# unit titles (such as .. function::).
-#add_module_names = True
-
-# If true, sectionauthor and moduleauthor directives will be shown in the
-# output. They are ignored by default.
-#show_authors = False
-
-# The name of the Pygments (syntax highlighting) style to use.
-pygments_style = 'sphinx'
-
-# A list of ignored prefixes for module index sorting.
-#modindex_common_prefix = []
-
-# If true, keep warnings as "system message" paragraphs in the built documents.
-#keep_warnings = False
-
-
-# -- Options for HTML output ----------------------------------------------
-
-# The theme to use for HTML and HTML Help pages. See the documentation for
-# a list of builtin themes.
-#html_theme = 'default'
-#html_theme = 'sphinxdoc'
-#html_theme = 'agogo' #like this
-#html_theme = 'scrolls'
-#html_theme = 'bootstrap'
-#html_theme_path = sphinx_bootstrap_theme.get_html_theme_path()
-#html_theme = 'better'
-#html_theme = 'pyramid'
-#html_theme = 'nature'
-#html_theme = 'haiku'
-#html_theme = "sphinx_rtd_theme"
-html_theme = "enjoydigital_sphinx_rtd_theme"
-
-# Theme options are theme-specific and customize the look and feel of a theme
-# further. For a list of options available for each theme, see the
-# documentation.
-#html_theme_options = {
-# "rightsidebar": "true",
-# "relbarbgcolor": "black"
-#}
-
-
-# Add any paths that contain custom themes here, relative to this directory.
-#html_theme_path = []
-
-# The name for this set of Sphinx documents. If None, it defaults to
-# "<project> v<release> documentation".
-#html_title = None
-
-# A shorter title for the navigation bar. Default is the same as html_title.
-#html_short_title = None
-
-# The name of an image file (relative to this directory) to place at the top
-# of the sidebar.
-html_logo = '_static/LiteEth_logo_full.png'
-
-
-# The name of an image file (within the static path) to use as favicon of the
-# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
-# pixels large.
-html_favicon = 'liteeth.ico'
-
-# Add any paths that contain custom static files (such as style sheets) here,
-# relative to this directory. They are copied after the builtin static files,
-# so a file named "default.css" will overwrite the builtin "default.css".
-html_static_path = ['_static']
-
-# Add any extra paths that contain custom files (such as robots.txt or
-# .htaccess) here, relative to this directory. These files are copied
-# directly to the root of the documentation.
-#html_extra_path = []
-
-# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,
-# using the given strftime format.
-#html_last_updated_fmt = '%b %d, %Y'
-
-# If true, SmartyPants will be used to convert quotes and dashes to
-# typographically correct entities.
-#html_use_smartypants = True
-
-# Custom sidebar templates, maps document names to template names.
-#html_sidebars = {}
-
-# Additional templates that should be rendered to pages, maps page names to
-# template names.
-#html_additional_pages = {}
-
-# If false, no module index is generated.
-#html_domain_indices = True
-
-# If false, no index is generated.
-#html_use_index = True
-
-# If true, the index is split into individual pages for each letter.
-#html_split_index = False
-
-# If true, links to the reST sources are added to the pages.
-#html_show_sourcelink = True
-
-# If true, "Created using Sphinx" is shown in the HTML footer. Default is True.
-#html_show_sphinx = True
-
-# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True.
-#html_show_copyright = True
-
-# If true, an OpenSearch description file will be output, and all pages will
-# contain a <link> tag referring to it. The value of this option must be the
-# base URL from which the finished HTML is served.
-#html_use_opensearch = ''
-
-# This is the file name suffix for HTML files (e.g. ".xhtml").
-#html_file_suffix = None
-
-# Output file base name for HTML help builder.
-htmlhelp_basename = 'LiteEthdoc'
-
-
-# -- Options for LaTeX output ---------------------------------------------
-
-latex_elements = {
-# The paper size ('letterpaper' or 'a4paper').
-#'papersize': 'letterpaper',
-
-# The font size ('10pt', '11pt' or '12pt').
-#'pointsize': '10pt',
-
-# Additional stuff for the LaTeX preamble.
-#'preamble': '',
-}
-
-# Grouping the document tree into LaTeX files. List of tuples
-# (source start file, target name, title,
-# author, documentclass [howto, manual, or own class]).
-latex_documents = [
- ('index', 'LiteEth.tex', u'LiteEth Documentation',
- u'Kermarrec Florent', 'manual'),
-]
-
-# The name of an image file (relative to this directory) to place at the top of
-# the title page.
-#latex_logo = None
-
-# For "manual" documents, if this is true, then toplevel headings are parts,
-# not chapters.
-#latex_use_parts = False
-
-# If true, show page references after internal links.
-#latex_show_pagerefs = False
-
-# If true, show URL addresses after external links.
-#latex_show_urls = False
-
-# Documents to append as an appendix to all manuals.
-#latex_appendices = []
-
-# If false, no module index is generated.
-#latex_domain_indices = True
-
-
-# -- Options for manual page output ---------------------------------------
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
- ('index', 'liteeth', u'LiteEth Documentation',
- [u'Florent Kermarrec'], 1)
-]
-
-# If true, show URL addresses after external links.
-#man_show_urls = False
-
-
-# -- Options for Texinfo output -------------------------------------------
-
-# Grouping the document tree into Texinfo files. List of tuples
-# (source start file, target name, title, author,
-# dir menu entry, description, category)
-texinfo_documents = [
- ('index', 'LiteEth', u'LiteEth Documentation',
- u'Florent Kermarrec', 'LiteEth', 'One line description of project.',
- 'Miscellaneous'),
-]
-
-# Documents to append as an appendix to all manuals.
-#texinfo_appendices = []
-
-# If false, no module index is generated.
-#texinfo_domain_indices = True
-
-# How to display URL addresses: 'footnote', 'no', or 'inline'.
-#texinfo_show_urls = 'footnote'
-
-# If true, do not generate a @detailmenu in the "Top" node's menu.
-#texinfo_no_detailmenu = False
-
-
-# -- Options for Epub output ----------------------------------------------
-
-# Bibliographic Dublin Core info.
-epub_title = u'LiteEth'
-epub_author = u'Florent Kermarrec'
-epub_publisher = u'Florent Kermarrec'
-epub_copyright = u'2015, LiteEth Contributors'
-
-# The basename for the epub file. It defaults to the project name.
-#epub_basename = u'LiteEth'
-
-# The HTML theme for the epub output. Since the default themes are not optimized
-# for small screen space, using the same theme for HTML and epub output is
-# usually not wise. This defaults to 'epub', a theme designed to save visual
-# space.
-#epub_theme = 'epub'
-
-# The language of the text. It defaults to the language option
-# or en if the language is not set.
-#epub_language = ''
-
-# The scheme of the identifier. Typical schemes are ISBN or URL.
-#epub_scheme = ''
-
-# The unique identifier of the text. This can be a ISBN number
-# or the project homepage.
-#epub_identifier = ''
-
-# A unique identification for the text.
-#epub_uid = ''
-
-# A tuple containing the cover image and cover page html template filenames.
-#epub_cover = ()
-
-# A sequence of (type, uri, title) tuples for the guide element of content.opf.
-#epub_guide = ()
-
-# HTML files that should be inserted before the pages created by sphinx.
-# The format is a list of tuples containing the path and title.
-#epub_pre_files = []
-
-# HTML files shat should be inserted after the pages created by sphinx.
-# The format is a list of tuples containing the path and title.
-#epub_post_files = []
-
-# A list of files that should not be packed into the epub file.
-epub_exclude_files = ['search.html']
-
-# The depth of the table of contents in toc.ncx.
-#epub_tocdepth = 3
-
-# Allow duplicate toc entries.
-#epub_tocdup = True
-
-# Choose between 'default' and 'includehidden'.
-#epub_tocscope = 'default'
-
-# Fix unsupported image types using the PIL.
-#epub_fix_images = False
-
-# Scale large images.
-#epub_max_image_width = 0
-
-# How to display URL addresses: 'footnote', 'no', or 'inline'.
-#epub_show_urls = 'inline'
-
-# If false, no index is generated.
-#epub_use_index = True
-
-
-# Example configuration for intersphinx: refer to the Python standard library.
-intersphinx_mapping = {'http://docs.python.org/': None}
-
-# HamishW - set highlighting language.
-highlight_language = 'cpp'
-
-# HamishW - set domain (cpp)
-primary_domain = 'cpp'
-
-# HamishW - tell Breathe about projects. Breathe is tool to convert Doxygen to Python objects, for import into Sphinx.
-#breathe_projects = { "myproject": "/home/me/docproj/doxyxml/", "nutshell":"./headers/xml/", }
-# HamishW - Specify a default project:
-#breathe_default_project = "nutshell"
-
+++ /dev/null
-.. _core-index:
-
-========================
-Core
-========================
-.. note::
- Please contribute to this document, or support us financially to write it.
\ No newline at end of file
+++ /dev/null
-.. _frontend-index:
-
-========================
-Frontend
-========================
-.. note::
- Please contribute to this document, or support us financially to write it.
+++ /dev/null
-.. _FAQ:
-
-===
-FAQ
-===
-.. note::
- Please contribute to this document.
+++ /dev/null
-.. _bug-reports:
-
-=============
-Bug Reporting
-=============
-- send us feedback and suggestions for improvements
-- send us bug reports when something goes wrong
-- send us the modifications and improvements you have done to LiteEth.
-The use of "git format-patch" is recommended. If your submission is large and
-complex and/or you are not sure how to proceed, feel free to discuss with us
-about it.
\ No newline at end of file
+++ /dev/null
-.. _sdk-download-and-install:
-
-====================
-Download and install
-====================
-Please follow Getting started section of LiteEth README_.
-
-.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/com/liteeth/README
+++ /dev/null
-.. _getting-started-index:
-
-===============
-Getting Started
-===============
-
-Now you know why LiteEth is :ref:`core for you <about>`, it's time to *get started*.
-
-This section provides a walk-through of :ref:`downloading and installing the tools`.
-
-.. toctree::
- :maxdepth: 1
-
- downloads
- FAQ
- bug_reports
-
+++ /dev/null
-.. _documentation-home:
-
-========================
-LiteEth Documentation
-========================
-
-This comprehensive documentation set contains everything you need to know to use LiteEth and integrate it in your design.
-
-**Getting started:**
-
-- :ref:`intro-index` explains what LiteEth does, why it is needed, its limitations and its licensing. It will help you understand whether LiteEth is the right core for you.
-- :ref:`getting-started-index` walks you through downloading, installing and using the LiteEth core.
-
-**LiteEth Internals:**
-
-- :ref:`core-index` describes core building blocks.
-- :ref:`frontend-index` describes core building blocks.
-
-The full hierarchy of articles, opened to the second level, is shown below.
-
-.. toctree::
- :maxdepth: 2
-
- intro/index
- getting_started/index
- core/index
- frontend/index
+++ /dev/null
-.. _about:
-
-================
-About LiteEth
-================
-
-LiteEth provides a small footprint and configurable Ethernet core.
-
-LiteEth is part of MiSoC libraries whose aims are to lower entry level of
-complex FPGA cores by providing simple, elegant and efficient implementations
-ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
-
-The core uses simple and specific streaming buses and will provides in the future
-adapters to use standardized AXI or Avalon-ST streaming buses.
-
-Since Python is used to describe the HDL, the core is highly and easily
-configurable.
-
-LiteEth uses technologies developed in partnership with M-Labs Ltd:
- - Migen enables generating HDL with Python in an efficient way.
- - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
-
-LiteEth can be used as MiSoC library or can be integrated with your standard
-design flow by generating the verilog rtl that you will use as a standard core.
-
-.. _about-toolchain:
-
-Features
-========
-- Ethernet MAC with various interfaces and various PHYs (GMII, MII, Loopback)
-- Hardware UDP/IP stack with ARP and ICMP
-
-Possibles improvements
-======================
-- add standardized interfaces (AXI, Avalon-ST)
-- add DMA interface to MAC
-- add hardware Etherbone support
-- add RGMII/SGMII PHYs
-- ... See below Support and Consulting :)
-
-Support and Consulting
-======================
-We love open-source hardware and like sharing our designs with others.
-
-LiteEth is mainly developed and maintained by EnjoyDigital.
-
-If you would like to know more about LiteEth or if you are already a happy user
-and would like to extend it for your needs, EnjoyDigital can provide standard
-commercial support as well as consulting services.
-
-So feel free to contact us, we'd love to work with you! (and eventually shorten
-the list of the possible improvements :)
-
-Contact
-=======
-E-mail: florent [AT] enjoy-digital.fr
-
-
+++ /dev/null
-.. _community:
-
-=========
-Community
-=========
+++ /dev/null
-.. _intro-index:
-
-======================
-Introducing LiteEth
-======================
-
-This section explains what LiteEth does, why it is needed, its limitations and its licensing. After reading, you will understand whether LiteEth is the right core for you, and where to go if you have :ref:`further questions <community>`.
-
-.. toctree::
- :maxdepth: 1
-
- about
- license
- release_notes
- talks_and_publications
+++ /dev/null
-.. _license:
-
-===================
-Open Source License
-===================
-
-LiteEth is released under the very permissive two-clause BSD license. Under the
-terms of this license, you are authorized to use LiteEth for closed-source
-proprietary designs.
-Even though we do not require you to do so, those things are awesome, so please
-do them if possible:
- - tell us that you are using LiteEth
- - cite LiteEth in publications related to research it has helped
- - send us feedback and suggestions for improvements
- - send us bug reports when something goes wrong
- - send us the modifications and improvements you have done to LiteEth.
-
-::
-
- Unless otherwise noted, LiteEth is copyright (C) 2015 Florent Kermarrec.
-
- Redistribution and use in source and binary forms, with or without modification,
- are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
- Other authors retain ownership of their contributions. If a submission can
- reasonably be considered independently copyrightable, it's yours and we
- encourage you to claim it with appropriate copyright notices. This submission
- then falls under the "otherwise noted" category. All submissions are strongly
- encouraged to use the two-clause BSD license reproduced above.
+++ /dev/null
-.. _release-notes:
-
-=============
-Release Notes
-=============
-
-.. _ChangeLog:
-
-ChangeLog
-=========
-0.9.0:
- - First 0.9.0 release supporting hardware UDP/IP stack with ICMP and ARP.
-
+++ /dev/null
-.. _talks-and-publications:
-
-======================
-Talks and Publications
-======================
-
-- Migen / MiSoC documentation:
- - `User guide <http://m-labs.hk/migen.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
- - `Tutorial: An introduction to Migen <http://m-labs.hk/migen-tutorial.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
-
-- Migen / MiSoC presentations:
- - `Lecture slides <http://m-labs.hk/migen-slides.pdf>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
- - `EHSM 2012 presentation <https://www.youtube.com/watch?v=yxKMsAi_WEA>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
- - `ORCONF2014 <https://www.youtube.com/watch?v=AfEPbw4nREo>`_ (`fallen <https://github.com/fallen>`_)
+++ /dev/null
-<img alt="./_static/LiteEth_logo_full.png" src="_static/LiteEth_logo_full.png">
-
-<h3>A small footprint and configurable Ethernet core with UDP/IP hw stack and Etherbone frontend</b>.</h3>
-
-<div class="container" style="width:100%;margin-bottom:10px;">
-
- <div class="one-third-container" style="width:32%; display:inline-block;">
- <div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
- <div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
- <div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteEth footprint is really small!</p></div>
- </div>
- </div>
- <div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
- <div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
- <div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
- <div class="signpost-body" style=""><p>LiteEth generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit user's needs! (Implement only the layers you need, store data in RAM or DMA, use full-hardware UDP/IP stack and so on...)</p></div>
- </div>
- </div>
- <div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
- <div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
- <div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
- <div class="signpost-body" style=""><p>LiteEth can target all FPGAs regardless of the vendor, you only have to ensure that your PHY is available!</p></div>
- </div>
- </div>
-</div>
-
+++ /dev/null
-.. title:: Main
-
-.. _home-page:
-
-.. raw:: html
- :file: home_page_layout.html
-
-
------
-
-News
-====
-
-- First 0.9.0 release supporting hardware UDP/IP stack with ICMP and ARP.
-
-.. toctree::
- :hidden:
-
- docs/intro/index
- docs/getting_started/index
- docs/core/index
- docs/frontend/index
- docs/site/about
-
+++ /dev/null
-#!/usr/bin/env python3
-
-import sys
-import os
-import argparse
-import subprocess
-import struct
-import importlib
-
-from mibuild.tools import write_to_file
-from migen.util.misc import autotype
-from migen.fhdl import verilog, edif
-from migen.fhdl.structure import _Fragment
-from migen.bank.description import CSRStatus
-from mibuild import tools
-from mibuild.xilinx.common import *
-
-from misoclib.soc import cpuif
-from misoclib.com.liteeth.common import *
-
-
-def _import(default, name):
- return importlib.import_module(default + "." + name)
-
-
-def _get_args():
- parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
- description="""\
-LiteEth - based on Migen.
-
-This program builds and/or loads LiteEth components.
-One or several actions can be specified:
-
-clean delete previous build(s).
-build-rtl build verilog rtl.
-build-bitstream build-bitstream build FPGA bitstream.
-build-csr-csv save CSR map into CSV file.
-
-load-bitstream load bitstream into volatile storage.
-
-all clean, build-csr-csv, build-bitstream, load-bitstream.
-""")
-
- parser.add_argument("-t", "--target", default="base", help="Core type to build")
- parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
- parser.add_argument("-p", "--platform", default=None, help="platform to build for")
- parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
- parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
- parser.add_argument("-Ob", "--build-option", default=[], nargs=2, action="append", help="set build option")
- parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
-
- parser.add_argument("action", nargs="+", help="specify an action")
-
- return parser.parse_args()
-
-# Note: misoclib need to be installed as a python library
-
-if __name__ == "__main__":
- args = _get_args()
-
- # create top-level Core object
- target_module = _import("targets", args.target)
- if args.sub_target:
- top_class = getattr(target_module, args.sub_target)
- else:
- top_class = target_module.default_subtarget
-
- if args.platform is None:
- if hasattr(top_class, "default_platform"):
- platform_name = top_class.default_platform
- else:
- raise ValueError("Target has no default platform, specify a platform with -p your_platform")
- else:
- platform_name = args.platform
- platform_module = _import("mibuild.platforms", platform_name)
- platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
- platform = platform_module.Platform(**platform_kwargs)
-
- build_name = top_class.__name__.lower() + "-" + platform_name
- top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
- soc = top_class(platform, **top_kwargs)
- soc.finalize()
- memory_regions = soc.get_memory_regions()
- csr_regions = soc.get_csr_regions()
-
- # decode actions
- action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
- actions = {k: False for k in action_list}
- for action in args.action:
- if action in actions:
- actions[action] = True
- else:
- print("Unknown action: "+action+". Valid actions are:")
- for a in action_list:
- print(" "+a)
- sys.exit(1)
-
- print("""
- __ _ __ ______ __
- / / (_) /____ / __/ /_/ /
- / /__/ / __/ -_) _// __/ _ \\
- /____/_/\__/\__/___/\__/_//_/
-
- A small footprint and configurable Ethernet
- core powered by Migen
-====== Building options: ======
-Platform: {}
-Target: {}
-Subtarget: {}
-System Clk: {} MHz
-===============================""".format(
- platform_name,
- args.target,
- top_class.__name__,
- soc.clk_freq/1000000
- )
-)
-
- # dependencies
- if actions["all"]:
- actions["build-csr-csv"] = True
- actions["build-bitstream"] = True
- actions["load-bitstream"] = True
-
- if actions["build-bitstream"]:
- actions["build-csr-csv"] = True
- actions["build-bitstream"] = True
- actions["load-bitstream"] = True
-
- if actions["clean"]:
- subprocess.call(["rm", "-rf", "build/*"])
-
- if actions["build-csr-csv"]:
- csr_csv = cpuif.get_csr_csv(csr_regions)
- write_to_file(args.csr_csv, csr_csv)
-
- if actions["build-bitstream"]:
- build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
- vns = platform.build(soc, build_name=build_name, **build_kwargs)
- if hasattr(soc, "do_exit") and vns is not None:
- if hasattr(soc.do_exit, '__call__'):
- soc.do_exit(vns)
-
- if actions["load-bitstream"]:
- prog = platform.create_programmer()
- prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
+++ /dev/null
-from migen.bus import wishbone
-from migen.genlib.io import CRG
-from migen.fhdl.specials import Keep
-from mibuild.xilinx.vivado import XilinxVivadoToolchain
-
-from misoclib.soc import SoC
-from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.frontend.la import LiteScopeLA
-from misoclib.tools.litescope.core.port import LiteScopeTerm
-
-from misoclib.com.uart.bridge import UARTWishboneBridge
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.core import LiteEthUDPIPCore
-
-
-class BaseSoC(SoC):
- csr_map = {
- "phy": 11,
- "core": 12
- }
- csr_map.update(SoC.csr_map)
- def __init__(self, platform, clk_freq=166*1000000,
- mac_address=0x10e2d5000000,
- ip_address="192.168.0.42"):
- clk_freq = int((1/(platform.default_clk_period))*1000000000)
- SoC.__init__(self, platform, clk_freq,
- cpu_type="none",
- with_csr=True, csr_data_width=32,
- with_uart=False,
- with_identifier=True,
- with_timer=False
- )
- self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
- self.add_wb_master(self.cpu_or_bridge.wishbone)
- self.submodules.crg = CRG(platform.request(platform.default_clk_name))
-
- # wishbone SRAM (to test Wishbone over UART and Etherbone)
- self.submodules.sram = wishbone.SRAM(1024)
- self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
-
- # ethernet PHY and UDP/IP stack
- self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq)
- self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)
-
- if isinstance(platform.toolchain, XilinxVivadoToolchain):
- self.specials += [
- Keep(self.crg.cd_sys.clk),
- Keep(self.phy.crg.cd_eth_rx.clk),
- Keep(self.phy.crg.cd_eth_tx.clk)
- ]
- platform.add_platform_command("""
-create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
-create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
-create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
-set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
-set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
-set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
-set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
-""")
-
-
-class BaseSoCDevel(BaseSoC):
- csr_map = {
- "la": 20
- }
- csr_map.update(BaseSoC.csr_map)
- def __init__(self, platform):
- BaseSoC.__init__(self, platform)
-
- self.core_icmp_rx_fsm_state = Signal(4)
- self.core_icmp_tx_fsm_state = Signal(4)
- self.core_udp_rx_fsm_state = Signal(4)
- self.core_udp_tx_fsm_state = Signal(4)
- self.core_ip_rx_fsm_state = Signal(4)
- self.core_ip_tx_fsm_state = Signal(4)
- self.core_arp_rx_fsm_state = Signal(4)
- self.core_arp_tx_fsm_state = Signal(4)
- self.core_arp_table_fsm_state = Signal(4)
-
- debug = (
- # MAC interface
- self.core.mac.core.sink.stb,
- self.core.mac.core.sink.sop,
- self.core.mac.core.sink.eop,
- self.core.mac.core.sink.ack,
- self.core.mac.core.sink.data,
-
- self.core.mac.core.source.stb,
- self.core.mac.core.source.sop,
- self.core.mac.core.source.eop,
- self.core.mac.core.source.ack,
- self.core.mac.core.source.data,
-
- # ICMP interface
- self.core.icmp.echo.sink.stb,
- self.core.icmp.echo.sink.sop,
- self.core.icmp.echo.sink.eop,
- self.core.icmp.echo.sink.ack,
- self.core.icmp.echo.sink.data,
-
- self.core.icmp.echo.source.stb,
- self.core.icmp.echo.source.sop,
- self.core.icmp.echo.source.eop,
- self.core.icmp.echo.source.ack,
- self.core.icmp.echo.source.data,
-
- # IP interface
- self.core.ip.crossbar.master.sink.stb,
- self.core.ip.crossbar.master.sink.sop,
- self.core.ip.crossbar.master.sink.eop,
- self.core.ip.crossbar.master.sink.ack,
- self.core.ip.crossbar.master.sink.data,
- self.core.ip.crossbar.master.sink.ip_address,
- self.core.ip.crossbar.master.sink.protocol,
-
- # State machines
- self.core_icmp_rx_fsm_state,
- self.core_icmp_tx_fsm_state,
-
- self.core_arp_rx_fsm_state,
- self.core_arp_tx_fsm_state,
- self.core_arp_table_fsm_state,
-
- self.core_ip_rx_fsm_state,
- self.core_ip_tx_fsm_state,
-
- self.core_udp_rx_fsm_state,
- self.core_udp_tx_fsm_state
- )
- self.submodules.la = LiteScopeLA(debug, 4096)
- self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-
- def do_finalize(self):
- BaseSoC.do_finalize(self)
- self.comb += [
- self.core_icmp_rx_fsm_state.eq(self.core.icmp.rx.fsm.state),
- self.core_icmp_tx_fsm_state.eq(self.core.icmp.tx.fsm.state),
-
- self.core_arp_rx_fsm_state.eq(self.core.arp.rx.fsm.state),
- self.core_arp_tx_fsm_state.eq(self.core.arp.tx.fsm.state),
- self.core_arp_table_fsm_state.eq(self.core.arp.table.fsm.state),
-
- self.core_ip_rx_fsm_state.eq(self.core.ip.rx.fsm.state),
- self.core_ip_tx_fsm_state.eq(self.core.ip.tx.fsm.state),
-
- self.core_udp_rx_fsm_state.eq(self.core.udp.rx.fsm.state),
- self.core_udp_tx_fsm_state.eq(self.core.udp.tx.fsm.state)
- ]
-
- def do_exit(self, vns):
- self.la.export(vns, "test/la.csv")
-
-default_subtarget = BaseSoC
+++ /dev/null
-from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.frontend.la import LiteScopeLA
-from misoclib.tools.litescope.core.port import LiteScopeTerm
-
-from misoclib.com.liteeth.common import *
-
-from targets.base import BaseSoC
-from misoclib.com.liteeth.frontend.etherbone import LiteEthEtherbone
-
-
-class EtherboneSoC(BaseSoC):
- default_platform = "kc705"
- def __init__(self, platform):
- BaseSoC.__init__(self, platform,
- mac_address=0x10e2d5000000,
- ip_address="192.168.0.42")
- self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
- self.add_wb_master(self.etherbone.master.bus)
-
-
-class EtherboneSoCDevel(EtherboneSoC):
- csr_map = {
- "la": 20
- }
- csr_map.update(EtherboneSoC.csr_map)
- def __init__(self, platform):
- EtherboneSoC.__init__(self, platform)
- debug = (
- # mmap stream from HOST
- self.etherbone.master.sink.stb,
- self.etherbone.master.sink.sop,
- self.etherbone.master.sink.eop,
- self.etherbone.master.sink.ack,
- self.etherbone.master.sink.we,
- self.etherbone.master.sink.count,
- self.etherbone.master.sink.base_addr,
- self.etherbone.master.sink.be,
- self.etherbone.master.sink.addr,
- self.etherbone.master.sink.data,
-
- # mmap stream to HOST
- self.etherbone.master.source.stb,
- self.etherbone.master.source.sop,
- self.etherbone.master.source.eop,
- self.etherbone.master.source.ack,
- self.etherbone.master.source.we,
- self.etherbone.master.source.count,
- self.etherbone.master.source.base_addr,
- self.etherbone.master.source.be,
- self.etherbone.master.source.addr,
- self.etherbone.master.source.data,
-
- # etherbone wishbone master
- self.etherbone.master.bus.dat_w,
- self.etherbone.master.bus.dat_r,
- self.etherbone.master.bus.adr,
- self.etherbone.master.bus.sel,
- self.etherbone.master.bus.cyc,
- self.etherbone.master.bus.stb,
- self.etherbone.master.bus.ack,
- self.etherbone.master.bus.we,
- self.etherbone.master.bus.cti,
- self.etherbone.master.bus.bte,
- self.etherbone.master.bus.err
- )
- self.submodules.la = LiteScopeLA(debug, 4096)
- self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-
- def do_exit(self, vns):
- self.la.export(vns, "test/la.csv")
-
-default_subtarget = EtherboneSoC
+++ /dev/null
-from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.frontend.la import LiteScopeLA
-from misoclib.tools.litescope.core.port import LiteScopeTerm
-
-from misoclib.com.liteeth.common import *
-
-from targets.base import BaseSoC
-from misoclib.com.liteeth.frontend.tty import LiteEthTTY
-
-
-class TTYSoC(BaseSoC):
- default_platform = "kc705"
- def __init__(self, platform):
- BaseSoC.__init__(self, platform,
- mac_address=0x10e2d5000000,
- ip_address="192.168.0.42")
- self.submodules.tty = LiteEthTTY(self.core.udp, convert_ip("192.168.0.14"), 10000)
- self.comb += Record.connect(self.tty.source, self.tty.sink)
-
-
-class TTYSoCDevel(TTYSoC):
- csr_map = {
- "la": 20
- }
- csr_map.update(TTYSoC.csr_map)
- def __init__(self, platform):
- TTYSoC.__init__(self, platform)
- debug = (
- self.tty.sink.stb,
- self.tty.sink.ack,
- self.tty.sink.data,
-
- self.tty.source.stb,
- self.tty.source.ack,
- self.tty.source.data
- )
- self.submodules.la = LiteScopeLA(debug, 4096)
- self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-
- def do_exit(self, vns):
- self.la.export(vns, "test/la.csv")
-
-default_subtarget = TTYSoC
+++ /dev/null
-from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.frontend.la import LiteScopeLA
-from misoclib.tools.litescope.core.port import LiteScopeTerm
-
-from misoclib.com.liteeth.common import *
-
-from targets.base import BaseSoC
-
-
-class UDPSoC(BaseSoC):
- default_platform = "kc705"
- def __init__(self, platform):
- BaseSoC.__init__(self, platform,
- mac_address=0x10e2d5000000,
- ip_address="192.168.0.42")
-
- # add udp loopback on port 6000 with dw=8
- self.add_udp_loopback(6000, 8, 8192, "loopback_8")
- # add udp loopback on port 8000 with dw=32
- self.add_udp_loopback(8000, 32, 8192, "loopback_32")
-
- def add_udp_loopback(self, port, dw, depth, name=None):
- port = self.core.udp.crossbar.get_port(port, dw)
- buf = Buffer(eth_udp_user_description(dw), depth//(dw//8), 8)
- if name is None:
- self.submodules += buf
- else:
- setattr(self.submodules, name, buf)
- self.comb += Port.connect(port, buf)
-
-
-class UDPSoCDevel(UDPSoC):
- csr_map = {
- "la": 20
- }
- csr_map.update(UDPSoC.csr_map)
- def __init__(self, platform):
- UDPSoC.__init__(self, platform)
- debug = (
- self.loopback_8.sink.stb,
- self.loopback_8.sink.sop,
- self.loopback_8.sink.eop,
- self.loopback_8.sink.ack,
- self.loopback_8.sink.data,
-
- self.loopback_8.source.stb,
- self.loopback_8.source.sop,
- self.loopback_8.source.eop,
- self.loopback_8.source.ack,
- self.loopback_8.source.data,
-
- self.loopback_32.sink.stb,
- self.loopback_32.sink.sop,
- self.loopback_32.sink.eop,
- self.loopback_32.sink.ack,
- self.loopback_32.sink.data,
-
- self.loopback_32.source.stb,
- self.loopback_32.source.sop,
- self.loopback_32.source.eop,
- self.loopback_32.source.ack,
- self.loopback_32.source.data
- )
- self.submodules.la = LiteScopeLA(debug, 4096)
- self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-
- def do_exit(self, vns):
- self.la.export(vns, "test/la.csv")
-
-default_subtarget = UDPSoC
+++ /dev/null
-#!/usr/bin/env python3
-import argparse
-import importlib
-
-
-def _get_args():
- parser = argparse.ArgumentParser()
- parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
- parser.add_argument("--port", default="2", help="UART port")
- parser.add_argument("--baudrate", default=115200, help="UART baudrate")
- parser.add_argument("--ip_address", default="192.168.0.42", help="Etherbone IP address")
- parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
- parser.add_argument("--busword", default=32, help="CSR busword")
-
- parser.add_argument("test", nargs="+", help="specify a test")
-
- return parser.parse_args()
-
-if __name__ == "__main__":
- args = _get_args()
- if args.bridge == "uart":
- from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
- port = args.port if not args.port.isdigit() else int(args.port)
- wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
- elif args.bridge == "etherbone":
- from misoclib.com.liteeth.software.wishbone import LiteETHWishboneBridgeDriver
- wb = LiteETHWishboneBridgeDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
- else:
- ValueError("Invalid bridge {}".format(args.bridge))
-
- def _import(name):
- return importlib.import_module(name)
-
- for test in args.test:
- t = _import(test)
- t.main(wb)
+++ /dev/null
-import socket
-import time
-from misoclib.com.liteeth.test.model.etherbone import *
-
-SRAM_BASE = 0x02000000
-
-import socket
-
-
-def main(wb):
- sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
-
- # test probe
- packet = EtherbonePacket()
- packet.pf = 1
- packet.encode()
- sock.sendto(bytes(packet), ("192.168.0.42", 20000))
- time.sleep(0.01)
-
- # test writes
- writes_datas = [j for j in range(16)]
- writes = EtherboneWrites(base_addr=SRAM_BASE, datas=writes_datas)
- record = EtherboneRecord()
- record.writes = writes
- record.reads = None
- record.bca = 0
- record.rca = 0
- record.rff = 0
- record.cyc = 0
- record.wca = 0
- record.wff = 0
- record.byte_enable = 0xf
- record.wcount = len(writes_datas)
- record.rcount = 0
-
- packet = EtherbonePacket()
- packet.records = [record]
- packet.encode()
- sock.sendto(bytes(packet), ("192.168.0.42", 20000))
- time.sleep(0.01)
-
- # test reads
- reads_addrs = [SRAM_BASE+4*j for j in range(16)]
- reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
- record = EtherboneRecord()
- record.writes = None
- record.reads = reads
- record.bca = 0
- record.rca = 0
- record.rff = 0
- record.cyc = 0
- record.wca = 0
- record.wff = 0
- record.byte_enable = 0xf
- record.wcount = 0
- record.rcount = len(reads_addrs)
-
- packet = EtherbonePacket()
- packet.records = [record]
- packet.encode()
- sock.sendto(bytes(packet), ("192.168.0.42", 20000))
- time.sleep(0.01)
+++ /dev/null
-import time
-from misoclib.tools.litescope.software.driver.la import LiteScopeLADriver
-
-
-def main(wb):
- la = LiteScopeLADriver(wb.regs, "la", debug=True)
-
- wb.open()
- regs = wb.regs
- # # #
- conditions = {}
- la.configure_term(port=0, cond=conditions)
- la.configure_sum("term")
- # Run Logic Analyzer
- la.run(offset=2048, length=4000)
-
- while not la.done():
- pass
-
- la.upload()
- la.save("dump.vcd")
- # # #
- wb.close()
+++ /dev/null
-def main(wb):
- wb.open()
- regs = wb.regs
- # # #
- print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
- print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
- print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
- SRAM_BASE = 0x02000000
- wb.write(SRAM_BASE, [i for i in range(64)])
- print(wb.read(SRAM_BASE, 64))
- # # #
- wb.close()
+++ /dev/null
-import socket
-import threading
-
-
-def test(fpga_ip, udp_port, test_message):
- tx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
- rx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
- rx_sock.bind(("", udp_port))
- rx_sock.settimeout(0.5)
-
- def receive():
- while True:
- try:
- msg = rx_sock.recv(8192)
- for byte in msg:
- print(chr(byte), end="")
- except:
- break
-
- def send():
- tx_sock.sendto(bytes(test_message, "utf-8"), (fpga_ip, udp_port))
-
- receive_thread = threading.Thread(target=receive)
- receive_thread.start()
-
- send_thread = threading.Thread(target=send)
- send_thread.start()
-
- try:
- send_thread.join(5)
- send_thread.join(5)
- except KeyboardInterrupt:
- pass
-
-
-def main(wb):
- test_message = "LiteEth virtual TTY Hello world\n"
- test("192.168.0.42", 10000, test_message)
+++ /dev/null
-import socket
-import time
-import threading
-import copy
-
-KB = 1024
-MB = 1024*KB
-GB = 1024*MB
-
-
-def seed_to_data(seed, random=True):
- if random:
- return (seed * 0x31415979 + 1) & 0xffffffff
- else:
- return seed
-
-
-def check(p1, p2):
- p1 = copy.deepcopy(p1)
- p2 = copy.deepcopy(p2)
- if isinstance(p1, int):
- return 0, 1, int(p1 != p2)
- else:
- if len(p1) >= len(p2):
- ref, res = p1, p2
- else:
- ref, res = p2, p1
- shift = 0
- while((ref[0] != res[0]) and (len(res) > 1)):
- res.pop(0)
- shift += 1
- length = min(len(ref), len(res))
- errors = 0
- for i in range(length):
- if ref.pop(0) != res.pop(0):
- errors += 1
- return shift, length, errors
-
-
-def generate_packet(seed, length):
- r = []
- for i in range(length):
- r.append(seed_to_data(seed, True)%0xff) # XXX FIXME
- seed += 1
- return r, seed
-
-
-def test(fpga_ip, udp_port, test_size):
- tx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
- rx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
- rx_sock.bind(("", udp_port))
-
- def receive():
- rx_seed = 0
- while rx_seed < test_size:
- data, addr = rx_sock.recvfrom(8192)
- rx_packet = []
- for byte in data:
- rx_packet.append(int(byte))
- rx_reference_packet, rx_seed = generate_packet(rx_seed, 1024)
- s, l, e = check(rx_reference_packet, rx_packet)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
- def send():
- tx_seed = 0
- while tx_seed < test_size:
- tx_packet, tx_seed = generate_packet(tx_seed, 1024)
- tx_sock.sendto(bytes(tx_packet), (fpga_ip, udp_port))
- time.sleep(0.001) # XXX: FIXME, Python limitation?
-
- receive_thread = threading.Thread(target=receive)
- receive_thread.start()
-
- send_thread = threading.Thread(target=send)
- send_thread.start()
-
- try:
- send_thread.join(10)
- receive_thread.join(0.1)
- except KeyboardInterrupt:
- pass
-
-
-def main(wb):
- test("192.168.0.42", 6000, 128*KB)
- test("192.168.0.42", 8000, 128*KB)
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.frontend.etherbone.packet import *
-from misoclib.com.liteeth.frontend.etherbone.probe import *
-from misoclib.com.liteeth.frontend.etherbone.record import *
-from misoclib.com.liteeth.frontend.etherbone.wishbone import *
-
-
-class LiteEthEtherbone(Module):
- def __init__(self, udp, udp_port):
- # decode/encode etherbone packets
- self.submodules.packet = packet = LiteEthEtherbonePacket(udp, udp_port)
-
- # packets can be probe (etherbone discovering) or records with
- # writes and reads
- self.submodules.probe = probe = LiteEthEtherboneProbe()
- self.submodules.record = record = LiteEthEtherboneRecord()
-
- # arbitrate/dispatch probe/records packets
- dispatcher = Dispatcher(packet.source, [probe.sink, record.sink])
- self.comb += dispatcher.sel.eq(~packet.source.pf)
- arbiter = Arbiter([probe.source, record.source], packet.sink)
- self.submodules += dispatcher, arbiter
-
- # create mmap ŵishbone master
- self.submodules.master = master = LiteEthEtherboneWishboneMaster()
- self.comb += [
- Record.connect(record.receiver.source, master.sink),
- Record.connect(master.source, record.sender.sink)
- ]
+++ /dev/null
---[[---------------
-LuaBit v0.4
--------------------
-a bitwise operation lib for lua.
-
-http://luaforge.net/projects/bit/
-
-How to use:
--------------------
- bit.bnot(n) -- bitwise not (~n)
- bit.band(m, n) -- bitwise and (m & n)
- bit.bor(m, n) -- bitwise or (m | n)
- bit.bxor(m, n) -- bitwise xor (m ^ n)
- bit.brshift(n, bits) -- right shift (n >> bits)
- bit.blshift(n, bits) -- left shift (n << bits)
- bit.blogic_rshift(n, bits) -- logic right shift(zero fill >>>)
-
-Please note that bit.brshift and bit.blshift only support number within
-32 bits.
-
-2 utility functions are provided too:
- bit.tobits(n) -- convert n into a bit table(which is a 1/0 sequence)
- -- high bits first
- bit.tonumb(bit_tbl) -- convert a bit table into a number
--------------------
-
-Under the MIT license.
-
-copyright(c) 2006~2007 hanzhao (abrash_han@hotmail.com)
---]]---------------
-
-do
-
-------------------------
--- bit lib implementions
-
-local function check_int(n)
- -- checking not float
- if(n - math.floor(n) > 0) then
- error("trying to use bitwise operation on non-integer!")
- end
-end
-
-local function to_bits(n)
- check_int(n)
- if(n < 0) then
- -- negative
- return to_bits(bit.bnot(math.abs(n)) + 1)
- end
- -- to bits table
- local tbl = {}
- local cnt = 1
- while (n > 0) do
- local last = math.mod(n,2)
- if(last == 1) then
- tbl[cnt] = 1
- else
- tbl[cnt] = 0
- end
- n = (n-last)/2
- cnt = cnt + 1
- end
-
- return tbl
-end
-
-local function tbl_to_number(tbl)
- local n = table.getn(tbl)
-
- local rslt = 0
- local power = 1
- for i = 1, n do
- rslt = rslt + tbl[i]*power
- power = power*2
- end
-
- return rslt
-end
-
-local function expand(tbl_m, tbl_n)
- local big = {}
- local small = {}
- if(table.getn(tbl_m) > table.getn(tbl_n)) then
- big = tbl_m
- small = tbl_n
- else
- big = tbl_n
- small = tbl_m
- end
- -- expand small
- for i = table.getn(small) + 1, table.getn(big) do
- small[i] = 0
- end
-
-end
-
-local function bit_or(m, n)
- local tbl_m = to_bits(m)
- local tbl_n = to_bits(n)
- expand(tbl_m, tbl_n)
-
- local tbl = {}
- local rslt = math.max(table.getn(tbl_m), table.getn(tbl_n))
- for i = 1, rslt do
- if(tbl_m[i]== 0 and tbl_n[i] == 0) then
- tbl[i] = 0
- else
- tbl[i] = 1
- end
- end
-
- return tbl_to_number(tbl)
-end
-
-local function bit_and(m, n)
- local tbl_m = to_bits(m)
- local tbl_n = to_bits(n)
- expand(tbl_m, tbl_n)
-
- local tbl = {}
- local rslt = math.max(table.getn(tbl_m), table.getn(tbl_n))
- for i = 1, rslt do
- if(tbl_m[i]== 0 or tbl_n[i] == 0) then
- tbl[i] = 0
- else
- tbl[i] = 1
- end
- end
-
- return tbl_to_number(tbl)
-end
-
-local function bit_not(n)
-
- local tbl = to_bits(n)
- local size = math.max(table.getn(tbl), 32)
- for i = 1, size do
- if(tbl[i] == 1) then
- tbl[i] = 0
- else
- tbl[i] = 1
- end
- end
- return tbl_to_number(tbl)
-end
-
-local function bit_xor(m, n)
- local tbl_m = to_bits(m)
- local tbl_n = to_bits(n)
- expand(tbl_m, tbl_n)
-
- local tbl = {}
- local rslt = math.max(table.getn(tbl_m), table.getn(tbl_n))
- for i = 1, rslt do
- if(tbl_m[i] ~= tbl_n[i]) then
- tbl[i] = 1
- else
- tbl[i] = 0
- end
- end
-
- --table.foreach(tbl, print)
-
- return tbl_to_number(tbl)
-end
-
-local function bit_rshift(n, bits)
- check_int(n)
-
- local high_bit = 0
- if(n < 0) then
- -- negative
- n = bit_not(math.abs(n)) + 1
- high_bit = 2147483648 -- 0x80000000
- end
-
- for i=1, bits do
- n = n/2
- n = bit_or(math.floor(n), high_bit)
- end
- return math.floor(n)
-end
-
--- logic rightshift assures zero filling shift
-local function bit_logic_rshift(n, bits)
- check_int(n)
- if(n < 0) then
- -- negative
- n = bit_not(math.abs(n)) + 1
- end
- for i=1, bits do
- n = n/2
- end
- return math.floor(n)
-end
-
-local function bit_lshift(n, bits)
- check_int(n)
-
- if(n < 0) then
- -- negative
- n = bit_not(math.abs(n)) + 1
- end
-
- for i=1, bits do
- n = n*2
- end
- return bit_and(n, 4294967295) -- 0xFFFFFFFF
-end
-
-local function bit_xor2(m, n)
- local rhs = bit_or(bit_not(m), bit_not(n))
- local lhs = bit_or(m, n)
- local rslt = bit_and(lhs, rhs)
- return rslt
-end
-
---------------------
--- bit lib interface
-
-bit = {
- -- bit operations
- bnot = bit_not,
- band = bit_and,
- bor = bit_or,
- bxor = bit_xor,
- brshift = bit_rshift,
- blshift = bit_lshift,
- bxor2 = bit_xor2,
- blogic_rshift = bit_logic_rshift,
-
- -- utility func
- tobits = to_bits,
- tonumb = tbl_to_number,
-}
-
-end
-
---[[
-for i = 1, 100 do
- for j = 1, 100 do
- if(bit.bxor(i, j) ~= bit.bxor2(i, j)) then
- error("bit.xor failed.")
- end
- end
-end
---]]
-
-
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
--- Etherbone Dissector
--- Copyright 2013 OHWR.org
--- Copyright 2015 EnjoyDigital (global clean up)
-
-local bit = require("bit")
-
-local VALS_BOOL = {[0] = "False", [1] = "True"}
-local VALS_RES = {[0] = "not set", [1] = "set, bad data?"}
-local VALS_SIZE = {
-[0x00] = "Bad Value",
-[0x01] = "8 bit",
-[0x02] = "16 bit",
-[0x03] = "16,8 bit",
-[0x04] = "32 bit",
-[0x05] = "32,8 bit",
-[0x06] = "32,16 bit",
-[0x07] = "32,16,8 bit",
-[0x08] = "64 bit",
-[0x09] = "64,8 bit",
-[0x0A] = "64,16 bit",
-[0x0B] = "64,16,8 bit",
-[0x0C] = "64,32 bit",
-[0x0D] = "64,32,8 bit",
-[0x0E] = "64,32,16 bit",
-[0x0F] = "64,32,16,8 bit",
-}
-
-function num2hex(num)
- local hexstr = '0123456789abcdef'
- local s = ''
- while num > 0 do
- local mod = math.fmod(num, 16)
- s = string.sub(hexstr, mod+1, mod+1) .. s
- num = math.floor(num / 16)
- end
- if s == '' then s = '0' end
- return s
-end
-
-function max(a, b)
- if a > b then
- return a
- else
- return b
- end
-end
-
--- declare protocol
-proto_eb = Proto("eb", "Etherbone")
-
--- declare fields
-local eb = proto_eb.fields
-eb.hdr = ProtoField.uint32("eb.hdr", "Header", base.HEX)
-eb.rec = ProtoField.bytes("eb.rec", "Record ", base.HEX)
-
-eb.hdr_magic = ProtoField.uint16("eb.hdr.magic", "Magic ", base.HEX, nil, 0xFFFF)
-eb.hdr_ver = ProtoField.uint16("eb.hdr.ver", "Version ", base.DEC, nil, 0xF000)
-eb.hdr_noreads = ProtoField.uint16("eb.hdr.noreads", "No Reads ", base.DEC, VALS_BOOL, 0x0400)
-eb.hdr_proberep = ProtoField.uint16("eb.hdr.proberes", "Probe Reply ", base.DEC, VALS_BOOL, 0x0200)
-eb.hdr_probereq = ProtoField.uint16("eb.hdr.probereq", "Probe Flag ", base.DEC, VALS_BOOL, 0x0100)
-eb.hdr_adrs = ProtoField.uint16("eb.hdr.adrw", "Address Width ", base.DEC, VALS_SIZE , 0x00F0)
-eb.hdr_ports = ProtoField.uint16("eb.hdr.portw", "Port Width ", base.DEC, VALS_SIZE , 0x000F)
-
-eb.rec_hdr = ProtoField.uint32("eb.rec.hdr", "Header ", base.HEX)
-eb.rec_writes = ProtoField.bytes("eb.rec.writes", "Writes ", base.HEX)
-eb.rec_reads = ProtoField.bytes("eb.rec.reads", "Reads ", base.HEX)
-
-eb.rec_hdr_flags = ProtoField.uint8("eb.rec.hdr.flags", "Flags ", base.HEX)
-eb.rec_hdr_select = ProtoField.uint8("eb.rec.hdr.select", "Select ", base.HEX)
-eb.rec_hdr_wr = ProtoField.uint8("eb.rec.hdr.wr", "Writes ", base.DEC)
-eb.rec_hdr_rd = ProtoField.uint8("eb.rec.hdr.rd", "Reads ", base.DEC)
-
-eb.rec_hdr_flags_adrcfg = ProtoField.uint8("eb.rec.hdr.flags.adrcfg", "ReplyToCfgSpace ", base.DEC, VALS_BOOL, 0x80)
-eb.rec_hdr_flags_rbacfg = ProtoField.uint8("eb.rec.hdr.adrcfg", "ReadFromCfgSpace ", base.DEC, VALS_BOOL, 0x40)
-eb.rec_hdr_flags_rdfifo = ProtoField.uint8("eb.rec.hdr.adrcfg", "ReadFIFO ", base.DEC, VALS_BOOL, 0x20)
-eb.rec_hdr_flags_dropcyc= ProtoField.uint8("eb.rec.hdr.adrcfg", "DropCycle ", base.DEC, VALS_BOOL, 0x08)
-eb.rec_hdr_flags_wbacfg = ProtoField.uint8("eb.rec.hdr.adrcfg", "WriteToCfgSpace ", base.DEC, VALS_BOOL, 0x04)
-eb.rec_hdr_flags_wrfifo = ProtoField.uint8("eb.rec.hdr.adrcfg", "WriteFIFO ", base.DEC, VALS_BOOL, 0x02)
-
-eb.rec_wrsadr8 = ProtoField.uint8("eb.rec.wrsadr8", "BaseAddr8 ", base.HEX)
-eb.rec_wrsadr16 = ProtoField.uint16("eb.rec.wrsadr16", "BaseAddr16 ", base.HEX)
-eb.rec_wrsadr32 = ProtoField.uint32("eb.rec.wrsadr32", "BaseAddr32 ", base.HEX)
-eb.rec_wrsadr64 = ProtoField.uint64("eb.rec.wrsadr64", "BaseAddr64 ", base.HEX)
-eb.rec_wrdata8 = ProtoField.uint8("eb.rec.wrdata8", "Value8 ", base.HEX)
-eb.rec_wrdata16 = ProtoField.uint16("eb.rec.wrdata16", "Value16 ", base.HEX)
-eb.rec_wrdata32 = ProtoField.uint32("eb.rec.wrdata32", "Value32 ", base.HEX)
-eb.rec_wrdata64 = ProtoField.uint64("eb.rec.wrdata64", "Value64 ", base.HEX)
-
-eb.rec_rdbadr8 = ProtoField.uint8("eb.rec.rdbadr8", "ReplyAddr8 ", base.HEX)
-eb.rec_rdbadr16 = ProtoField.uint16("eb.rec.rdbadr16", "ReplyAddr16 ", base.HEX)
-eb.rec_rdbadr32 = ProtoField.uint32("eb.rec.rdbadr32", "ReplyAddr32 ", base.HEX)
-eb.rec_rdbadr64 = ProtoField.uint64("eb.rec.rdbadr64", "ReplyAddr64 ", base.HEX)
-eb.rec_rddata8 = ProtoField.uint8("eb.rec.rddata8", "Address8 ", base.HEX)
-eb.rec_rddata16 = ProtoField.uint16("eb.rec.rddata16", "Address16 ", base.HEX)
-eb.rec_rddata32 = ProtoField.uint32("eb.rec.rddata32", "Address32 ", base.HEX)
-eb.rec_rddata64 = ProtoField.uint64("eb.rec.rddata64", "Address64 ", base.HEX)
-
--- define the dissector
-function proto_eb.dissector(buf, pinfo, tree)
- if (buf:len() < 4) then
- return 0 -- too short, go to default protocol
- end
-
- local mylen = buf:len()
- pinfo.cols.protocol = "eb"
-
- -- add packet to the tree root, fields will be added to subtree
- local t = tree:add( proto_eb, buf(0, mylen) )
- local t_hdr = t:add( eb.hdr, buf(0,4) )
-
- local magic = num2hex(tonumber(buf(0,2):uint()))
- if(magic == "4e6f") then
-
- t_hdr:add( eb.hdr_magic, buf(0,2)) -- magic
- t_hdr:add( eb.hdr_ver, buf(2,2)) -- version
- t_hdr:add( eb.hdr_noreads, buf(2,2)) -- no reads
- t_hdr:add( eb.hdr_proberep, buf(2,2)) -- probe response
- t_hdr:add( eb.hdr_probereq, buf(2,2)) -- probe request
-
- t_hdr:add( eb.hdr_adrs, buf(2,2)) -- supported addr size
- t_hdr:add( eb.hdr_ports, buf(2,2)) -- supported port size
-
- local probe = tonumber(buf(2,1):uint()) % 4
- if (probe == 0) then
- local widths = tonumber(buf(3,1):uint())
- local data_width = widths % 16
- local addr_width = (widths - data_width) / 16
- local alignment = max(max(addr_width, data_width), 2)
-
- local record_alignment = max(alignment, 4)
- local offset = max(alignment, 4)
-
- local recordcnt = 0
- while (offset < buf:len()) do
- local wr = tonumber(buf(offset+2,1):uint())
- local rd = tonumber(buf(offset+3,1):uint())
-
- local rdadr = 0
- local wradr = 0
- if(rd > 0) then
- rdadr = 1
- end
- if(wr > 0) then
- wradr = 1
- end
-
- if((wr == 0) and (rd == 0)) then
- offset = offset + record_alignment
- else
- local t_rec = t:add( "Record "..tostring(recordcnt).." (W"..tostring(wr).." R"..tostring(rd)..")", buf(offset, (record_alignment+(rd+wr+rdadr+wradr)*alignment)))
- recordcnt = recordcnt + 1
-
- local t_rec_hdr = t_rec:add( eb.rec_hdr, buf(offset,4))
- local t_rec_hdr_flags = t_rec_hdr:add( eb.rec_hdr_flags, buf(offset,1))
- t_rec_hdr_flags:add( eb.rec_hdr_flags_adrcfg, buf(offset,1))
- t_rec_hdr_flags:add( eb.rec_hdr_flags_rbacfg, buf(offset,1))
- t_rec_hdr_flags:add( eb.rec_hdr_flags_rdfifo, buf(offset,1))
- t_rec_hdr_flags:add( eb.rec_hdr_flags_dropcyc , buf(offset,1))
- t_rec_hdr_flags:add( eb.rec_hdr_flags_wbacfg , buf(offset,1))
- t_rec_hdr_flags:add( eb.rec_hdr_flags_wrfifo, buf(offset,1))
- t_rec_hdr:add( eb.rec_hdr_select, buf(offset+1,1))
- t_rec_hdr:add( eb.rec_hdr_wr, buf(offset+2,1))
- t_rec_hdr:add( eb.rec_hdr_rd, buf(offset+3,1))
- offset = offset + record_alignment
- local tmp_offset
-
- if(wr > 0) then
- local t_writes = t_rec:add( eb.rec_writes, buf(offset,(1+wr)*alignment))
-
- if addr_width==1 then t_writes:add(eb.rec_wrsadr8, buf(offset+alignment-1, 1))
- elseif addr_width==2 then t_writes:add(eb.rec_wrsadr16, buf(offset+alignment-2, 2))
- elseif addr_width==4 then t_writes:add(eb.rec_wrsadr32, buf(offset+alignment-4, 4))
- elseif addr_width==8 then t_writes:add(eb.rec_wrsadr64, buf(offset+alignment-8, 8))
- end
- offset = offset + alignment
-
- tmp_offset = offset
- while (tmp_offset < offset+wr*alignment) do
- if data_width==1 then t_writes:add( eb.rec_wrdata8, buf(tmp_offset+alignment-1, 1))
- elseif data_width==2 then t_writes:add( eb.rec_wrdata16, buf(tmp_offset+alignment-2, 2))
- elseif data_width==4 then t_writes:add( eb.rec_wrdata32, buf(tmp_offset+alignment-4, 4))
- elseif data_width==8 then t_writes:add( eb.rec_wrdata64, buf(tmp_offset+alignment-8, 8))
- end
- tmp_offset = tmp_offset + alignment
- end
- offset = tmp_offset
- end
-
- if(rd > 0) then
- local t_reads = t_rec:add( eb.rec_reads, buf(offset,(1+rd)*alignment))
-
- if addr_width==1 then t_reads:add( eb.rec_rdbadr8, buf(offset+alignment-1, 1))
- elseif addr_width==2 then t_reads:add( eb.rec_rdbadr16, buf(offset+alignment-2, 2))
- elseif addr_width==4 then t_reads:add( eb.rec_rdbadr32, buf(offset+alignment-4, 4))
- elseif addr_width==8 then t_reads:add( eb.rec_rdbadr64, buf(offset+alignment-8, 8))
- end
- offset = offset + alignment
-
- tmp_offset = offset
- while (tmp_offset < offset+rd*alignment) do
- if addr_width==1 then t_reads:add( eb.rec_rddata8, buf(tmp_offset+alignment-1, 1))
- elseif addr_width==2 then t_reads:add( eb.rec_rddata16, buf(tmp_offset+alignment-2, 2))
- elseif addr_width==4 then t_reads:add( eb.rec_rddata32, buf(tmp_offset+alignment-4, 4))
- elseif addr_width==8 then t_reads:add( eb.rec_rddata64, buf(tmp_offset+alignment-8, 8))
- end
- tmp_offset = tmp_offset + alignment
- end
- offset = tmp_offset
- end
- end
- end
-
- end
-
- else
- return 0
- end
-
-end
-
--- register eb protocol on UDP port 20000
-local tab = DissectorTable.get("udp.port")
-tab:add(20000, proto_eb)
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthEtherbonePacketPacketizer(Packetizer):
- def __init__(self):
- Packetizer.__init__(self,
- eth_etherbone_packet_description(32),
- eth_udp_user_description(32),
- etherbone_packet_header)
-
-
-class LiteEthEtherbonePacketTX(Module):
- def __init__(self, udp_port):
- self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
- self.source = source = Source(eth_udp_user_description(32))
-
- # # #
-
- self.submodules.packetizer = packetizer = LiteEthEtherbonePacketPacketizer()
- self.comb += [
- packetizer.sink.stb.eq(sink.stb),
- packetizer.sink.sop.eq(sink.sop),
- packetizer.sink.eop.eq(sink.eop),
- sink.ack.eq(packetizer.sink.ack),
-
- packetizer.sink.magic.eq(etherbone_magic),
- packetizer.sink.port_size.eq(32//8),
- packetizer.sink.addr_size.eq(32//8),
- packetizer.sink.pf.eq(sink.pf),
- packetizer.sink.pr.eq(sink.pr),
- packetizer.sink.nr.eq(sink.nr),
- packetizer.sink.version.eq(etherbone_version),
-
- packetizer.sink.data.eq(sink.data)
- ]
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- packetizer.source.ack.eq(1),
- If(packetizer.source.stb & packetizer.source.sop,
- packetizer.source.ack.eq(0),
- NextState("SEND")
- )
- )
- fsm.act("SEND",
- Record.connect(packetizer.source, source),
- source.src_port.eq(udp_port),
- source.dst_port.eq(udp_port),
- source.ip_address.eq(sink.ip_address),
- source.length.eq(sink.length + etherbone_packet_header.length),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthEtherbonePacketDepacketizer(Depacketizer):
- def __init__(self):
- Depacketizer.__init__(self,
- eth_udp_user_description(32),
- eth_etherbone_packet_description(32),
- etherbone_packet_header)
-
-
-class LiteEthEtherbonePacketRX(Module):
- def __init__(self):
- self.sink = sink = Sink(eth_udp_user_description(32))
- self.source = source = Source(eth_etherbone_packet_user_description(32))
-
- # # #
-
- self.submodules.depacketizer = depacketizer = LiteEthEtherbonePacketDepacketizer()
- self.comb += Record.connect(sink, depacketizer.sink)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb & depacketizer.source.sop,
- depacketizer.source.ack.eq(0),
- NextState("CHECK")
- )
- )
- valid = Signal()
- self.sync += valid.eq(
- depacketizer.source.stb &
- (depacketizer.source.magic == etherbone_magic)
- )
- fsm.act("CHECK",
- If(valid,
- NextState("PRESENT")
- ).Else(
- NextState("DROP")
- )
- )
- self.comb += [
- source.sop.eq(depacketizer.source.sop),
- source.eop.eq(depacketizer.source.eop),
-
- source.pf.eq(depacketizer.source.pf),
- source.pr.eq(depacketizer.source.pr),
- source.nr.eq(depacketizer.source.nr),
-
- source.data.eq(depacketizer.source.data),
-
- source.src_port.eq(sink.src_port),
- source.dst_port.eq(sink.dst_port),
- source.ip_address.eq(sink.ip_address),
- source.length.eq(sink.length - etherbone_packet_header.length)
- ]
- fsm.act("PRESENT",
- source.stb.eq(depacketizer.source.stb),
- depacketizer.source.ack.eq(source.ack),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
- fsm.act("DROP",
- depacketizer.source.ack.eq(1),
- If(depacketizer.source.stb &
- depacketizer.source.eop &
- depacketizer.source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteEthEtherbonePacket(Module):
- def __init__(self, udp, udp_port):
- self.submodules.tx = tx = LiteEthEtherbonePacketTX(udp_port)
- self.submodules.rx = rx = LiteEthEtherbonePacketRX()
- udp_port = udp.crossbar.get_port(udp_port, dw=32)
- self.comb += [
- Record.connect(tx.source, udp_port.sink),
- Record.connect(udp_port.source, rx.sink)
- ]
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthEtherboneProbe(Module):
- def __init__(self):
- self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
- self.source = source = Source(eth_etherbone_packet_user_description(32))
-
- # # #
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- sink.ack.eq(1),
- If(sink.stb & sink.sop,
- sink.ack.eq(0),
- NextState("PROBE_RESPONSE")
- )
- )
- fsm.act("PROBE_RESPONSE",
- Record.connect(sink, source),
- source.pf.eq(0),
- source.pr.eq(1),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthEtherboneRecordPacketizer(Packetizer):
- def __init__(self):
- Packetizer.__init__(self,
- eth_etherbone_record_description(32),
- eth_etherbone_packet_user_description(32),
- etherbone_record_header)
-
-
-class LiteEthEtherboneRecordDepacketizer(Depacketizer):
- def __init__(self):
- Depacketizer.__init__(self,
- eth_etherbone_packet_user_description(32),
- eth_etherbone_record_description(32),
- etherbone_record_header)
-
-
-class LiteEthEtherboneRecordReceiver(Module):
- def __init__(self, buffer_depth=256):
- self.sink = sink = Sink(eth_etherbone_record_description(32))
- self.source = source = Source(eth_etherbone_mmap_description(32))
-
- # # #
-
- fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth,
- buffered=True)
- self.submodules += fifo
- self.comb += Record.connect(sink, fifo.sink)
-
- self.submodules.base_addr = base_addr = FlipFlop(32)
- self.comb += base_addr.d.eq(fifo.source.data)
-
- self.submodules.counter = counter = Counter(max=512)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- fifo.source.ack.eq(1),
- counter.reset.eq(1),
- If(fifo.source.stb & fifo.source.sop,
- base_addr.ce.eq(1),
- If(fifo.source.wcount,
- NextState("RECEIVE_WRITES")
- ).Elif(fifo.source.rcount,
- NextState("RECEIVE_READS")
- )
- )
- )
- fsm.act("RECEIVE_WRITES",
- source.stb.eq(fifo.source.stb),
- source.sop.eq(counter.value == 0),
- source.eop.eq(counter.value == fifo.source.wcount-1),
- source.count.eq(fifo.source.wcount),
- source.be.eq(fifo.source.byte_enable),
- source.addr.eq(base_addr.q[2:] + counter.value),
- source.we.eq(1),
- source.data.eq(fifo.source.data),
- fifo.source.ack.eq(source.ack),
- If(source.stb & source.ack,
- counter.ce.eq(1),
- If(source.eop,
- If(fifo.source.rcount,
- NextState("RECEIVE_BASE_RET_ADDR")
- ).Else(
- NextState("IDLE")
- )
- )
- )
- )
- fsm.act("RECEIVE_BASE_RET_ADDR",
- counter.reset.eq(1),
- If(fifo.source.stb & fifo.source.sop,
- base_addr.ce.eq(1),
- NextState("RECEIVE_READS")
- )
- )
- fsm.act("RECEIVE_READS",
- source.stb.eq(fifo.source.stb),
- source.sop.eq(counter.value == 0),
- source.eop.eq(counter.value == fifo.source.rcount-1),
- source.count.eq(fifo.source.rcount),
- source.base_addr.eq(base_addr.q),
- source.addr.eq(fifo.source.data[2:]),
- fifo.source.ack.eq(source.ack),
- If(source.stb & source.ack,
- counter.ce.eq(1),
- If(source.eop,
- NextState("IDLE")
- )
- )
- )
-
-
-class LiteEthEtherboneRecordSender(Module):
- def __init__(self, buffer_depth=256):
- self.sink = sink = Sink(eth_etherbone_mmap_description(32))
- self.source = source = Source(eth_etherbone_record_description(32))
-
- # # #
-
- pbuffer = Buffer(eth_etherbone_mmap_description(32), buffer_depth)
- self.submodules += pbuffer
- self.comb += Record.connect(sink, pbuffer.sink)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- pbuffer.source.ack.eq(1),
- If(pbuffer.source.stb & pbuffer.source.sop,
- pbuffer.source.ack.eq(0),
- NextState("SEND_BASE_ADDRESS")
- )
- )
- self.comb += [
- source.byte_enable.eq(pbuffer.source.be),
- If(pbuffer.source.we,
- source.wcount.eq(pbuffer.source.count)
- ).Else(
- source.rcount.eq(pbuffer.source.count)
- )
- ]
-
- fsm.act("SEND_BASE_ADDRESS",
- source.stb.eq(pbuffer.source.stb),
- source.sop.eq(1),
- source.eop.eq(0),
- source.data.eq(pbuffer.source.base_addr),
- If(source.ack,
- NextState("SEND_DATA")
- )
- )
- fsm.act("SEND_DATA",
- source.stb.eq(pbuffer.source.stb),
- source.sop.eq(0),
- source.eop.eq(pbuffer.source.eop),
- source.data.eq(pbuffer.source.data),
- If(source.stb & source.ack,
- pbuffer.source.ack.eq(1),
- If(source.eop,
- NextState("IDLE")
- )
- )
- )
-
-
-# Limitation: For simplicity we only support 1 record per packet
-class LiteEthEtherboneRecord(Module):
- def __init__(self, endianness="big"):
- self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
- self.source = source = Sink(eth_etherbone_packet_user_description(32))
-
- # # #
-
- # receive record, decode it and generate mmap stream
- self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
- self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver()
- self.comb += [
- Record.connect(sink, depacketizer.sink),
- Record.connect(depacketizer.source, receiver.sink)
- ]
- if endianness is "big":
- self.comb += receiver.sink.data.eq(reverse_bytes(depacketizer.source.data))
-
- # save last ip address
- last_ip_address = Signal(32)
- self.sync += [
- If(sink.stb & sink.sop & sink.ack,
- last_ip_address.eq(sink.ip_address)
- )
- ]
-
- # receive mmap stream, encode it and send records
- self.submodules.sender = sender = LiteEthEtherboneRecordSender()
- self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
- self.comb += [
- Record.connect(sender.source, packetizer.sink),
- Record.connect(packetizer.source, source),
- # XXX improve this
- source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header.length),
- source.ip_address.eq(last_ip_address)
- ]
- if endianness is "big":
- self.comb += packetizer.sink.data.eq(reverse_bytes(sender.source.data))
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from migen.bus import wishbone
-
-
-class LiteEthEtherboneWishboneMaster(Module):
- def __init__(self):
- self.sink = sink = Sink(eth_etherbone_mmap_description(32))
- self.source = source = Source(eth_etherbone_mmap_description(32))
- self.bus = bus = wishbone.Interface()
-
- # # #
-
- self.submodules.data = data = FlipFlop(32)
- self.comb += data.d.eq(bus.dat_r)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- sink.ack.eq(1),
- If(sink.stb & sink.sop,
- sink.ack.eq(0),
- If(sink.we,
- NextState("WRITE_DATA")
- ).Else(
- NextState("READ_DATA")
- )
- )
- )
- fsm.act("WRITE_DATA",
- bus.adr.eq(sink.addr),
- bus.dat_w.eq(sink.data),
- bus.sel.eq(sink.be),
- bus.stb.eq(sink.stb),
- bus.we.eq(1),
- bus.cyc.eq(1),
- If(bus.stb & bus.ack,
- sink.ack.eq(1),
- If(sink.eop,
- NextState("IDLE")
- )
- )
- )
- fsm.act("READ_DATA",
- bus.adr.eq(sink.addr),
- bus.sel.eq(sink.be),
- bus.stb.eq(sink.stb),
- bus.cyc.eq(1),
- If(bus.stb & bus.ack,
- data.ce.eq(1),
- NextState("SEND_DATA")
- )
- )
- fsm.act("SEND_DATA",
- source.stb.eq(sink.stb),
- source.sop.eq(sink.sop),
- source.eop.eq(sink.eop),
- source.base_addr.eq(sink.base_addr),
- source.addr.eq(sink.addr),
- source.count.eq(sink.count),
- source.be.eq(sink.be),
- source.we.eq(1),
- source.data.eq(data.q),
- If(source.stb & source.ack,
- sink.ack.eq(1),
- If(source.eop,
- NextState("IDLE")
- ).Else(
- NextState("READ_DATA")
- )
- )
- )
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthTTYTX(Module):
- def __init__(self, ip_address, udp_port, fifo_depth=None):
- self.sink = sink = Sink(eth_tty_description(8))
- self.source = source = Source(eth_udp_user_description(8))
-
- # # #
-
- if fifo_depth is None:
- self.comb += [
- source.stb.eq(sink.stb),
- source.sop.eq(1),
- source.eop.eq(1),
- source.length.eq(1),
- source.data.eq(sink.data),
- sink.ack.eq(source.ack)
- ]
- else:
- self.submodules.fifo = fifo = SyncFIFO([("data", 8)], fifo_depth)
- self.comb += Record.connect(sink, fifo.sink)
-
- self.submodules.level = level = FlipFlop(max=fifo_depth)
- self.comb += level.d.eq(fifo.fifo.level)
-
- self.submodules.counter = counter = Counter(max=fifo_depth)
-
- self.submodules.fsm = fsm = FSM(reset_state="IDLE")
- fsm.act("IDLE",
- If(fifo.source.stb,
- level.ce.eq(1),
- counter.reset.eq(1),
- NextState("SEND")
- )
- )
- fsm.act("SEND",
- source.stb.eq(fifo.source.stb),
- source.sop.eq(counter.value == 0),
- If(level.q == 0,
- source.eop.eq(1),
- ).Else(
- source.eop.eq(counter.value == (level.q-1)),
- ),
- source.src_port.eq(udp_port),
- source.dst_port.eq(udp_port),
- source.ip_address.eq(ip_address),
- If(level.q == 0,
- source.length.eq(1),
- ).Else(
- source.length.eq(level.q),
- ),
- source.data.eq(fifo.source.data),
- fifo.source.ack.eq(source.ack),
- If(source.stb & source.ack,
- counter.ce.eq(1),
- If(source.eop,
- NextState("IDLE")
- )
- )
- )
-
-
-class LiteEthTTYRX(Module):
- def __init__(self, ip_address, udp_port, fifo_depth=None):
- self.sink = sink = Sink(eth_udp_user_description(8))
- self.source = source = Source(eth_tty_description(8))
-
- # # #
-
- valid = Signal()
- self.comb += valid.eq(
- (sink.ip_address == ip_address) &
- (sink.dst_port == udp_port)
- )
- if fifo_depth is None:
- self.comb += [
- source.stb.eq(sink.stb & valid),
- source.data.eq(sink.data),
- sink.ack.eq(source.ack)
- ]
- else:
- self.submodules.fifo = fifo = SyncFIFO([("data", 8)], fifo_depth)
- self.comb += [
- fifo.sink.stb.eq(sink.stb & valid),
- fifo.sink.data.eq(sink.data),
- sink.ack.eq(fifo.sink.ack),
- Record.connect(fifo.source, source)
- ]
-
-
-class LiteEthTTY(Module):
- def __init__(self, udp, ip_address, udp_port,
- rx_fifo_depth=64,
- tx_fifo_depth=64):
- self.submodules.tx = tx = LiteEthTTYTX(ip_address, udp_port, tx_fifo_depth)
- self.submodules.rx = rx = LiteEthTTYRX(ip_address, udp_port, rx_fifo_depth)
- udp_port = udp.crossbar.get_port(udp_port, dw=8)
- self.comb += [
- Record.connect(tx.source, udp_port.sink),
- Record.connect(udp_port.source, rx.sink)
- ]
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
- # Autodetect PHY
- if hasattr(pads, "source_stb"):
- # This is a simulation PHY
- from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
- return LiteEthPHYSim(pads)
- elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
- if hasattr(clock_pads, "tx"):
- # This is a 10/100/1G PHY
- from misoclib.com.liteeth.phy.gmii_mii import LiteEthPHYGMIIMII
- return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
- else:
- # This is a pure 1G PHY
- from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
- return LiteEthPHYGMII(clock_pads, pads, **kwargs)
- elif hasattr(pads, "rx_ctl"):
- # This is a 10/100/1G RGMII PHY
- raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
- elif flen(pads.tx_data) == 4:
- # This is a MII PHY
- from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
- return LiteEthPHYMII(clock_pads, pads, **kwargs)
- else:
- raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation")
+++ /dev/null
-from migen.genlib.io import DDROutput
-
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthPHYGMIITX(Module):
- def __init__(self, pads, pads_register=True):
- self.sink = sink = Sink(eth_phy_description(8))
-
- # # #
-
- if hasattr(pads, "tx_er"):
- self.sync += pads.tx_er.eq(0)
- pads_eq = [
- pads.tx_en.eq(sink.stb),
- pads.tx_data.eq(sink.data)
- ]
- if pads_register:
- self.sync += pads_eq
- else:
- self.comb += pads_eq
- self.comb += sink.ack.eq(1)
-
-
-class LiteEthPHYGMIIRX(Module):
- def __init__(self, pads):
- self.source = source = Source(eth_phy_description(8))
-
- # # #
-
- dv_d = Signal()
- self.sync += dv_d.eq(pads.dv)
-
- sop = Signal()
- eop = Signal()
- self.comb += [
- sop.eq(pads.dv & ~dv_d),
- eop.eq(~pads.dv & dv_d)
- ]
- self.sync += [
- source.stb.eq(pads.dv),
- source.sop.eq(sop),
- source.data.eq(pads.rx_data)
- ]
- self.comb += source.eop.eq(eop)
-
-
-class LiteEthPHYGMIICRG(Module, AutoCSR):
- def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
- self._reset = CSRStorage()
-
- # # #
-
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
-
- # RX : Let the synthesis tool insert the appropriate clock buffer
- self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
-
- # TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused
- # MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
- self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
- # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
- self.specials += Instance("BUFGMUX",
- i_I0=self.cd_eth_rx.clk,
- i_I1=clock_pads.tx,
- i_S=mii_mode,
- o_O=self.cd_eth_tx.clk)
-
- if with_hw_init_reset:
- reset = Signal()
- counter_done = Signal()
- self.submodules.counter = counter = Counter(max=512)
- self.comb += [
- counter_done.eq(counter.value == 256),
- counter.ce.eq(~counter_done),
- reset.eq(~counter_done | self._reset.storage)
- ]
- else:
- reset = self._reset.storage
- self.comb += pads.rst_n.eq(~reset)
- self.specials += [
- AsyncResetSynchronizer(self.cd_eth_tx, reset),
- AsyncResetSynchronizer(self.cd_eth_rx, reset),
- ]
-
-
-class LiteEthPHYGMII(Module, AutoCSR):
- def __init__(self, clock_pads, pads, with_hw_init_reset=True):
- self.dw = 8
- self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
- pads,
- with_hw_init_reset)
- self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
- "eth_tx")
- self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
- "eth_rx")
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-from migen.genlib.io import DDROutput
-from migen.flow.plumbing import Multiplexer, Demultiplexer
-from migen.genlib.cdc import PulseSynchronizer
-
-from misoclib.com.liteeth.common import *
-
-from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIICRG
-from misoclib.com.liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
-from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
-
-modes = {
- "GMII": 0,
- "MII": 1
-}
-
-tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
-rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)]
-
-
-class LiteEthPHYGMIIMIITX(Module):
- def __init__(self, pads, mode):
- self.sink = sink = Sink(eth_phy_description(8))
-
- # # #
-
- gmii_tx_pads = Record(tx_pads_layout)
- gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False)
- self.submodules += gmii_tx
-
- mii_tx_pads = Record(tx_pads_layout)
- mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False)
- self.submodules += mii_tx
-
- demux = Demultiplexer(eth_phy_description(8), 2)
- self.submodules += demux
- self.comb += [
- demux.sel.eq(mode == modes["MII"]),
- Record.connect(sink, demux.sink),
- Record.connect(demux.source0, gmii_tx.sink),
- Record.connect(demux.source1, mii_tx.sink),
- ]
-
- if hasattr(pads, "tx_er"):
- self.comb += pads.tx_er.eq(0)
- self.sync += [
- If(mode == modes["MII"],
- pads.tx_en.eq(mii_tx_pads.tx_en),
- pads.tx_data.eq(mii_tx_pads.tx_data),
- ).Else(
- pads.tx_en.eq(gmii_tx_pads.tx_en),
- pads.tx_data.eq(gmii_tx_pads.tx_data),
- )
- ]
-
-
-class LiteEthPHYGMIIMIIRX(Module):
- def __init__(self, pads, mode):
- self.source = source = Source(eth_phy_description(8))
-
- # # #
-
- pads_d = Record(rx_pads_layout)
- self.sync += [
- pads_d.dv.eq(pads.dv),
- pads_d.rx_data.eq(pads.rx_data)
- ]
-
- gmii_rx = LiteEthPHYGMIIRX(pads_d)
- self.submodules += gmii_rx
-
- mii_rx = LiteEthPHYMIIRX(pads_d)
- self.submodules += mii_rx
-
- mux = Multiplexer(eth_phy_description(8), 2)
- self.submodules += mux
- self.comb += [
- mux.sel.eq(mode == modes["MII"]),
- Record.connect(gmii_rx.source, mux.sink0),
- Record.connect(mii_rx.source, mux.sink1),
- Record.connect(mux.source, source)
- ]
-
-
-class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
- def __init__(self, clk_freq):
- self.mode = Signal()
- self._mode = CSRStatus()
-
- # # #
-
- mode = Signal()
- update_mode = Signal()
- self.sync += \
- If(update_mode,
- self.mode.eq(mode)
- )
- self.comb += self._mode.status.eq(self.mode)
-
- # Principle:
- # sys_clk >= 125MHz
- # eth_rx <= 125Mhz
- # We generate ticks every 1024 clock cycles in eth_rx domain
- # and measure ticks period in sys_clk domain.
-
- # Generate a tick every 1024 clock cycles (eth_rx clock domain)
- eth_tick = Signal()
- eth_counter = Signal(10)
- self.sync.eth_rx += eth_counter.eq(eth_counter + 1)
- self.comb += eth_tick.eq(eth_counter == 0)
-
- # Synchronize tick (sys clock domain)
- sys_tick = Signal()
- eth_ps = PulseSynchronizer("eth_rx", "sys")
- self.comb += [
- eth_ps.i.eq(eth_tick),
- sys_tick.eq(eth_ps.o)
- ]
- self.submodules += eth_ps
-
- # sys_clk domain counter
- sys_counter = Counter(24)
- self.submodules += sys_counter
-
- fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
-
- fsm.act("IDLE",
- sys_counter.reset.eq(1),
- If(sys_tick,
- NextState("COUNT")
- )
- )
- fsm.act("COUNT",
- sys_counter.ce.eq(1),
- If(sys_tick,
- NextState("DETECTION")
- )
- )
- fsm.act("DETECTION",
- update_mode.eq(1),
- # if freq < 125MHz-5% use MII mode
- If(sys_counter.value > int((clk_freq/125000000)*1024*1.05),
- mode.eq(1)
- # if freq >= 125MHz-5% use GMII mode
- ).Else(
- mode.eq(0)
- ),
- NextState("IDLE")
- )
-
-
-class LiteEthPHYGMIIMII(Module, AutoCSR):
- def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
- self.dw = 8
- # Note: we can use GMII CRG since it also handles tx clock pad used for MII
- self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
- mode = self.mode_detection.mode
- self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
- self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
- self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.generic import *
-
-
-class LiteEthPHYLoopbackCRG(Module, AutoCSR):
- def __init__(self):
- self._reset = CSRStorage()
-
- # # #
-
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal())
- ]
-
- reset = self._reset.storage
- self.comb += [
- self.cd_eth_rx.rst.eq(reset),
- self.cd_eth_tx.rst.eq(reset)
- ]
-
-
-class LiteEthPHYLoopback(Module, AutoCSR):
- def __init__(self):
- self.dw = 8
- self.submodules.crg = LiteEthLoopbackPHYCRG()
- self.sink = sink = Sink(eth_phy_description(8))
- self.source = source = Source(eth_phy_description(8))
- self.comb += Record.connect(self.sink, self.source)
+++ /dev/null
-from misoclib.com.liteeth.common import *
-
-
-def converter_description(dw):
- payload_layout = [("data", dw)]
- return EndpointDescription(payload_layout, packetized=True)
-
-
-class LiteEthPHYMIITX(Module):
- def __init__(self, pads, pads_register=True):
- self.sink = sink = Sink(eth_phy_description(8))
-
- # # #
-
- if hasattr(pads, "tx_er"):
- self.sync += pads.tx_er.eq(0)
- converter = Converter(converter_description(8),
- converter_description(4))
- self.submodules += converter
- self.comb += [
- converter.sink.stb.eq(sink.stb),
- converter.sink.data.eq(sink.data),
- sink.ack.eq(converter.sink.ack),
- converter.source.ack.eq(1)
- ]
- pads_eq = [
- pads.tx_en.eq(converter.source.stb),
- pads.tx_data.eq(converter.source.data)
- ]
- if pads_register:
- self.sync += pads_eq
- else:
- self.comb += pads_eq
-
-
-class LiteEthPHYMIIRX(Module):
- def __init__(self, pads):
- self.source = source = Source(eth_phy_description(8))
-
- # # #
-
- sop = FlipFlop(reset=1)
- self.submodules += sop
-
- converter = Converter(converter_description(4),
- converter_description(8))
- converter = InsertReset(converter)
- self.submodules += converter
-
- self.sync += [
- converter.reset.eq(~pads.dv),
- converter.sink.stb.eq(1),
- converter.sink.data.eq(pads.rx_data)
- ]
- self.comb += [
- sop.reset.eq(~pads.dv),
- sop.ce.eq(pads.dv),
- converter.sink.sop.eq(sop.q),
- converter.sink.eop.eq(~pads.dv)
- ]
- self.comb += Record.connect(converter.source, source)
-
-
-class LiteEthPHYMIICRG(Module, AutoCSR):
- def __init__(self, clock_pads, pads, with_hw_init_reset):
- self._reset = CSRStorage()
-
- # # #
-
- if hasattr(clock_pads, "phy"):
- self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
-
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
- self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
-
- if with_hw_init_reset:
- reset = Signal()
- counter_done = Signal()
- self.submodules.counter = counter = Counter(max=512)
- self.comb += [
- counter_done.eq(counter.value == 256),
- counter.ce.eq(~counter_done),
- reset.eq(~counter_done | self._reset.storage)
- ]
- else:
- reset = self._reset.storage
- self.comb += pads.rst_n.eq(~reset)
- self.specials += [
- AsyncResetSynchronizer(self.cd_eth_tx, reset),
- AsyncResetSynchronizer(self.cd_eth_rx, reset),
- ]
-
-
-class LiteEthPHYMII(Module, AutoCSR):
- def __init__(self, clock_pads, pads, with_hw_init_reset=True):
- self.dw = 8
- self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
- self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
- self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-# RGMII PHY for Spartan-6
-
-from migen.genlib.io import DDROutput
-from migen.genlib.misc import WaitTimer
-from migen.genlib.fsm import FSM, NextState
-
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthPHYRGMIITX(Module):
- def __init__(self, pads, pads_register=True):
- self.sink = sink = Sink(eth_phy_description(8))
-
- # # #
-
- self.specials += Instance("ODDR2",
- p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
- i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"),
- i_CE=1, i_S=0, i_R=0,
- i_D0=sink.stb, i_D1=sink.stb, o_Q=pads.tx_ctl,
- )
- for i in range(4):
- self.specials += Instance("ODDR2",
- p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
- i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"),
- i_CE=1, i_S=0, i_R=0,
- i_D0=sink.data[i], i_D1=sink.data[4+i], o_Q=pads.tx_data[i],
- )
- self.comb += sink.ack.eq(1)
-
-
-class LiteEthPHYRGMIIRX(Module):
- def __init__(self, pads):
- self.source = source = Source(eth_phy_description(8))
-
- # # #
-
- rx_ctl = Signal()
- rx_data = Signal(8)
-
- self.specials += Instance("IDDR2",
- p_DDR_ALIGNMENT="C0", p_INIT_Q0=0, p_INIT_Q1=0, p_SRTYPE="ASYNC",
- i_C0=ClockSignal("eth_rx"), i_C1=~ClockSignal("eth_rx"),
- i_CE=1, i_S=0, i_R=0,
- i_D=pads.rx_ctl, o_Q1=rx_ctl,
- )
- for i in range(4):
- self.specials += Instance("IDDR2",
- p_DDR_ALIGNMENT="C0", p_INIT_Q0=0, p_INIT_Q1=0, p_SRTYPE="ASYNC",
- i_C0=ClockSignal("eth_rx"), i_C1=~ClockSignal("eth_rx"),
- i_CE=1, i_S=0, i_R=0,
- i_D=pads.rx_data[i], o_Q0=rx_data[4+i], o_Q1=rx_data[i],
- )
-
-
- rx_ctl_d = Signal()
- self.sync += rx_ctl_d.eq(rx_ctl)
-
- sop = Signal()
- eop = Signal()
- self.comb += [
- sop.eq(rx_ctl & ~rx_ctl_d),
- eop.eq(~rx_ctl & rx_ctl_d)
- ]
- self.sync += [
- source.stb.eq(rx_ctl),
- source.sop.eq(sop),
- source.data.eq(rx_data)
- ]
- self.comb += source.eop.eq(eop)
-
-
-class LiteEthPHYRGMIICRG(Module, AutoCSR):
- def __init__(self, clock_pads, pads, with_hw_init_reset):
- self._reset = CSRStorage()
-
- # # #
-
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
-
-
- # RX
- dcm_reset = Signal()
- dcm_locked = Signal()
-
- timer = WaitTimer(1024)
- fsm = FSM(reset_state="DCM_RESET")
- self.submodules += timer, fsm
-
- fsm.act("DCM_RESET",
- dcm_reset.eq(1),
- timer.wait.eq(1),
- If(timer.done,
- timer.wait.eq(0),
- NextState("DCM_WAIT")
- )
- )
- fsm.act("DCM_WAIT",
- timer.wait.eq(1),
- If(timer.done,
- NextState("DCM_CHECK_LOCK")
- )
- )
- fsm.act("DCM_CHECK_LOCK",
- If(~dcm_locked,
- NextState("DCM_RESET")
- )
- )
-
- clk90_rx = Signal()
- clk0_rx = Signal()
- clk0_rx_bufg = Signal()
- self.specials += Instance("DCM",
- i_CLKIN=clock_pads.rx,
- i_CLKFB=clk0_rx_bufg,
- o_CLK0=clk0_rx,
- o_CLK90=clk90_rx,
- o_LOCKED=dcm_locked,
- i_PSEN=0,
- i_PSCLK=0,
- i_PSINCDEC=0,
- i_RST=dcm_reset
- )
-
- self.specials += Instance("BUFG", i_I=clk0_rx, o_O=clk0_rx_bufg)
- self.specials += Instance("BUFG", i_I=clk90_rx, o_O=self.cd_eth_rx.clk)
-
- # TX
- self.specials += DDROutput(1, 0, clock_pads.tx, ClockSignal("eth_tx"))
- self.specials += Instance("BUFG", i_I=self.cd_eth_rx.clk, o_O=self.cd_eth_tx.clk)
-
- # Reset
- if with_hw_init_reset:
- reset = Signal()
- counter_done = Signal()
- self.submodules.counter = counter = Counter(max=512)
- self.comb += [
- counter_done.eq(counter.value == 256),
- counter.ce.eq(~counter_done),
- reset.eq(~counter_done | self._reset.storage)
- ]
- else:
- reset = self._reset.storage
- self.comb += pads.rst_n.eq(~reset)
- self.specials += [
- AsyncResetSynchronizer(self.cd_eth_tx, reset),
- AsyncResetSynchronizer(self.cd_eth_rx, reset),
- ]
-
-
-class LiteEthPHYRGMII(Module, AutoCSR):
- def __init__(self, clock_pads, pads, with_hw_init_reset=True):
- self.dw = 8
- self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
- pads,
- with_hw_init_reset)
- self.submodules.tx = RenameClockDomains(LiteEthPHYRGMIITX(pads),
- "eth_tx")
- self.submodules.rx = RenameClockDomains(LiteEthPHYRGMIIRX(pads),
- "eth_rx")
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-import os
-
-from misoclib.com.liteeth.common import *
-
-
-class LiteEthPHYSimCRG(Module, AutoCSR):
- def __init__(self):
- self._reset = CSRStorage()
-
- # # #
-
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal())
- ]
-
- reset = self._reset.storage
- self.comb += [
- self.cd_eth_rx.rst.eq(reset),
- self.cd_eth_tx.rst.eq(reset)
- ]
-
-
-class LiteEthPHYSim(Module, AutoCSR):
- def __init__(self, pads, tap="tap0", ip_address="192.168.0.14"):
- self.dw = 8
- self.submodules.crg = LiteEthPHYSimCRG()
- self.sink = sink = Sink(eth_phy_description(8))
- self.source = source = Source(eth_phy_description(8))
- self.tap = tap
- self.ip_address = ip_address
-
- self.comb += [
- pads.source_stb.eq(self.sink.stb),
- pads.source_data.eq(self.sink.data),
- self.sink.ack.eq(1)
- ]
-
- self.sync += [
- self.source.stb.eq(pads.sink_stb),
- self.source.sop.eq(pads.sink_stb & ~self.source.stb),
- self.source.data.eq(pads.sink_data),
- ]
- self.comb += [
- self.source.eop.eq(~pads.sink_stb & self.source.stb),
- ]
-
- # XXX avoid use of os.system
- os.system("openvpn --mktun --dev {}".format(self.tap))
- os.system("ifconfig {} {} up".format(self.tap, self.ip_address))
- os.system("mknod /dev/net/{} c 10 200".format(self.tap))
-
- def do_exit(self, *args, **kwargs):
- # XXX avoid use of os.system
- os.system("rm -f /dev/net/{}".format(self.tap))
- os.system("openvpn --rmtun --dev {}".format(self.tap))
+++ /dev/null
-import socket
-
-from misoclib.tools.litescope.software.driver.reg import *
-
-from misoclib.com.liteeth.test.model.etherbone import *
-
-
-class LiteEthWishboneBridgeDriver:
- def __init__(self, ip_address, udp_port=20000, addrmap=None, busword=8, debug=False):
- self.ip_address = ip_address
- self.udp_port = udp_port
- self.debug = debug
-
- self.tx_sock = None
- self.rx_sock = None
- if addrmap is not None:
- self.regs = build_map(addrmap, busword, self.read, self.write)
-
- def open(self):
- self.tx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
- self.rx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
- self.rx_sock.bind(("", self.udp_port))
-
- def close(self):
- pass
-
- def read(self, addr, burst_length=1):
- reads_addrs = [addr+4*j for j in range(burst_length)]
- reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
- record = EtherboneRecord()
- record.writes = None
- record.reads = reads
- record.bca = 0
- record.rca = 0
- record.rff = 0
- record.cyc = 0
- record.wca = 0
- record.wff = 0
- record.byte_enable = 0xf
- record.wcount = 0
- record.rcount = len(reads_addrs)
-
- packet = EtherbonePacket()
- packet.records = [record]
- packet.encode()
- self.tx_sock.sendto(bytes(packet), (self.ip_address, self.udp_port))
-
- datas, addrs = self.rx_sock.recvfrom(8192)
- packet = EtherbonePacket(datas)
- packet.decode()
- datas = packet.records.pop().writes.get_datas()
- if self.debug:
- for i, data in enumerate(datas):
- print("RD {:08X} @ {:08X}".format(data, addr + 4*i))
- if burst_length == 1:
- return datas[0]
- else:
- return datas
-
- def write(self, addr, datas):
- if not isinstance(datas, list):
- datas = [datas]
- writes_datas = [d for d in datas]
- writes = EtherboneWrites(base_addr=addr, datas=writes_datas)
- record = EtherboneRecord()
- record.writes = writes
- record.reads = None
- record.bca = 0
- record.rca = 0
- record.rff = 0
- record.cyc = 0
- record.wca = 0
- record.wff = 0
- record.byte_enable = 0xf
- record.wcount = len(writes_datas)
- record.rcount = 0
-
- packet = EtherbonePacket()
- packet.records = [record]
- packet.encode()
- self.tx_sock.sendto(bytes(packet), (self.ip_address, self.udp_port))
-
- if self.debug:
- for i, data in enumerate(datas):
- print("WR {:08X} @ {:08X}".format(data, addr + 4*i))
+++ /dev/null
-LEDIR = ../../
-PYTHON = python3
-
-CMD = PYTHONPATH=$(LEDIR) $(PYTHON)
-
-model_tb:
- $(CMD) ./model/mac.py
- $(CMD) ./model/arp.py
- $(CMD) ./model/ip.py
- $(CMD) ./model/udp.py
- $(CMD) ./model/icmp.py
- $(CMD) ./model/etherbone.py
-
-mac_core_tb:
- $(CMD) mac_core_tb.py
-
-mac_wishbone_tb:
- $(CMD) mac_wishbone_tb.py
-
-arp_tb:
- $(CMD) arp_tb.py
-
-ip_tb:
- $(CMD) ip_tb.py
-
-udp_tb:
- $(CMD) udp_tb.py
-
-icmp_tb:
- $(CMD) icmp_tb.py
-
-etherbone_tb:
- $(CMD) etherbone_tb.py
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac import LiteEthMAC
-from misoclib.com.liteeth.core.arp import LiteEthARP
-
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac, arp
-
-ip_address = 0x12345678
-mac_address = 0x12345678abcd
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.phy_model = phy.PHY(8, debug=False)
- self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
- self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
-
- self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_preamble_crc=True)
- self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, 100000)
-
- # use sys_clk for each clock_domain
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_rx.rst.eq(ResetSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal()),
- self.cd_eth_tx.rst.eq(ResetSignal()),
- ]
-
- def gen_simulation(self, selfp):
- selfp.cd_eth_rx.rst = 1
- selfp.cd_eth_tx.rst = 1
- yield
- selfp.cd_eth_rx.rst = 0
- selfp.cd_eth_tx.rst = 0
-
- for i in range(100):
- yield
-
- while selfp.arp.table.request.ack != 1:
- selfp.arp.table.request.stb = 1
- selfp.arp.table.request.ip_address = 0x12345678
- yield
- selfp.arp.table.request.stb = 0
- while selfp.arp.table.response.stb != 1:
- selfp.arp.table.response.ack = 1
- yield
- print("Received MAC : 0x{:12x}".format(selfp.arp.table.response.mac_address))
-
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-import random
-import copy
-
-from migen.fhdl.std import *
-from migen.flow.actor import Sink, Source
-from migen.genlib.record import *
-
-from misoclib.com.liteeth.common import *
-
-
-def print_with_prefix(s, prefix=""):
- if not isinstance(s, str):
- s = s.__repr__()
- s = s.split("\n")
- for l in s:
- print(prefix + l)
-
-
-def seed_to_data(seed, random=True):
- if random:
- return (seed * 0x31415979 + 1) & 0xffffffff
- else:
- return seed
-
-
-def split_bytes(v, n, endianness="big"):
- r = []
- r_bytes = v.to_bytes(n, byteorder=endianness)
- for byte in r_bytes:
- r.append(int(byte))
- return r
-
-
-def merge_bytes(b, endianness="big"):
- return int.from_bytes(bytes(b), endianness)
-
-
-def get_field_data(field, datas):
- v = merge_bytes(datas[field.byte:field.byte+math.ceil(field.width/8)])
- return (v >> field.offset) & (2**field.width-1)
-
-
-def comp(p1, p2):
- r = True
- for x, y in zip(p1, p2):
- if x != y:
- r = False
- return r
-
-
-def check(p1, p2):
- p1 = copy.deepcopy(p1)
- p2 = copy.deepcopy(p2)
- if isinstance(p1, int):
- return 0, 1, int(p1 != p2)
- else:
- if len(p1) >= len(p2):
- ref, res = p1, p2
- else:
- ref, res = p2, p1
- shift = 0
- while((ref[0] != res[0]) and (len(res) > 1)):
- res.pop(0)
- shift += 1
- length = min(len(ref), len(res))
- errors = 0
- for i in range(length):
- if ref.pop(0) != res.pop(0):
- errors += 1
- return shift, length, errors
-
-
-def randn(max_n):
- return random.randint(0, max_n-1)
-
-
-class Packet(list):
- def __init__(self, init=[]):
- self.ongoing = False
- self.done = False
- for data in init:
- self.append(data)
-
-
-class PacketStreamer(Module):
- def __init__(self, description, last_be=None):
- self.source = Source(description)
- self.last_be = last_be
-
- # # #
-
- self.packets = []
- self.packet = Packet()
- self.packet.done = True
-
- def send(self, packet):
- packet = copy.deepcopy(packet)
- self.packets.append(packet)
- return packet
-
- def send_blocking(self, packet):
- packet = self.send(packet)
- while not packet.done:
- yield
-
- def do_simulation(self, selfp):
- if len(self.packets) and self.packet.done:
- self.packet = self.packets.pop(0)
- if not self.packet.ongoing and not self.packet.done:
- selfp.source.stb = 1
- if self.source.description.packetized:
- selfp.source.sop = 1
- selfp.source.data = self.packet.pop(0)
- self.packet.ongoing = True
- elif selfp.source.stb == 1 and selfp.source.ack == 1:
- if self.source.description.packetized:
- selfp.source.sop = 0
- if len(self.packet) == 1:
- selfp.source.eop = 1
- if self.last_be is not None:
- selfp.source.last_be = self.last_be
- else:
- selfp.source.eop = 0
- if self.last_be is not None:
- selfp.source.last_be = 0
- if len(self.packet) > 0:
- selfp.source.stb = 1
- selfp.source.data = self.packet.pop(0)
- else:
- self.packet.done = True
- selfp.source.stb = 0
-
-
-class PacketLogger(Module):
- def __init__(self, description):
- self.sink = Sink(description)
-
- # # #
-
- self.packet = Packet()
-
- def receive(self):
- self.packet.done = False
- while not self.packet.done:
- yield
-
- def do_simulation(self, selfp):
- selfp.sink.ack = 1
- if selfp.sink.stb:
- if self.sink.description.packetized:
- if selfp.sink.sop:
- self.packet = Packet()
- self.packet.append(selfp.sink.data)
- else:
- self.packet.append(selfp.sink.data)
- if selfp.sink.eop:
- self.packet.done = True
- else:
- self.packet.append(selfp.sink.data)
-
-
-class AckRandomizer(Module):
- def __init__(self, description, level=0):
- self.level = level
-
- self.sink = Sink(description)
- self.source = Source(description)
-
- self.run = Signal()
-
- self.comb += \
- If(self.run,
- Record.connect(self.sink, self.source)
- ).Else(
- self.source.stb.eq(0),
- self.sink.ack.eq(0),
- )
-
- def do_simulation(self, selfp):
- n = randn(100)
- if n < self.level:
- selfp.run = 0
- else:
- selfp.run = 1
-
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core import LiteEthUDPIPCore
-from misoclib.com.liteeth.frontend.etherbone import LiteEthEtherbone
-
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp, etherbone
-
-ip_address = 0x12345678
-mac_address = 0x12345678abcd
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.phy_model = phy.PHY(8, debug=False)
- self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
- self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
- self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False)
- self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False)
- self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False)
-
- self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
- self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
-
- self.submodules.sram = wishbone.SRAM(1024)
- self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.master.bus, self.sram.bus)
-
- # use sys_clk for each clock_domain
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_rx.rst.eq(ResetSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal()),
- self.cd_eth_tx.rst.eq(ResetSignal()),
- ]
-
- def gen_simulation(self, selfp):
- selfp.cd_eth_rx.rst = 1
- selfp.cd_eth_tx.rst = 1
- yield
- selfp.cd_eth_rx.rst = 0
- selfp.cd_eth_tx.rst = 0
-
- for i in range(100):
- yield
-
- test_probe = True
- test_writes = True
- test_reads = True
-
- # test probe
- if test_probe:
- packet = etherbone.EtherbonePacket()
- packet.pf = 1
- self.etherbone_model.send(packet)
- yield from self.etherbone_model.receive()
- print("probe: " + str(bool(self.etherbone_model.rx_packet.pr)))
-
- for i in range(8):
- # test writes
- if test_writes:
- writes_datas = [j for j in range(16)]
- writes = etherbone.EtherboneWrites(base_addr=0x1000,
- datas=writes_datas)
- record = etherbone.EtherboneRecord()
- record.writes = writes
- record.reads = None
- record.bca = 0
- record.rca = 0
- record.rff = 0
- record.cyc = 0
- record.wca = 0
- record.wff = 0
- record.byte_enable = 0xf
- record.wcount = len(writes_datas)
- record.rcount = 0
-
- packet = etherbone.EtherbonePacket()
- packet.records = [record]
- self.etherbone_model.send(packet)
- for i in range(256):
- yield
-
- # test reads
- if test_reads:
- reads_addrs = [0x1000 + 4*j for j in range(16)]
- reads = etherbone.EtherboneReads(base_ret_addr=0x1000,
- addrs=reads_addrs)
- record = etherbone.EtherboneRecord()
- record.writes = None
- record.reads = reads
- record.bca = 0
- record.rca = 0
- record.rff = 0
- record.cyc = 0
- record.wca = 0
- record.wff = 0
- record.byte_enable = 0xf
- record.wcount = 0
- record.rcount = len(reads_addrs)
-
- packet = etherbone.EtherbonePacket()
- packet.records = [record]
- self.etherbone_model.send(packet)
- yield from self.etherbone_model.receive()
- loopback_writes_datas = []
- loopback_writes_datas = self.etherbone_model.rx_packet.records.pop().writes.get_datas()
-
- # check results
- s, l, e = check(writes_datas, loopback_writes_datas)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core import LiteEthIPCore
-
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model.dumps import *
-from misoclib.com.liteeth.test.model.mac import *
-from misoclib.com.liteeth.test.model.ip import *
-from misoclib.com.liteeth.test.model.icmp import *
-from misoclib.com.liteeth.test.model import phy, mac, arp, ip, icmp
-
-ip_address = 0x12345678
-mac_address = 0x12345678abcd
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.phy_model = phy.PHY(8, debug=True)
- self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
- self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
- self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False)
- self.submodules.icmp_model = icmp.ICMP(self.ip_model, ip_address, debug=True)
-
- self.submodules.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000)
-
- # use sys_clk for each clock_domain
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_rx.rst.eq(ResetSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal()),
- self.cd_eth_tx.rst.eq(ResetSignal()),
- ]
-
- def gen_simulation(self, selfp):
- selfp.cd_eth_rx.rst = 1
- selfp.cd_eth_tx.rst = 1
- yield
- selfp.cd_eth_rx.rst = 0
- selfp.cd_eth_tx.rst = 0
-
- for i in range(100):
- yield
-
- packet = MACPacket(ping_request)
- packet.decode_remove_header()
- packet = IPPacket(packet)
- packet.decode()
- packet = ICMPPacket(packet)
- packet.decode()
- self.icmp_model.send(packet)
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core import LiteEthIPCore
-
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac, arp, ip
-
-ip_address = 0x12345678
-mac_address = 0x12345678abcd
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.phy_model = phy.PHY(8, debug=False)
- self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
- self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
- self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=True)
-
- self.submodules.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000)
- self.ip_port = self.ip.ip.crossbar.get_port(udp_protocol)
-
- # use sys_clk for each clock_domain
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_rx.rst.eq(ResetSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal()),
- self.cd_eth_tx.rst.eq(ResetSignal()),
- ]
-
- def gen_simulation(self, selfp):
- selfp.cd_eth_rx.rst = 1
- selfp.cd_eth_tx.rst = 1
- yield
- selfp.cd_eth_rx.rst = 0
- selfp.cd_eth_tx.rst = 0
-
- for i in range(100):
- yield
-
- while True:
- selfp.ip_port.sink.stb = 1
- selfp.ip_port.sink.sop = 1
- selfp.ip_port.sink.eop = 1
- selfp.ip_port.sink.ip_address = 0x12345678
- selfp.ip_port.sink.protocol = udp_protocol
-
- selfp.ip_port.source.ack = 1
- if selfp.ip_port.source.stb == 1 and selfp.ip_port.source.sop == 1:
- print("packet from IP 0x{:08x}".format(selfp.ip_port.sink.ip_address))
-
- yield
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
-
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.phy_model = phy.PHY(8, debug=False)
- self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
- self.submodules.core = LiteEthMACCore(phy=self.phy_model, dw=8, with_preamble_crc=True)
-
- self.submodules.streamer = PacketStreamer(eth_phy_description(8), last_be=1)
- self.submodules.streamer_randomizer = AckRandomizer(eth_phy_description(8), level=50)
-
- self.submodules.logger_randomizer = AckRandomizer(eth_phy_description(8), level=50)
- self.submodules.logger = PacketLogger(eth_phy_description(8))
-
- # use sys_clk for each clock_domain
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_rx.rst.eq(ResetSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal()),
- self.cd_eth_tx.rst.eq(ResetSignal()),
- ]
-
- self.comb += [
- Record.connect(self.streamer.source, self.streamer_randomizer.sink),
- Record.connect(self.streamer_randomizer.source, self.core.sink),
- Record.connect(self.core.source, self.logger_randomizer.sink),
- Record.connect(self.logger_randomizer.source, self.logger.sink)
- ]
-
- def gen_simulation(self, selfp):
- selfp.cd_eth_rx.rst = 1
- selfp.cd_eth_tx.rst = 1
- yield
- selfp.cd_eth_rx.rst = 0
- selfp.cd_eth_tx.rst = 0
-
- for i in range(8):
- packet = mac.MACPacket([i for i in range(64)])
- packet.target_mac = 0x010203040506
- packet.sender_mac = 0x090A0B0C0C0D
- packet.ethernet_type = 0x0800
- packet.encode_header()
- yield from self.streamer.send(packet)
- yield from self.logger.receive()
-
- # check results
- s, l, e = check(packet, self.logger.packet)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=4000, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac import LiteEthMAC
-
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac
-
-
-class WishboneMaster:
- def __init__(self, obj):
- self.obj = obj
- self.dat = 0
-
- def write(self, adr, dat):
- self.obj.cyc = 1
- self.obj.stb = 1
- self.obj.adr = adr
- self.obj.we = 1
- self.obj.sel = 0xF
- self.obj.dat_w = dat
- while self.obj.ack == 0:
- yield
- self.obj.cyc = 0
- self.obj.stb = 0
- yield
-
- def read(self, adr):
- self.obj.cyc = 1
- self.obj.stb = 1
- self.obj.adr = adr
- self.obj.we = 0
- self.obj.sel = 0xF
- self.obj.dat_w = 0
- while self.obj.ack == 0:
- yield
- self.dat = self.obj.dat_r
- self.obj.cyc = 0
- self.obj.stb = 0
- yield
-
-
-class SRAMReaderDriver:
- def __init__(self, obj):
- self.obj = obj
-
- def start(self, slot, length):
- self.obj._slot.storage = slot
- self.obj._length.storage = length
- self.obj._start.re = 1
- yield
- self.obj._start.re = 0
- yield
-
- def wait_done(self):
- while self.obj.ev.done.pending == 0:
- yield
-
- def clear_done(self):
- self.obj.ev.done.clear = 1
- yield
- self.obj.ev.done.clear = 0
- yield
-
-
-class SRAMWriterDriver:
- def __init__(self, obj):
- self.obj = obj
-
- def wait_available(self):
- while self.obj.ev.available.pending == 0:
- yield
-
- def clear_available(self):
- self.obj.ev.available.clear = 1
- yield
- self.obj.ev.available.clear = 0
- yield
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.phy_model = phy.PHY(8, debug=False)
- self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
- self.submodules.ethmac = LiteEthMAC(phy=self.phy_model, dw=32, interface="wishbone", with_preamble_crc=True)
-
- # use sys_clk for each clock_domain
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_rx.rst.eq(ResetSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal()),
- self.cd_eth_tx.rst.eq(ResetSignal()),
- ]
-
- def gen_simulation(self, selfp):
- selfp.cd_eth_rx.rst = 1
- selfp.cd_eth_tx.rst = 1
- yield
- selfp.cd_eth_rx.rst = 0
- selfp.cd_eth_tx.rst = 0
-
- wishbone_master = WishboneMaster(selfp.ethmac.bus)
- sram_reader_driver = SRAMReaderDriver(selfp.ethmac.interface.sram.reader)
- sram_writer_driver = SRAMWriterDriver(selfp.ethmac.interface.sram.writer)
-
- sram_writer_slots_offset = [0x000, 0x200]
- sram_reader_slots_offset = [0x400, 0x600]
-
- length = 150+2
-
- tx_payload = [seed_to_data(i, True) % 0xFF for i in range(length)] + [0, 0, 0, 0]
-
- errors = 0
-
- while True:
- for slot in range(2):
- print("slot {}: ".format(slot), end="")
- # fill tx memory
- for i in range(length//4+1):
- dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
- yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
-
- # send tx payload & wait
- yield from sram_reader_driver.start(slot, length)
- yield from sram_reader_driver.wait_done()
- yield from sram_reader_driver.clear_done()
-
- # wait rx
- yield from sram_writer_driver.wait_available()
- yield from sram_writer_driver.clear_available()
-
- # get rx payload (loopback on PHY Model)
- rx_payload = []
- for i in range(length//4+1):
- yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
- dat = wishbone_master.dat
- rx_payload += list(dat.to_bytes(4, byteorder='big'))
-
- # check results
- s, l, e = check(tx_payload[:length], rx_payload[:min(length, len(rx_payload))])
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=3000, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-import math
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
-
-from misoclib.com.liteeth.test.model import mac
-
-
-def print_arp(s):
- print_with_prefix(s, "[ARP]")
-
-preamble = split_bytes(eth_preamble, 8)
-
-
-# ARP model
-class ARPPacket(Packet):
- def __init__(self, init=[]):
- Packet.__init__(self, init)
-
- def decode(self):
- header = []
- for byte in self[:arp_header.length]:
- header.append(self.pop(0))
- for k, v in sorted(arp_header.fields.items()):
- setattr(self, k, get_field_data(v, header))
-
- def encode(self):
- header = 0
- for k, v in sorted(arp_header.fields.items()):
- value = merge_bytes(split_bytes(getattr(self, k),
- math.ceil(v.width/8)),
- "little")
- header += (value << v.offset+(v.byte*8))
- for d in split_bytes(header, arp_header.length):
- self.insert(0, d)
-
- def __repr__(self):
- r = "--------\n"
- for k in sorted(arp_header.fields.keys()):
- r += k + " : 0x{:0x}\n".format(getattr(self, k))
- r += "payload: "
- for d in self:
- r += "{:02x}".format(d)
- return r
-
-
-class ARP(Module):
- def __init__(self, mac, mac_address, ip_address, debug=False):
- self.mac = mac
- self.mac_address = mac_address
- self.ip_address = ip_address
- self.debug = debug
- self.tx_packets = []
- self.tx_packet = ARPPacket()
- self.rx_packet = ARPPacket()
- self.table = {}
- self.request_pending = False
-
- self.mac.set_arp_callback(self.callback)
-
- def send(self, packet):
- packet.encode()
- if self.debug:
- print_arp(">>>>>>>>")
- print_arp(packet)
- mac_packet = mac.MACPacket(packet)
- mac_packet.target_mac = packet.target_mac
- mac_packet.sender_mac = packet.sender_mac
- mac_packet.ethernet_type = ethernet_type_arp
- self.mac.send(mac_packet)
-
- def callback(self, packet):
- packet = ARPPacket(packet)
- packet.decode()
- if self.debug:
- print_arp("<<<<<<<<")
- print_arp(packet)
- self.process(packet)
-
- def process(self, packet):
- if len(packet) != eth_min_len-arp_header.length:
- raise ValueError
- if packet.hwtype != arp_hwtype_ethernet:
- raise ValueError
- if packet.proto != arp_proto_ip:
- raise ValueError
- if packet.hwsize != 6:
- raise ValueError
- if packet.protosize != 4:
- raise ValueError
- if packet.opcode == arp_opcode_request:
- self.process_request(packet)
- elif packet.opcode == arp_opcode_reply:
- self.process_reply(packet)
-
- def process_request(self, request):
- if request.target_ip == self.ip_address:
- reply = ARPPacket([0]*(eth_min_len-arp_header.length))
- reply.hwtype = arp_hwtype_ethernet
- reply.proto = arp_proto_ip
- reply.opcode = arp_opcode_reply
- reply.hwsize = 6
- reply.protosize = 4
- reply.sender_mac = self.mac_address
- reply.sender_ip = self.ip_address
- reply.target_mac = request.sender_mac
- reply.target_ip = request.sender_ip
- self.send(reply)
-
- def process_reply(self, reply):
- self.table[reply.sender_ip] = reply.sender_mac
-
- def request(self, ip_address):
- request = ARPPacket([0]*(eth_min_len-arp_header.length))
- request.hwtype = arp_hwtype_ethernet
- request.proto = arp_proto_ip
- request.opcode = arp_opcode_request
- request.hwsize = 6
- request.protosize = 4
- request.sender_mac = self.mac_address
- request.sender_ip = self.ip_address
- request.target_mac = 0xffffffffffff
- request.target_ip = ip_address
-
-if __name__ == "__main__":
- from misoclib.com.liteeth.test.model.dumps import *
- from misoclib.com.liteeth.test.model.mac import *
- errors = 0
- # ARP request
- packet = MACPacket(arp_request)
- packet.decode_remove_header()
- packet = ARPPacket(packet)
- # check decoding
- packet.decode()
- # print(packet)
- errors += verify_packet(packet, arp_request_infos)
- # check encoding
- packet.encode()
- packet.decode()
- # print(packet)
- errors += verify_packet(packet, arp_request_infos)
-
- # ARP Reply
- packet = MACPacket(arp_reply)
- packet.decode_remove_header()
- packet = ARPPacket(packet)
- # check decoding
- packet.decode()
- # print(packet)
- errors += verify_packet(packet, arp_reply_infos)
- # check encoding
- packet.encode()
- packet.decode()
- # print(packet)
- errors += verify_packet(packet, arp_reply_infos)
-
- print("arp errors " + str(errors))
+++ /dev/null
-import re
-
-
-def format_dump(dump):
- return [int(s, 16) for s in re.split(r'[;,\s\n]\s*', dump) if s is not ""]
-
-
-def verify_packet(packet, infos):
- errors = 0
- for k, v in infos.items():
- if hasattr(packet, k):
- if getattr(packet, k) != v:
- print("[Error] " + k)
- errors += 1
- return errors
-
-arp_request = format_dump("""
-00 22 19 22 54 9e 00 12 3f 97 92 01 08 06 00 01
-08 00 06 04 00 01 00 12 3f 97 92 01 a9 fe ff 42
-00 22 19 22 54 9e a9 fe 64 62""")
-
-arp_request_infos = {
- "sender_mac": 0x00123f979201,
- "target_mac": 0x00221922549e,
- "ethernet_type": 0x806,
- "hwtype": 0x1,
- "opcode": 0x1,
- "protosize": 0x4,
- "proto": 0x800,
- "sender_ip": 0xa9feff42,
- "target_ip": 0xa9fe6462
-
-}
-
-arp_reply = format_dump("""
-00 12 3f 97 92 01 00 22 19 22 54 9e 08 06 00 01
-08 00 06 04 00 02 00 22 19 22 54 9e a9 fe 64 62
-00 12 3f 97 92 01 a9 fe ff 42 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00""")
-
-arp_reply_infos = {
- "sender_mac": 0x00221922549e,
- "target_mac": 0x00123f979201,
- "ethernet_type": 0x806,
- "hwtype": 0x1,
- "opcode": 0x2,
- "protosize": 0x4,
- "proto": 0x800,
- "sender_ip": 0xa9fe6462,
- "target_ip": 0xa9feff42
-}
-
-udp = format_dump("""
-d0 7a b5 96 cd 0a 00 14 0b 33 33 27 08 00 45 00
-00 5f 31 16 00 00 80 11 87 77 c0 a8 01 65 b2 7b
-0d 78 a6 3f 69 0f 00 4b 6a 54 64 31 3a 61 64 32
-3a 69 64 32 30 3a 5a fa 29 99 3a 5e ce 19 d1 8b
-aa 9b 4e 4d f9 2e 51 52 fe ff 65 31 3a 71 34 3a
-70 69 6e 67 31 3a 74 34 3a 85 72 00 00 31 3a 76
-34 3a 55 54 7e 62 31 3a 79 31 3a 71 65""")
-
-udp_infos = {
- "sender_mac": 0x00140b333327,
- "target_mac": 0xd07ab596cd0a,
- "protocol": 0x11,
- "sender_ip": 0xc0a80165,
- "target_ip": 0xb27b0d78,
- "src_port": 0xa63f,
- "dst_port": 0x690f
-}
-
-ping_request = format_dump("""
-00 50 56 e0 14 49 00 0c 29 34 0b de 08 00 45 00
-00 3c d7 43 00 00 80 01 2b 73 c0 a8 9e 8b ae 89
-2a 4d 08 00 2a 5c 02 00 21 00 61 62 63 64 65 66
-67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76
-77 61 62 63 64 65 66 67 68 69""")
-
-ping_request_infos = {
- "code": 0x0,
- "msgtype": 0x8,
- "quench": 0x2002100
-}
-
-ping_reply = format_dump("""
-00 0c 29 34 0b de 00 50 56 e0 14 49 08 00 45 00
-00 3c 76 e1 00 00 80 01 8b d5 ae 89 2a 4d c0 a8
-9e 8b 00 00 32 5c 02 00 21 00 61 62 63 64 65 66
-67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76
-77 61 62 63 64 65 66 67 68 69""")
-
-ping_reply_infos = {}
+++ /dev/null
-import math
-import copy
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
-
-from misoclib.com.liteeth.test.model import udp
-
-
-def print_etherbone(s):
- print_with_prefix(s, "[ETHERBONE]")
-
-
-# Etherbone model
-class EtherboneWrite:
- def __init__(self, data):
- self.data = data
-
- def __repr__(self):
- return "WR32 0x{:08x}".format(self.data)
-
-
-class EtherboneRead:
- def __init__(self, addr):
- self.addr = addr
-
- def __repr__(self):
- return "RD32 @ 0x{:08x}".format(self.addr)
-
-
-class EtherboneWrites(Packet):
- def __init__(self, init=[], base_addr=0, datas=[]):
- Packet.__init__(self, init)
- self.base_addr = base_addr
- self.writes = []
- self.encoded = init != []
- for data in datas:
- self.add(EtherboneWrite(data))
-
- def add(self, write):
- self.writes.append(write)
-
- def get_datas(self):
- datas = []
- for write in self.writes:
- datas.append(write.data)
- return datas
-
- def encode(self):
- if self.encoded:
- raise ValueError
- for byte in split_bytes(self.base_addr, 4):
- self.append(byte)
- for write in self.writes:
- for byte in split_bytes(write.data, 4):
- self.append(byte)
- self.encoded = True
-
- def decode(self):
- if not self.encoded:
- raise ValueError
- base_addr = []
- for i in range(4):
- base_addr.append(self.pop(0))
- self.base_addr = merge_bytes(base_addr)
- self.writes = []
- while len(self) != 0:
- write = []
- for i in range(4):
- write.append(self.pop(0))
- self.writes.append(EtherboneWrite(merge_bytes(write)))
- self.encoded = False
-
- def __repr__(self):
- r = "Writes\n"
- r += "--------\n"
- r += "BaseAddr @ 0x{:08x}\n".format(self.base_addr)
- for write in self.writes:
- r += write.__repr__() + "\n"
- return r
-
-
-class EtherboneReads(Packet):
- def __init__(self, init=[], base_ret_addr=0, addrs=[]):
- Packet.__init__(self, init)
- self.base_ret_addr = base_ret_addr
- self.reads = []
- self.encoded = init != []
- for addr in addrs:
- self.add(EtherboneRead(addr))
-
- def add(self, read):
- self.reads.append(read)
-
- def get_addrs(self):
- addrs = []
- for read in self.reads:
- addrs.append(read.addr)
- return addrs
-
- def encode(self):
- if self.encoded:
- raise ValueError
- for byte in split_bytes(self.base_ret_addr, 4):
- self.append(byte)
- for read in self.reads:
- for byte in split_bytes(read.addr, 4):
- self.append(byte)
- self.encoded = True
-
- def decode(self):
- if not self.encoded:
- raise ValueError
- base_ret_addr = []
- for i in range(4):
- base_ret_addr.append(self.pop(0))
- self.base_ret_addr = merge_bytes(base_ret_addr)
- self.reads = []
- while len(self) != 0:
- read = []
- for i in range(4):
- read.append(self.pop(0))
- self.reads.append(EtherboneRead(merge_bytes(read)))
- self.encoded = False
-
- def __repr__(self):
- r = "Reads\n"
- r += "--------\n"
- r += "BaseRetAddr @ 0x{:08x}\n".format(self.base_ret_addr)
- for read in self.reads:
- r += read.__repr__() + "\n"
- return r
-
-
-class EtherboneRecord(Packet):
- def __init__(self, init=[]):
- Packet.__init__(self, init)
- self.writes = None
- self.reads = None
- self.encoded = init != []
-
- def get_writes(self):
- if self.wcount == 0:
- return None
- else:
- writes = []
- for i in range((self.wcount+1)*4):
- writes.append(self.pop(0))
- return EtherboneWrites(writes)
-
- def get_reads(self):
- if self.rcount == 0:
- return None
- else:
- reads = []
- for i in range((self.rcount+1)*4):
- reads.append(self.pop(0))
- return EtherboneReads(reads)
-
- def decode(self):
- if not self.encoded:
- raise ValueError
- header = []
- for byte in self[:etherbone_record_header.length]:
- header.append(self.pop(0))
- for k, v in sorted(etherbone_record_header.fields.items()):
- setattr(self, k, get_field_data(v, header))
- self.writes = self.get_writes()
- if self.writes is not None:
- self.writes.decode()
- self.reads = self.get_reads()
- if self.reads is not None:
- self.reads.decode()
- self.encoded = False
-
- def set_writes(self, writes):
- self.wcount = len(writes.writes)
- writes.encode()
- for byte in writes:
- self.append(byte)
-
- def set_reads(self, reads):
- self.rcount = len(reads.reads)
- reads.encode()
- for byte in reads:
- self.append(byte)
-
- def encode(self):
- if self.encoded:
- raise ValueError
- if self.writes is not None:
- self.set_writes(self.writes)
- if self.reads is not None:
- self.set_reads(self.reads)
- header = 0
- for k, v in sorted(etherbone_record_header.fields.items()):
- value = merge_bytes(split_bytes(getattr(self, k),
- math.ceil(v.width/8)),
- "little")
- header += (value << v.offset+(v.byte*8))
- for d in split_bytes(header, etherbone_record_header.length):
- self.insert(0, d)
- self.encoded = True
-
- def __repr__(self, n=0):
- r = "Record {}\n".format(n)
- r += "--------\n"
- if self.encoded:
- for d in self:
- r += "{:02x}".format(d)
- else:
- for k in sorted(etherbone_record_header.fields.keys()):
- r += k + " : 0x{:0x}\n".format(getattr(self, k))
- if self.wcount != 0:
- r += self.writes.__repr__()
- if self.rcount != 0:
- r += self.reads.__repr__()
- return r
-
-
-class EtherbonePacket(Packet):
- def __init__(self, init=[]):
- Packet.__init__(self, init)
- self.encoded = init != []
- self.records = []
-
- self.magic = etherbone_magic
- self.version = etherbone_version
- self.addr_size = 32//8
- self.port_size = 32//8
- self.nr = 0
- self.pr = 0
- self.pf = 0
-
- def get_records(self):
- records = []
- done = False
- payload = self
- while len(payload) != 0:
- record = EtherboneRecord(payload)
- record.decode()
- records.append(copy.deepcopy(record))
- payload = record
- return records
-
- def decode(self):
- if not self.encoded:
- raise ValueError
- header = []
- for byte in self[:etherbone_packet_header.length]:
- header.append(self.pop(0))
- for k, v in sorted(etherbone_packet_header.fields.items()):
- setattr(self, k, get_field_data(v, header))
- self.records = self.get_records()
- self.encoded = False
-
- def set_records(self, records):
- for record in records:
- record.encode()
- for byte in record:
- self.append(byte)
-
- def encode(self):
- if self.encoded:
- raise ValueError
- self.set_records(self.records)
- header = 0
- for k, v in sorted(etherbone_packet_header.fields.items()):
- value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
- header += (value << v.offset+(v.byte*8))
- for d in split_bytes(header, etherbone_packet_header.length):
- self.insert(0, d)
- self.encoded = True
-
- def __repr__(self):
- r = "Packet\n"
- r += "--------\n"
- if self.encoded:
- for d in self:
- r += "{:02x}".format(d)
- else:
- for k in sorted(etherbone_packet_header.fields.keys()):
- r += k + " : 0x{:0x}\n".format(getattr(self, k))
- for i, record in enumerate(self.records):
- r += record.__repr__(i)
- return r
-
-
-class Etherbone(Module):
- def __init__(self, udp, debug=False):
- self.udp = udp
- self.debug = debug
- self.tx_packets = []
- self.tx_packet = EtherbonePacket()
- self.rx_packet = EtherbonePacket()
-
- udp.set_etherbone_callback(self.callback)
-
- def send(self, packet):
- packet.encode()
- if self.debug:
- print_etherbone(">>>>>>>>")
- print_etherbone(packet)
- udp_packet = udp.UDPPacket(packet)
- udp_packet.src_port = 0x1234 # XXX
- udp_packet.dst_port = 20000 # XXX
- udp_packet.length = len(packet)
- udp_packet.checksum = 0
- self.udp.send(udp_packet)
-
- def receive(self):
- self.rx_packet = EtherbonePacket()
- while not self.rx_packet.done:
- yield
-
- def callback(self, packet):
- packet = EtherbonePacket(packet)
- packet.decode()
- if self.debug:
- print_etherbone("<<<<<<<<")
- print_etherbone(packet)
- self.rx_packet = packet
- self.rx_packet.done = True
- self.process(packet)
-
- def process(self, packet):
- pass
-
-if __name__ == "__main__":
- # Writes/Reads
- writes = EtherboneWrites(base_addr=0x1000, datas=[i for i in range(16)])
- reads = EtherboneReads(base_ret_addr=0x2000, addrs=[i for i in range(16)])
-
- # Record
- record = EtherboneRecord()
- record.writes = writes
- record.reads = reads
- record.bca = 0
- record.rca = 0
- record.rff = 0
- record.cyc = 0
- record.wca = 0
- record.wff = 0
- record.byte_enable = 0
- record.wcount = len(writes.get_datas())
- record.rcount = len(reads.get_addrs())
-
- # Packet
- packet = EtherbonePacket()
- packet.records = [copy.deepcopy(record) for i in range(8)]
- packet.nr = 0
- packet.pr = 0
- packet.pf = 0
- # print(packet)
- packet.encode()
- # print(packet)
-
- # Send packet over UDP to check against Wireshark dissector
- import socket
- sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
- sock.sendto(bytes(packet), ("192.168.1.1", 20000))
-
- packet = EtherbonePacket(packet)
- packet.decode()
- print(packet)
+++ /dev/null
-import math
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
-
-from misoclib.com.liteeth.test.model import ip
-
-
-def print_icmp(s):
- print_with_prefix(s, "[ICMP]")
-
-
-# ICMP model
-class ICMPPacket(Packet):
- def __init__(self, init=[]):
- Packet.__init__(self, init)
-
- def decode(self):
- header = []
- for byte in self[:icmp_header.length]:
- header.append(self.pop(0))
- for k, v in sorted(icmp_header.fields.items()):
- setattr(self, k, get_field_data(v, header))
-
- def encode(self):
- header = 0
- for k, v in sorted(icmp_header.fields.items()):
- value = merge_bytes(split_bytes(getattr(self, k),
- math.ceil(v.width/8)),
- "little")
- header += (value << v.offset+(v.byte*8))
- for d in split_bytes(header, icmp_header.length):
- self.insert(0, d)
-
- def __repr__(self):
- r = "--------\n"
- for k in sorted(icmp_header.fields.keys()):
- r += k + " : 0x{:0x}\n".format(getattr(self, k))
- r += "payload: "
- for d in self:
- r += "{:02x}".format(d)
- return r
-
-
-class ICMP(Module):
- def __init__(self, ip, ip_address, debug=False):
- self.ip = ip
- self.ip_address = ip_address
- self.debug = debug
- self.tx_packets = []
- self.tx_packet = ICMPPacket()
- self.rx_packet = ICMPPacket()
-
- self.ip.set_icmp_callback(self.callback)
-
- def send(self, packet):
- packet.encode()
- if self.debug:
- print_icmp(">>>>>>>>")
- print_icmp(packet)
- ip_packet = ip.IPPacket(packet)
- ip_packet.version = 0x4
- ip_packet.ihl = 0x5
- ip_packet.total_length = len(packet) + ip_packet.ihl
- ip_packet.identification = 0
- ip_packet.flags = 0
- ip_packet.fragment_offset = 0
- ip_packet.ttl = 0x80
- ip_packet.sender_ip = self.ip_address
- ip_packet.target_ip = 0x12345678 # XXX
- ip_packet.checksum = 0
- ip_packet.protocol = icmp_protocol
- self.ip.send(ip_packet)
-
- def callback(self, packet):
- packet = ICMPPacket(packet)
- packet.decode()
- if self.debug:
- print_icmp("<<<<<<<<")
- print_icmp(packet)
- self.process(packet)
-
- def process(self, packet):
- pass
-
-if __name__ == "__main__":
- from misoclib.com.liteeth.test.model.dumps import *
- from misoclib.com.liteeth.test.model.mac import *
- from misoclib.com.liteeth.test.model.ip import *
- errors = 0
- # ICMP packet
- packet = MACPacket(ping_request)
- packet.decode_remove_header()
- # print(packet)
- packet = IPPacket(packet)
- packet.decode()
- # print(packet)
- packet = ICMPPacket(packet)
- packet.decode()
- # print(packet)
- errors += verify_packet(packet, ping_request_infos)
- packet.encode()
- packet.decode()
- # print(packet)
- errors += verify_packet(packet, ping_request_infos)
-
- print("icmp errors " + str(errors))
+++ /dev/null
-import math
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
-
-from misoclib.com.liteeth.test.model import mac
-
-
-def print_ip(s):
- print_with_prefix(s, "[IP]")
-
-
-def carry_around_add(a, b):
- c = a + b
- return (c & 0xffff) + (c >> 16)
-
-
-def checksum(msg):
- s = 0
- for i in range(0, len(msg), 2):
- w = msg[i] + (msg[i+1] << 8)
- s = carry_around_add(s, w)
- return ~s & 0xffff
-
-
-# IP model
-class IPPacket(Packet):
- def __init__(self, init=[]):
- Packet.__init__(self, init)
-
- def get_checksum(self):
- return self[10] | (self[11] << 8)
-
- def check_checksum(self):
- return checksum(self[:ipv4_header.length]) == 0
-
- def decode(self):
- header = []
- for byte in self[:ipv4_header.length]:
- header.append(self.pop(0))
- for k, v in sorted(ipv4_header.fields.items()):
- setattr(self, k, get_field_data(v, header))
-
- def encode(self):
- header = 0
- for k, v in sorted(ipv4_header.fields.items()):
- value = merge_bytes(split_bytes(getattr(self, k),
- math.ceil(v.width/8)),
- "little")
- header += (value << v.offset+(v.byte*8))
- for d in split_bytes(header, ipv4_header.length):
- self.insert(0, d)
-
- def insert_checksum(self):
- self[10] = 0
- self[11] = 0
- c = checksum(self[:ipv4_header.length])
- self[10] = c & 0xff
- self[11] = (c >> 8) & 0xff
-
- def __repr__(self):
- r = "--------\n"
- for k in sorted(ipv4_header.fields.keys()):
- r += k + " : 0x{:0x}\n".format(getattr(self, k))
- r += "payload: "
- for d in self:
- r += "{:02x}".format(d)
- return r
-
-
-class IP(Module):
- def __init__(self, mac, mac_address, ip_address, debug=False, loopback=False):
- self.mac = mac
- self.mac_address = mac_address
- self.ip_address = ip_address
- self.debug = debug
- self.loopback = loopback
- self.rx_packet = IPPacket()
- self.table = {}
- self.request_pending = False
-
- self.udp_callback = None
- self.icmp_callback = None
-
- self.mac.set_ip_callback(self.callback)
-
- def set_udp_callback(self, callback):
- self.udp_callback = callback
-
- def set_icmp_callback(self, callback):
- self.icmp_callback = callback
-
- def send(self, packet):
- packet.encode()
- packet.insert_checksum()
- if self.debug:
- print_ip(">>>>>>>>")
- print_ip(packet)
- mac_packet = mac.MACPacket(packet)
- mac_packet.target_mac = 0x12345678abcd # XXX
- mac_packet.sender_mac = self.mac_address
- mac_packet.ethernet_type = ethernet_type_ip
- self.mac.send(mac_packet)
-
- def callback(self, packet):
- packet = IPPacket(packet)
- if not packet.check_checksum():
- received = packet.get_checksum()
- packet.insert_checksum()
- expected = packet.get_checksum()
- raise ValueError("Checksum error received {:04x} / expected {:04x}".format(received, expected))
- packet.decode()
- if self.debug:
- print_ip("<<<<<<<<")
- print_ip(packet)
- if self.loopback:
- self.send(packet)
- else:
- if packet.version != 0x4:
- raise ValueError
- if packet.ihl != 0x5:
- raise ValueError
- self.process(packet)
-
- def process(self, packet):
- if packet.protocol == udp_protocol:
- if self.udp_callback is not None:
- self.udp_callback(packet)
- elif packet.protocol == icmp_protocol:
- if self.icmp_callback is not None:
- self.icmp_callback(packet)
-
-if __name__ == "__main__":
- from misoclib.com.liteeth.test.model.dumps import *
- from misoclib.com.liteeth.test.model.mac import *
- errors = 0
- # UDP packet
- packet = MACPacket(udp)
- packet.decode_remove_header()
- # print(packet)
- packet = IPPacket(packet)
- # check decoding
- errors += not packet.check_checksum()
- packet.decode()
- # print(packet)
- errors += verify_packet(packet, {})
- # check encoding
- packet.encode()
- packet.insert_checksum()
- errors += not packet.check_checksum()
- packet.decode()
- # print(packet)
- errors += verify_packet(packet, {})
-
- print("ip errors " + str(errors))
+++ /dev/null
-import math
-import binascii
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
-
-
-def print_mac(s):
- print_with_prefix(s, "[MAC]")
-
-preamble = split_bytes(eth_preamble, 8, "little")
-
-
-def crc32(l):
- crc = []
- crc_bytes = split_bytes(binascii.crc32(bytes(l)), 4, "little")
- for byte in crc_bytes:
- crc.append(int(byte))
- return crc
-
-
-# MAC model
-class MACPacket(Packet):
- def __init__(self, init=[]):
- Packet.__init__(self, init)
- self.preamble_error = False
- self.crc_error = False
-
- def check_remove_preamble(self):
- if comp(self[0:8], preamble):
- for i in range(8):
- self.pop(0)
- return False
- else:
- return True
-
- def check_remove_crc(self):
- if comp(self[-4:], crc32(self[:-4])):
- for i in range(4):
- self.pop()
- return False
- else:
- return True
-
- def decode_remove_header(self):
- header = []
- for byte in self[:mac_header.length]:
- header.append(self.pop(0))
- for k, v in sorted(mac_header.fields.items()):
- setattr(self, k, get_field_data(v, header))
-
- def decode(self):
- self.preamble_error = self.check_remove_preamble()
- self.crc_error = self.check_remove_crc()
- if self.crc_error or self.preamble_error:
- raise ValueError # XXX handle this properly
- else:
- self.decode_remove_header()
-
- def encode_header(self):
- header = 0
- for k, v in sorted(mac_header.fields.items()):
- value = merge_bytes(split_bytes(getattr(self, k),
- math.ceil(v.width/8)),
- "little")
- header += (value << v.offset+(v.byte*8))
- for d in split_bytes(header, mac_header.length):
- self.insert(0, d)
-
- def insert_crc(self):
- for d in crc32(self):
- self.append(d)
-
- def insert_preamble(self):
- for d in reversed(preamble):
- self.insert(0, d)
-
- def encode(self):
- self.encode_header()
- self.insert_crc()
- self.insert_preamble()
-
- def __repr__(self):
- r = "--------\n"
- for k in sorted(mac_header.fields.keys()):
- r += k + " : 0x{:0x}\n".format(getattr(self, k))
- r += "payload: "
- for d in self:
- r += "{:02x}".format(d)
- return r
-
-
-class MAC(Module):
- def __init__(self, phy, debug=False, loopback=False):
- self.phy = phy
- self.debug = debug
- self.loopback = loopback
- self.rx_packet = MACPacket()
-
- self.ip_callback = None
- self.arp_callback = None
-
- phy.set_mac_callback(self.callback)
-
- def set_ip_callback(self, callback):
- self.ip_callback = callback
-
- def set_arp_callback(self, callback):
- self.arp_callback = callback
-
- def send(self, packet):
- if self.debug:
- print_mac(">>>>>>>>")
- print_mac(packet)
- packet.encode()
- self.phy.send(packet)
-
- def callback(self, datas):
- packet = MACPacket(datas)
- packet.decode()
- if self.debug:
- print_mac("<<<<<<<<")
- print_mac(packet)
- if self.loopback:
- self.send(packet)
- else:
- if packet.ethernet_type == ethernet_type_ip:
- if self.ip_callback is not None:
- self.ip_callback(packet)
- elif packet.ethernet_type == ethernet_type_arp:
- if self.arp_callback is not None:
- self.arp_callback(packet)
- else:
- raise ValueError # XXX handle this properly
-
-if __name__ == "__main__":
- from misoclib.com.liteeth.test.model.dumps import *
- errors = 0
- packet = MACPacket(arp_request)
- packet.decode_remove_header()
- # print(packet)
- errors += verify_packet(packet, arp_request_infos)
- packet.encode_header()
- packet.decode_remove_header()
- # print(packet)
- errors += verify_packet(packet, arp_request_infos)
-
- # print(packet)
- packet = MACPacket(arp_reply)
- packet.decode_remove_header()
- errors += verify_packet(packet, arp_reply_infos)
- packet.encode_header()
- packet.decode_remove_header()
- # print(packet)
- errors += verify_packet(packet, arp_reply_infos)
-
- print("mac errors " + str(errors))
+++ /dev/null
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
-
-
-def print_phy(s):
- print_with_prefix(s, "[PHY]")
-
-
-# PHY model
-class PHYSource(PacketStreamer):
- def __init__(self, dw):
- PacketStreamer.__init__(self, eth_phy_description(dw))
-
-
-class PHYSink(PacketLogger):
- def __init__(self, dw):
- PacketLogger.__init__(self, eth_phy_description(dw))
-
-
-class PHY(Module):
- def __init__(self, dw, debug=False):
- self.dw = dw
- self.debug = debug
-
- self.submodules.phy_source = PHYSource(dw)
- self.submodules.phy_sink = PHYSink(dw)
-
- self.source = self.phy_source.source
- self.sink = self.phy_sink.sink
-
- self.mac_callback = None
-
- def set_mac_callback(self, callback):
- self.mac_callback = callback
-
- def send(self, datas):
- packet = Packet(datas)
- if self.debug:
- r = ">>>>>>>>\n"
- r += "length " + str(len(datas)) + "\n"
- for d in datas:
- r += "{:02x}".format(d)
- print_phy(r)
- self.phy_source.send(packet)
-
- def receive(self):
- yield from self.phy_sink.receive()
- if self.debug:
- r = "<<<<<<<<\n"
- r += "length " + str(len(self.phy_sink.packet)) + "\n"
- for d in self.phy_sink.packet:
- r += "{:02x}".format(d)
- print_phy(r)
- self.packet = self.phy_sink.packet
-
- def gen_simulation(self, selfp):
- while True:
- yield from self.receive()
- if self.mac_callback is not None:
- self.mac_callback(self.packet)
+++ /dev/null
-import math
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
-
-from misoclib.com.liteeth.test.model import ip
-
-
-def print_udp(s):
- print_with_prefix(s, "[UDP]")
-
-
-# UDP model
-class UDPPacket(Packet):
- def __init__(self, init=[]):
- Packet.__init__(self, init)
-
- def decode(self):
- header = []
- for byte in self[:udp_header.length]:
- header.append(self.pop(0))
- for k, v in sorted(udp_header.fields.items()):
- setattr(self, k, get_field_data(v, header))
-
- def encode(self):
- header = 0
- for k, v in sorted(udp_header.fields.items()):
- value = merge_bytes(split_bytes(getattr(self, k),
- math.ceil(v.width/8)),
- "little")
- header += (value << v.offset+(v.byte*8))
- for d in split_bytes(header, udp_header.length):
- self.insert(0, d)
-
- def __repr__(self):
- r = "--------\n"
- for k in sorted(udp_header.fields.keys()):
- r += k + " : 0x{:0x}\n".format(getattr(self, k))
- r += "payload: "
- for d in self:
- r += "{:02x}".format(d)
- return r
-
-
-class UDP(Module):
- def __init__(self, ip, ip_address, debug=False, loopback=False):
- self.ip = ip
- self.ip_address = ip_address
- self.debug = debug
- self.loopback = loopback
- self.tx_packets = []
- self.tx_packet = UDPPacket()
- self.rx_packet = UDPPacket()
-
- self.etherbone_callback = None
-
- self.ip.set_udp_callback(self.callback)
-
- def set_etherbone_callback(self, callback):
- self.etherbone_callback = callback
-
- def send(self, packet):
- packet.encode()
- if self.debug:
- print_udp(">>>>>>>>")
- print_udp(packet)
- ip_packet = ip.IPPacket(packet)
- ip_packet.version = 0x4
- ip_packet.ihl = 0x5
- ip_packet.total_length = len(packet) + ip_packet.ihl
- ip_packet.identification = 0
- ip_packet.flags = 0
- ip_packet.fragment_offset = 0
- ip_packet.ttl = 0x80
- ip_packet.sender_ip = self.ip_address
- ip_packet.target_ip = 0x12345678 # XXX
- ip_packet.checksum = 0
- ip_packet.protocol = udp_protocol
- self.ip.send(ip_packet)
-
- def callback(self, packet):
- packet = UDPPacket(packet)
- packet.decode()
- if self.debug:
- print_udp("<<<<<<<<")
- print_udp(packet)
- if self.loopback:
- self.send(packet)
- else:
- self.process(packet)
-
- def process(self, packet):
- if packet.dst_port == 20000:
- if self.etherbone_callback is not None:
- self.etherbone_callback(packet)
-
-if __name__ == "__main__":
- from misoclib.com.liteeth.test.model.dumps import *
- from misoclib.com.liteeth.test.model.mac import *
- from misoclib.com.liteeth.test.model.ip import *
- errors = 0
- # UDP packet
- packet = MACPacket(udp)
- packet.decode_remove_header()
- # print(packet)
- packet = IPPacket(packet)
- packet.decode()
- # print(packet)
- packet = UDPPacket(packet)
- packet.decode()
- # print(packet)
- if packet.length != (len(packet)+udp_header.length):
- errors += 1
- errors += verify_packet(packet, udp_infos)
- packet.encode()
- packet.decode()
- # print(packet)
- if packet.length != (len(packet)+udp_header.length):
- errors += 1
- errors += verify_packet(packet, udp_infos)
-
- print("udp errors " + str(errors))
+++ /dev/null
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
-
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core import LiteEthUDPIPCore
-
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp
-
-ip_address = 0x12345678
-mac_address = 0x12345678abcd
-
-
-class TB(Module):
- def __init__(self, dw=8):
- self.dw = dw
- self.submodules.phy_model = phy.PHY(8, debug=False)
- self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
- self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
- self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False)
- self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True)
-
- self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
- udp_port = self.core.udp.crossbar.get_port(0x5678, dw)
- self.submodules.streamer = PacketStreamer(eth_udp_user_description(dw))
- self.submodules.logger = PacketLogger(eth_udp_user_description(dw))
- self.comb += [
- Record.connect(self.streamer.source, udp_port.sink),
- udp_port.sink.ip_address.eq(0x12345678),
- udp_port.sink.src_port.eq(0x1234),
- udp_port.sink.dst_port.eq(0x5678),
- udp_port.sink.length.eq(64//(dw//8)),
- Record.connect(udp_port.source, self.logger.sink)
- ]
-
- # use sys_clk for each clock_domain
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_rx.rst.eq(ResetSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal()),
- self.cd_eth_tx.rst.eq(ResetSignal()),
- ]
-
- def gen_simulation(self, selfp):
- selfp.cd_eth_rx.rst = 1
- selfp.cd_eth_tx.rst = 1
- yield
- selfp.cd_eth_rx.rst = 0
- selfp.cd_eth_tx.rst = 0
-
- for i in range(100):
- yield
-
- while True:
- packet = Packet([i for i in range(64//(self.dw//8))])
- yield from self.streamer.send(packet)
- yield from self.logger.receive()
-
- # check results
- s, l, e = check(packet, self.logger.packet)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-
-if __name__ == "__main__":
- run_simulation(TB(8), ncycles=2048, vcd_name="my.vcd", keep_files=True)
- run_simulation(TB(16), ncycles=2048, vcd_name="my.vcd", keep_files=True)
- run_simulation(TB(32), ncycles=2048, vcd_name="my.vcd", keep_files=True)
--- /dev/null
+Unless otherwise noted, LiteEth is copyright (C) 2015 Florent Kermarrec.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+Other authors retain ownership of their contributions. If a submission can
+reasonably be considered independently copyrightable, it's yours and we
+encourage you to claim it with appropriate copyright notices. This submission
+then falls under the "otherwise noted" category. All submissions are strongly
+encouraged to use the two-clause BSD license reproduced above.
--- /dev/null
+ __ _ __ ______ __ __ ____ _
+ / / (_) /____ / __/ /_/ / / |/ (_)__ (_)
+ / /__/ / __/ -_) _// __/ _ \/ /|_/ / / _ \/ /
+ /____/_/\__/\__/___/\__/_//_/_/ /_/_/_//_/_/
+
+ Copyright 2012-2015 / EnjoyDigital / M-Labs Ltd
+
+ A small footprint and configurable minimal Ethernet core
+ powered by Migen
+
+[> Intro
+---------
+LiteEthMini is a subset of LiteEth (https://github.com/enjoy-digital/liteeth)
+intended to be used with a CPU and a software stack.
+
+[> Features
+-----------
+- Ethernet MAC with various various PHYs (GMII, MII, RGMII, Loopback)
+- SRAM storage and wishbone interface
+
+[> Possible improvements
+-------------------------
+- add DMA interface to MAC
+- add SGMII PHY
+- ... See below Support and consulting :)
+
+If you want to support these features, please contact us at florent [AT]
+enjoy-digital.fr. You can also contact our partner on the public mailing list
+devel [AT] lists.m-labs.hk.
+
+[> License
+-----------
+LiteEthMini is released under the very permissive two-clause BSD license. Under
+the terms of this license, you are authorized to use LiteEthMini for closed-source
+proprietary designs.
+Even though we do not require you to do so, those things are awesome, so please
+do them if possible:
+ - tell us that you are using LiteEthMini
+ - cite LiteEthMini in publications related to research it has helped
+ - send us feedback and suggestions for improvements
+ - send us bug reports when something goes wrong
+ - send us the modifications and improvements you have done to LiteEthMini.
+
+[> Support and consulting
+--------------------------
+We love open-source hardware and like sharing our designs with others.
+
+LiteEthMini is mainly developed and maintained by EnjoyDigital.
+
+If you would like to know more about LiteEthMini or if you are already a happy
+user and would like to extend it for your needs, EnjoyDigital can provide standard
+commercial support as well as consulting services.
+
+So feel free to contact us, we'd love to work with you! (and eventually shorten
+the list of the possible improvements :)
+
+[> Contact
+E-mail: florent [AT] enjoy-digital.fr
\ No newline at end of file
--- /dev/null
+import math
+from collections import OrderedDict
+
+from migen.fhdl.std import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.record import *
+from migen.genlib.fsm import FSM, NextState
+from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, WaitTimer
+from migen.flow.actor import *
+from migen.actorlib.structuring import Converter, Pipeline
+from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
+from migen.actorlib.packet import *
+from migen.bank.description import *
+
+class Port:
+ def connect(self, port):
+ r = [
+ Record.connect(self.source, port.sink),
+ Record.connect(port.source, self.sink)
+ ]
+ return r
+
+eth_mtu = 1532
+eth_min_len = 46
+eth_interpacket_gap = 12
+eth_preamble = 0xD555555555555555
+buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
+
+def eth_phy_description(dw):
+ payload_layout = [
+ ("data", dw),
+ ("last_be", dw//8),
+ ("error", dw//8)
+ ]
+ return EndpointDescription(payload_layout, packetized=True)
+
+
+def eth_mac_description(dw):
+ payload_layout = mac_header.get_layout() + [
+ ("data", dw),
+ ("last_be", dw//8),
+ ("error", dw//8)
+ ]
+ return EndpointDescription(payload_layout, packetized=True)
--- /dev/null
+from misoclib.com.liteethmini.common import *
+from misoclib.com.liteethmini.mac.core import LiteEthMACCore
+from misoclib.com.liteethmini.mac.frontend.wishbone import LiteEthMACWishboneInterface
+
+
+class LiteEthMAC(Module, AutoCSR):
+ def __init__(self, phy, dw,
+ interface="wishbone",
+ endianness="big",
+ with_preamble_crc=True):
+ self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
+ self.csrs = []
+ if interface == "wishbone":
+ self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
+ self.comb += Port.connect(self.interface, self.core)
+ self.ev, self.bus = self.interface.sram.ev, self.interface.bus
+ self.csrs = self.interface.get_csrs() + self.core.get_csrs()
+ else:
+ raise NotImplementedError
+
+ def get_csrs(self):
+ return self.csrs
--- /dev/null
+from misoclib.com.liteethmini.common import *
+from misoclib.com.liteethmini.mac.core import gap, preamble, crc, padding, last_be
+from misoclib.com.liteethmini.phy.sim import LiteEthPHYSim
+from misoclib.com.liteethmini.phy.mii import LiteEthPHYMII
+
+
+class LiteEthMACCore(Module, AutoCSR):
+ def __init__(self, phy, dw, endianness="big",
+ with_preamble_crc=True,
+ with_padding=True):
+ if dw < phy.dw:
+ raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw))
+
+ rx_pipeline = [phy]
+ tx_pipeline = [phy]
+
+ # Interpacket gap
+ tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
+ rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
+ self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx")
+ self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx")
+
+ tx_pipeline += [tx_gap_inserter]
+ rx_pipeline += [rx_gap_checker]
+
+ # Preamble / CRC
+ if isinstance(phy, LiteEthPHYSim):
+ # In simulation, avoid CRC/Preamble to enable direct connection
+ # to the Ethernet tap.
+ self._preamble_crc = CSRStatus(reset=1)
+ elif with_preamble_crc:
+ self._preamble_crc = CSRStatus(reset=1)
+ # Preamble insert/check
+ preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
+ preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
+ self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
+ self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
+
+ # CRC insert/check
+ crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
+ crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
+ self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
+ self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
+
+ tx_pipeline += [preamble_inserter, crc32_inserter]
+ rx_pipeline += [preamble_checker, crc32_checker]
+
+ # Padding
+ if with_padding:
+ padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
+ padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
+ self.submodules += RenameClockDomains(padding_inserter, "eth_tx")
+ self.submodules += RenameClockDomains(padding_checker, "eth_rx")
+
+ tx_pipeline += [padding_inserter]
+ rx_pipeline += [padding_checker]
+
+ # Delimiters
+ if dw != 8:
+ tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
+ rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
+ self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
+ self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
+
+ tx_pipeline += [tx_last_be]
+ rx_pipeline += [rx_last_be]
+
+ # Converters
+ if dw != phy.dw:
+ reverse = endianness == "big"
+ tx_converter = Converter(eth_phy_description(dw),
+ eth_phy_description(phy.dw),
+ reverse=reverse)
+ rx_converter = Converter(eth_phy_description(phy.dw),
+ eth_phy_description(dw),
+ reverse=reverse)
+ self.submodules += RenameClockDomains(tx_converter, "eth_tx")
+ self.submodules += RenameClockDomains(rx_converter, "eth_rx")
+
+ tx_pipeline += [tx_converter]
+ rx_pipeline += [rx_converter]
+
+ # Cross Domain Crossing
+ if isinstance(phy, LiteEthPHYMII):
+ fifo_depth = 8
+ else:
+ fifo_depth = 64
+ tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
+ rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
+ self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
+ self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
+
+ tx_pipeline += [tx_cdc]
+ rx_pipeline += [rx_cdc]
+
+ # Graph
+ self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline))
+ self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
+
+ self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
--- /dev/null
+from misoclib.com.liteethmini.common import *
+
+
+class LiteEthMACCRCEngine(Module):
+ """Cyclic Redundancy Check Engine
+
+ Compute next CRC value from last CRC value and data input using
+ an optimized asynchronous LFSR.
+
+ Parameters
+ ----------
+ data_width : int
+ Width of the data bus.
+ width : int
+ Width of the CRC.
+ polynom : int
+ Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
+
+ Attributes
+ ----------
+ data : in
+ Data input.
+ last : in
+ last CRC value.
+ next :
+ next CRC value.
+ """
+ def __init__(self, data_width, width, polynom):
+ self.data = Signal(data_width)
+ self.last = Signal(width)
+ self.next = Signal(width)
+
+ # # #
+
+ def _optimize_eq(l):
+ """
+ Replace even numbers of XORs in the equation
+ with an equivalent XOR
+ """
+ d = OrderedDict()
+ for e in l:
+ if e in d:
+ d[e] += 1
+ else:
+ d[e] = 1
+ r = []
+ for key, value in d.items():
+ if value%2 != 0:
+ r.append(key)
+ return r
+
+ # compute and optimize CRC's LFSR
+ curval = [[("state", i)] for i in range(width)]
+ for i in range(data_width):
+ feedback = curval.pop() + [("din", i)]
+ for j in range(width-1):
+ if (polynom & (1<<(j+1))):
+ curval[j] += feedback
+ curval[j] = _optimize_eq(curval[j])
+ curval.insert(0, feedback)
+
+ # implement logic
+ for i in range(width):
+ xors = []
+ for t, n in curval[i]:
+ if t == "state":
+ xors += [self.last[n]]
+ elif t == "din":
+ xors += [self.data[n]]
+ self.comb += self.next[i].eq(optree("^", xors))
+
+
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
+class LiteEthMACCRC32(Module):
+ """IEEE 802.3 CRC
+
+ Implement an IEEE 802.3 CRC generator/checker.
+
+ Parameters
+ ----------
+ data_width : int
+ Width of the data bus.
+
+ Attributes
+ ----------
+ d : in
+ Data input.
+ value : out
+ CRC value (used for generator).
+ error : out
+ CRC error (used for checker).
+ """
+ width = 32
+ polynom = 0x04C11DB7
+ init = 2**width-1
+ check = 0xC704DD7B
+ def __init__(self, data_width):
+ self.data = Signal(data_width)
+ self.value = Signal(self.width)
+ self.error = Signal()
+
+ # # #
+
+ self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
+ reg = Signal(self.width, reset=self.init)
+ self.sync += reg.eq(self.engine.next)
+ self.comb += [
+ self.engine.data.eq(self.data),
+ self.engine.last.eq(reg),
+
+ self.value.eq(~reg[::-1]),
+ self.error.eq(self.engine.next != self.check)
+ ]
+
+
+class LiteEthMACCRCInserter(Module):
+ """CRC Inserter
+
+ Append a CRC at the end of each packet.
+
+ Parameters
+ ----------
+ description : description
+ description of the dataflow.
+
+ Attributes
+ ----------
+ sink : in
+ Packets input without CRC.
+ source : out
+ Packets output with CRC.
+ """
+ def __init__(self, crc_class, description):
+ self.sink = sink = Sink(description)
+ self.source = source = Source(description)
+ self.busy = Signal()
+
+ # # #
+
+ dw = flen(sink.data)
+ crc = crc_class(dw)
+ fsm = FSM(reset_state="IDLE")
+ self.submodules += crc, fsm
+
+ fsm.act("IDLE",
+ crc.reset.eq(1),
+ sink.ack.eq(1),
+ If(sink.stb & sink.sop,
+ sink.ack.eq(0),
+ NextState("COPY"),
+ )
+ )
+ fsm.act("COPY",
+ crc.ce.eq(sink.stb & source.ack),
+ crc.data.eq(sink.data),
+ Record.connect(sink, source),
+ source.eop.eq(0),
+ If(sink.stb & sink.eop & source.ack,
+ NextState("INSERT"),
+ )
+ )
+ ratio = crc.width//dw
+ if ratio > 1:
+ cnt = Signal(max=ratio, reset=ratio-1)
+ cnt_done = Signal()
+ fsm.act("INSERT",
+ source.stb.eq(1),
+ chooser(crc.value, cnt, source.data, reverse=True),
+ If(cnt_done,
+ source.eop.eq(1),
+ If(source.ack, NextState("IDLE"))
+ )
+ )
+ self.comb += cnt_done.eq(cnt == 0)
+ self.sync += \
+ If(fsm.ongoing("IDLE"),
+ cnt.eq(cnt.reset)
+ ).Elif(fsm.ongoing("INSERT") & ~cnt_done,
+ cnt.eq(cnt - source.ack)
+ )
+ else:
+ fsm.act("INSERT",
+ source.stb.eq(1),
+ source.eop.eq(1),
+ source.data.eq(crc.value),
+ If(source.ack, NextState("IDLE"))
+ )
+ self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
+
+
+class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter):
+ def __init__(self, description):
+ LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, description)
+
+
+class LiteEthMACCRCChecker(Module):
+ """CRC Checker
+
+ Check CRC at the end of each packet.
+
+ Parameters
+ ----------
+ description : description
+ description of the dataflow.
+
+ Attributes
+ ----------
+ sink : in
+ Packets input with CRC.
+ source : out
+ Packets output without CRC and "error" set to 0
+ on eop when CRC OK / set to 1 when CRC KO.
+ """
+ def __init__(self, crc_class, description):
+ self.sink = sink = Sink(description)
+ self.source = source = Source(description)
+ self.busy = Signal()
+
+ # # #
+
+ dw = flen(sink.data)
+ crc = crc_class(dw)
+ self.submodules += crc
+ ratio = crc.width//dw
+
+ error = Signal()
+ fifo = InsertReset(SyncFIFO(description, ratio + 1))
+ self.submodules += fifo
+
+ fsm = FSM(reset_state="RESET")
+ self.submodules += fsm
+
+ fifo_in = Signal()
+ fifo_out = Signal()
+ fifo_full = Signal()
+
+ self.comb += [
+ fifo_full.eq(fifo.fifo.level == ratio),
+ fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
+ fifo_out.eq(source.stb & source.ack),
+
+ Record.connect(sink, fifo.sink),
+ fifo.sink.stb.eq(fifo_in),
+ self.sink.ack.eq(fifo_in),
+
+ source.stb.eq(sink.stb & fifo_full),
+ source.sop.eq(fifo.source.sop),
+ source.eop.eq(sink.eop),
+ fifo.source.ack.eq(fifo_out),
+ source.payload.eq(fifo.source.payload),
+
+ source.error.eq(sink.error | crc.error),
+ ]
+
+ fsm.act("RESET",
+ crc.reset.eq(1),
+ fifo.reset.eq(1),
+ NextState("IDLE"),
+ )
+ self.comb += crc.data.eq(sink.data)
+ fsm.act("IDLE",
+ If(sink.stb & sink.sop & sink.ack,
+ crc.ce.eq(1),
+ NextState("COPY")
+ )
+ )
+ fsm.act("COPY",
+ If(sink.stb & sink.ack,
+ crc.ce.eq(1),
+ If(sink.eop,
+ NextState("RESET")
+ )
+ )
+ )
+ self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
+
+
+class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):
+ def __init__(self, description):
+ LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, description)
--- /dev/null
+from misoclib.com.liteethmini.common import *
+
+class LiteEthMACGap(Module):
+ def __init__(self, dw, ack_on_gap=False):
+ self.sink = sink = Sink(eth_phy_description(dw))
+ self.source = source = Source(eth_phy_description(dw))
+
+ # # #
+
+ gap = math.ceil(eth_interpacket_gap/(dw//8))
+ self.submodules.counter = counter = Counter(max=gap)
+
+ self.submodules.fsm = fsm = FSM(reset_state="COPY")
+ fsm.act("COPY",
+ counter.reset.eq(1),
+ Record.connect(sink, source),
+ If(sink.stb & sink.eop & sink.ack,
+ NextState("GAP")
+ )
+ )
+ fsm.act("GAP",
+ counter.ce.eq(1),
+ sink.ack.eq(int(ack_on_gap)),
+ If(counter.value == (gap-1),
+ NextState("COPY")
+ )
+ )
--- /dev/null
+from misoclib.com.liteethmini.common import *
+
+
+class LiteEthMACTXLastBE(Module):
+ def __init__(self, dw):
+ self.sink = sink = Sink(eth_phy_description(dw))
+ self.source = source = Source(eth_phy_description(dw))
+
+ # # #
+
+ ongoing = Signal()
+ self.sync += \
+ If(sink.stb & sink.ack,
+ If(sink.sop,
+ ongoing.eq(1)
+ ).Elif(sink.last_be,
+ ongoing.eq(0)
+ )
+ )
+ self.comb += [
+ source.stb.eq(sink.stb & (sink.sop | ongoing)),
+ source.sop.eq(sink.sop),
+ source.eop.eq(sink.last_be),
+ source.data.eq(sink.data),
+ sink.ack.eq(source.ack)
+ ]
+
+
+class LiteEthMACRXLastBE(Module):
+ def __init__(self, dw):
+ self.sink = sink = Sink(eth_phy_description(dw))
+ self.source = source = Source(eth_phy_description(dw))
+
+ # # #
+
+ self.comb += [
+ source.stb.eq(sink.stb),
+ source.sop.eq(sink.sop),
+ source.eop.eq(sink.eop),
+ source.data.eq(sink.data),
+ source.last_be.eq(sink.eop),
+ sink.ack.eq(source.ack)
+ ]
--- /dev/null
+from misoclib.com.liteethmini.common import *
+
+
+class LiteEthMACPaddingInserter(Module):
+ def __init__(self, dw, padding):
+ self.sink = sink = Sink(eth_phy_description(dw))
+ self.source = source = Source(eth_phy_description(dw))
+
+ # # #
+
+ padding_limit = math.ceil(padding/(dw/8))-1
+
+ self.submodules.counter = counter = Counter(16, reset=1)
+ counter_done = Signal()
+ self.comb += [
+ counter.reset.eq(sink.stb & sink.sop & sink.ack),
+ counter.ce.eq(source.stb & source.ack),
+ counter_done.eq(counter.value >= padding_limit),
+ ]
+
+ self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+ fsm.act("IDLE",
+ Record.connect(sink, source),
+ If(source.stb & source.ack,
+ counter.ce.eq(1),
+ If(sink.eop,
+ If(~counter_done,
+ source.eop.eq(0),
+ NextState("PADDING")
+ )
+ )
+ )
+ )
+ fsm.act("PADDING",
+ source.stb.eq(1),
+ source.eop.eq(counter_done),
+ source.data.eq(0),
+ If(source.ack,
+ If(counter_done,
+ NextState("IDLE")
+ )
+ )
+ )
+
+
+class LiteEthMACPaddingChecker(Module):
+ def __init__(self, dw, packet_min_length):
+ self.sink = sink = Sink(eth_phy_description(dw))
+ self.source = source = Source(eth_phy_description(dw))
+
+ # # #
+
+ # XXX see if we should drop the packet when
+ # payload size < minimum ethernet payload size
+ self.comb += Record.connect(sink, source)
+
--- /dev/null
+from misoclib.com.liteethmini.common import *
+
+
+class LiteEthMACPreambleInserter(Module):
+ def __init__(self, dw):
+ self.sink = Sink(eth_phy_description(dw))
+ self.source = Source(eth_phy_description(dw))
+
+ # # #
+
+ preamble = Signal(64, reset=eth_preamble)
+ cnt_max = (64//dw)-1
+ cnt = Signal(max=cnt_max+1)
+ clr_cnt = Signal()
+ inc_cnt = Signal()
+
+ self.sync += \
+ If(clr_cnt,
+ cnt.eq(0)
+ ).Elif(inc_cnt,
+ cnt.eq(cnt+1)
+ )
+
+ fsm = FSM(reset_state="IDLE")
+ self.submodules += fsm
+ fsm.act("IDLE",
+ self.sink.ack.eq(1),
+ clr_cnt.eq(1),
+ If(self.sink.stb & self.sink.sop,
+ self.sink.ack.eq(0),
+ NextState("INSERT"),
+ )
+ )
+ fsm.act("INSERT",
+ self.source.stb.eq(1),
+ self.source.sop.eq(cnt == 0),
+ chooser(preamble, cnt, self.source.data),
+ If(cnt == cnt_max,
+ If(self.source.ack, NextState("COPY"))
+ ).Else(
+ inc_cnt.eq(self.source.ack)
+ )
+ )
+
+ self.comb += [
+ self.source.data.eq(self.sink.data),
+ self.source.last_be.eq(self.sink.last_be)
+ ]
+ fsm.act("COPY",
+ Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
+ self.source.sop.eq(0),
+
+ If(self.sink.stb & self.sink.eop & self.source.ack,
+ NextState("IDLE"),
+ )
+ )
+
+
+class LiteEthMACPreambleChecker(Module):
+ def __init__(self, dw):
+ self.sink = Sink(eth_phy_description(dw))
+ self.source = Source(eth_phy_description(dw))
+
+ # # #
+
+ preamble = Signal(64, reset=eth_preamble)
+ cnt_max = (64//dw) - 1
+ cnt = Signal(max=cnt_max+1)
+ clr_cnt = Signal()
+ inc_cnt = Signal()
+
+ self.sync += \
+ If(clr_cnt,
+ cnt.eq(0)
+ ).Elif(inc_cnt,
+ cnt.eq(cnt+1)
+ )
+
+ discard = Signal()
+ clr_discard = Signal()
+ set_discard = Signal()
+
+ self.sync += \
+ If(clr_discard,
+ discard.eq(0)
+ ).Elif(set_discard,
+ discard.eq(1)
+ )
+
+ sop = Signal()
+ clr_sop = Signal()
+ set_sop = Signal()
+ self.sync += \
+ If(clr_sop,
+ sop.eq(0)
+ ).Elif(set_sop,
+ sop.eq(1)
+ )
+
+ ref = Signal(dw)
+ match = Signal()
+ self.comb += [
+ chooser(preamble, cnt, ref),
+ match.eq(self.sink.data == ref)
+ ]
+
+ fsm = FSM(reset_state="IDLE")
+ self.submodules += fsm
+
+ fsm.act("IDLE",
+ self.sink.ack.eq(1),
+ clr_cnt.eq(1),
+ clr_discard.eq(1),
+ If(self.sink.stb & self.sink.sop,
+ clr_cnt.eq(0),
+ inc_cnt.eq(1),
+ clr_discard.eq(0),
+ set_discard.eq(~match),
+ NextState("CHECK"),
+ )
+ )
+ fsm.act("CHECK",
+ self.sink.ack.eq(1),
+ If(self.sink.stb,
+ set_discard.eq(~match),
+ If(cnt == cnt_max,
+ If(discard | (~match),
+ NextState("IDLE")
+ ).Else(
+ set_sop.eq(1),
+ NextState("COPY")
+ )
+ ).Else(
+ inc_cnt.eq(1)
+ )
+ )
+ )
+ self.comb += [
+ self.source.data.eq(self.sink.data),
+ self.source.last_be.eq(self.sink.last_be)
+ ]
+ fsm.act("COPY",
+ Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
+ self.source.sop.eq(sop),
+ clr_sop.eq(self.source.stb & self.source.ack),
+
+ If(self.source.stb & self.source.eop & self.source.ack,
+ NextState("IDLE"),
+ )
+ )
--- /dev/null
+from misoclib.com.liteethmini.common import *
+
+from migen.bank.description import *
+from migen.bank.eventmanager import *
+
+
+class LiteEthMACSRAMWriter(Module, AutoCSR):
+ def __init__(self, dw, depth, nslots=2):
+ self.sink = sink = Sink(eth_phy_description(dw))
+ self.crc_error = Signal()
+
+ slotbits = max(log2_int(nslots), 1)
+ lengthbits = log2_int(depth*4) # length in bytes
+
+ self._slot = CSRStatus(slotbits)
+ self._length = CSRStatus(lengthbits)
+
+ self.submodules.ev = EventManager()
+ self.ev.available = EventSourceLevel()
+ self.ev.finalize()
+
+ # # #
+
+ # packet dropped if no slot available
+ sink.ack.reset = 1
+
+ # length computation
+ increment = Signal(3)
+ self.comb += \
+ If(sink.last_be[3],
+ increment.eq(1)
+ ).Elif(sink.last_be[2],
+ increment.eq(2)
+ ).Elif(sink.last_be[1],
+ increment.eq(3)
+ ).Else(
+ increment.eq(4)
+ )
+ counter = Counter(lengthbits, increment=increment)
+ self.submodules += counter
+
+ # slot computation
+ slot = Counter(slotbits)
+ self.submodules += slot
+
+ ongoing = Signal()
+
+ # status fifo
+ fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
+ self.submodules += fifo
+
+ # fsm
+ fsm = FSM(reset_state="IDLE")
+ self.submodules += fsm
+
+ fsm.act("IDLE",
+ If(sink.stb & sink.sop,
+ If(fifo.sink.ack,
+ ongoing.eq(1),
+ counter.ce.eq(1),
+ NextState("WRITE")
+ )
+ )
+ )
+ fsm.act("WRITE",
+ counter.ce.eq(sink.stb),
+ ongoing.eq(1),
+ If(sink.stb & sink.eop,
+ If((sink.error & sink.last_be) != 0,
+ NextState("DISCARD")
+ ).Else(
+ NextState("TERMINATE")
+ )
+ )
+ )
+ fsm.act("DISCARD",
+ counter.reset.eq(1),
+ NextState("IDLE")
+ )
+ self.comb += [
+ fifo.sink.slot.eq(slot.value),
+ fifo.sink.length.eq(counter.value)
+ ]
+ fsm.act("TERMINATE",
+ counter.reset.eq(1),
+ slot.ce.eq(1),
+ fifo.sink.stb.eq(1),
+ NextState("IDLE")
+ )
+ self.comb += [
+ fifo.source.ack.eq(self.ev.available.clear),
+ self.ev.available.trigger.eq(fifo.source.stb),
+ self._slot.status.eq(fifo.source.slot),
+ self._length.status.eq(fifo.source.length),
+ ]
+
+ # memory
+ mems = [None]*nslots
+ ports = [None]*nslots
+ for n in range(nslots):
+ mems[n] = Memory(dw, depth)
+ ports[n] = mems[n].get_port(write_capable=True)
+ self.specials += ports[n]
+ self.mems = mems
+
+ cases = {}
+ for n, port in enumerate(ports):
+ cases[n] = [
+ ports[n].adr.eq(counter.value[2:]),
+ ports[n].dat_w.eq(sink.data),
+ If(sink.stb & ongoing,
+ ports[n].we.eq(0xf)
+ )
+ ]
+ self.comb += Case(slot.value, cases)
+
+
+class LiteEthMACSRAMReader(Module, AutoCSR):
+ def __init__(self, dw, depth, nslots=2):
+ self.source = source = Source(eth_phy_description(dw))
+
+ slotbits = max(log2_int(nslots), 1)
+ lengthbits = log2_int(depth*4) # length in bytes
+ self.lengthbits = lengthbits
+
+ self._start = CSR()
+ self._ready = CSRStatus()
+ self._slot = CSRStorage(slotbits)
+ self._length = CSRStorage(lengthbits)
+
+ self.submodules.ev = EventManager()
+ self.ev.done = EventSourcePulse()
+ self.ev.finalize()
+
+ # # #
+
+ # command fifo
+ fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
+ self.submodules += fifo
+ self.comb += [
+ fifo.sink.stb.eq(self._start.re),
+ fifo.sink.slot.eq(self._slot.storage),
+ fifo.sink.length.eq(self._length.storage),
+ self._ready.status.eq(fifo.sink.ack)
+ ]
+
+ # length computation
+ self.submodules.counter = counter = Counter(lengthbits, increment=4)
+
+ # fsm
+ first = Signal()
+ last = Signal()
+ last_d = Signal()
+
+ fsm = FSM(reset_state="IDLE")
+ self.submodules += fsm
+
+ fsm.act("IDLE",
+ counter.reset.eq(1),
+ If(fifo.source.stb,
+ NextState("CHECK")
+ )
+ )
+ fsm.act("CHECK",
+ If(~last_d,
+ NextState("SEND"),
+ ).Else(
+ NextState("END"),
+ )
+ )
+ length_lsb = fifo.source.length[0:2]
+ self.comb += [
+ If(last,
+ If(length_lsb == 3,
+ source.last_be.eq(0b0010)
+ ).Elif(length_lsb == 2,
+ source.last_be.eq(0b0100)
+ ).Elif(length_lsb == 1,
+ source.last_be.eq(0b1000)
+ ).Else(
+ source.last_be.eq(0b0001)
+ )
+ )
+ ]
+ fsm.act("SEND",
+ source.stb.eq(1),
+ source.sop.eq(first),
+ source.eop.eq(last),
+ If(source.ack,
+ counter.ce.eq(~last),
+ NextState("CHECK")
+ )
+ )
+ fsm.act("END",
+ fifo.source.ack.eq(1),
+ self.ev.done.trigger.eq(1),
+ NextState("IDLE")
+ )
+
+ # first/last computation
+ self.sync += [
+ If(fsm.ongoing("IDLE"),
+ first.eq(1)
+ ).Elif(source.stb & source.ack,
+ first.eq(0)
+ )
+ ]
+ self.comb += last.eq((counter.value + 4) >= fifo.source.length)
+ self.sync += last_d.eq(last)
+
+ # memory
+ rd_slot = fifo.source.slot
+
+ mems = [None]*nslots
+ ports = [None]*nslots
+ for n in range(nslots):
+ mems[n] = Memory(dw, depth)
+ ports[n] = mems[n].get_port()
+ self.specials += ports[n]
+ self.mems = mems
+
+ cases = {}
+ for n, port in enumerate(ports):
+ self.comb += ports[n].adr.eq(counter.value[2:])
+ cases[n] = [source.data.eq(port.dat_r)]
+ self.comb += Case(rd_slot, cases)
+
+
+class LiteEthMACSRAM(Module, AutoCSR):
+ def __init__(self, dw, depth, nrxslots, ntxslots):
+ self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots)
+ self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots)
+ self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
+ self.sink, self.source = self.writer.sink, self.reader.source
--- /dev/null
+from misoclib.com.liteethmini.common import *
+from misoclib.com.liteethmini.mac.frontend import sram
+
+from migen.bus import wishbone
+from migen.fhdl.simplify import FullMemoryWE
+
+
+class LiteEthMACWishboneInterface(Module, AutoCSR):
+ def __init__(self, dw, nrxslots=2, ntxslots=2):
+ self.sink = Sink(eth_phy_description(dw))
+ self.source = Source(eth_phy_description(dw))
+ self.bus = wishbone.Interface()
+
+ # # #
+
+ # storage in SRAM
+ sram_depth = buffer_depth//(dw//8)
+ self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots)
+ self.comb += [
+ Record.connect(self.sink, self.sram.sink),
+ Record.connect(self.sram.source, self.source)
+ ]
+
+ # Wishbone interface
+ wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True)
+ for n in range(nrxslots)]
+ # TODO: FullMemoryWE should move to Mibuild
+ wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
+ for n in range(ntxslots)]
+ wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
+
+ wb_slaves = []
+ decoderoffset = log2_int(sram_depth)
+ decoderbits = log2_int(len(wb_sram_ifs))
+ for n, wb_sram_if in enumerate(wb_sram_ifs):
+ def slave_filter(a, v=n):
+ return a[decoderoffset:decoderoffset+decoderbits] == v
+ wb_slaves.append((slave_filter, wb_sram_if.bus))
+ self.submodules += wb_sram_if
+ wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
+ self.submodules += wb_con
--- /dev/null
+from misoclib.com.liteethmini.common import *
+
+
+def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
+ # Autodetect PHY
+ if hasattr(pads, "source_stb"):
+ # This is a simulation PHY
+ from misoclib.com.liteethmini.phy.sim import LiteEthPHYSim
+ return LiteEthPHYSim(pads)
+ elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
+ if hasattr(clock_pads, "tx"):
+ # This is a 10/100/1G PHY
+ from misoclib.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII
+ return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
+ else:
+ # This is a pure 1G PHY
+ from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMII
+ return LiteEthPHYGMII(clock_pads, pads, **kwargs)
+ elif hasattr(pads, "rx_ctl"):
+ # This is a 10/100/1G RGMII PHY
+ raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
+ elif flen(pads.tx_data) == 4:
+ # This is a MII PHY
+ from misoclib.com.liteethmini.phy.mii import LiteEthPHYMII
+ return LiteEthPHYMII(clock_pads, pads, **kwargs)
+ else:
+ raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation")
--- /dev/null
+from migen.genlib.io import DDROutput
+
+from misoclib.com.liteethmini.common import *
+
+
+class LiteEthPHYGMIITX(Module):
+ def __init__(self, pads, pads_register=True):
+ self.sink = sink = Sink(eth_phy_description(8))
+
+ # # #
+
+ if hasattr(pads, "tx_er"):
+ self.sync += pads.tx_er.eq(0)
+ pads_eq = [
+ pads.tx_en.eq(sink.stb),
+ pads.tx_data.eq(sink.data)
+ ]
+ if pads_register:
+ self.sync += pads_eq
+ else:
+ self.comb += pads_eq
+ self.comb += sink.ack.eq(1)
+
+
+class LiteEthPHYGMIIRX(Module):
+ def __init__(self, pads):
+ self.source = source = Source(eth_phy_description(8))
+
+ # # #
+
+ dv_d = Signal()
+ self.sync += dv_d.eq(pads.dv)
+
+ sop = Signal()
+ eop = Signal()
+ self.comb += [
+ sop.eq(pads.dv & ~dv_d),
+ eop.eq(~pads.dv & dv_d)
+ ]
+ self.sync += [
+ source.stb.eq(pads.dv),
+ source.sop.eq(sop),
+ source.data.eq(pads.rx_data)
+ ]
+ self.comb += source.eop.eq(eop)
+
+
+class LiteEthPHYGMIICRG(Module, AutoCSR):
+ def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
+ self._reset = CSRStorage()
+
+ # # #
+
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+
+ # RX : Let the synthesis tool insert the appropriate clock buffer
+ self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
+
+ # TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused
+ # MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
+ self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
+ # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
+ self.specials += Instance("BUFGMUX",
+ i_I0=self.cd_eth_rx.clk,
+ i_I1=clock_pads.tx,
+ i_S=mii_mode,
+ o_O=self.cd_eth_tx.clk)
+
+ if with_hw_init_reset:
+ reset = Signal()
+ counter_done = Signal()
+ self.submodules.counter = counter = Counter(max=512)
+ self.comb += [
+ counter_done.eq(counter.value == 256),
+ counter.ce.eq(~counter_done),
+ reset.eq(~counter_done | self._reset.storage)
+ ]
+ else:
+ reset = self._reset.storage
+ self.comb += pads.rst_n.eq(~reset)
+ self.specials += [
+ AsyncResetSynchronizer(self.cd_eth_tx, reset),
+ AsyncResetSynchronizer(self.cd_eth_rx, reset),
+ ]
+
+
+class LiteEthPHYGMII(Module, AutoCSR):
+ def __init__(self, clock_pads, pads, with_hw_init_reset=True):
+ self.dw = 8
+ self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
+ pads,
+ with_hw_init_reset)
+ self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
+ "eth_tx")
+ self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
+ "eth_rx")
+ self.sink, self.source = self.tx.sink, self.rx.source
--- /dev/null
+from migen.genlib.io import DDROutput
+from migen.flow.plumbing import Multiplexer, Demultiplexer
+from migen.genlib.cdc import PulseSynchronizer
+
+from misoclib.com.liteethmini.common import *
+
+from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMIICRG
+from misoclib.com.liteethmini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
+from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
+
+modes = {
+ "GMII": 0,
+ "MII": 1
+}
+
+tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
+rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)]
+
+
+class LiteEthPHYGMIIMIITX(Module):
+ def __init__(self, pads, mode):
+ self.sink = sink = Sink(eth_phy_description(8))
+
+ # # #
+
+ gmii_tx_pads = Record(tx_pads_layout)
+ gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False)
+ self.submodules += gmii_tx
+
+ mii_tx_pads = Record(tx_pads_layout)
+ mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False)
+ self.submodules += mii_tx
+
+ demux = Demultiplexer(eth_phy_description(8), 2)
+ self.submodules += demux
+ self.comb += [
+ demux.sel.eq(mode == modes["MII"]),
+ Record.connect(sink, demux.sink),
+ Record.connect(demux.source0, gmii_tx.sink),
+ Record.connect(demux.source1, mii_tx.sink),
+ ]
+
+ if hasattr(pads, "tx_er"):
+ self.comb += pads.tx_er.eq(0)
+ self.sync += [
+ If(mode == modes["MII"],
+ pads.tx_en.eq(mii_tx_pads.tx_en),
+ pads.tx_data.eq(mii_tx_pads.tx_data),
+ ).Else(
+ pads.tx_en.eq(gmii_tx_pads.tx_en),
+ pads.tx_data.eq(gmii_tx_pads.tx_data),
+ )
+ ]
+
+
+class LiteEthPHYGMIIMIIRX(Module):
+ def __init__(self, pads, mode):
+ self.source = source = Source(eth_phy_description(8))
+
+ # # #
+
+ pads_d = Record(rx_pads_layout)
+ self.sync += [
+ pads_d.dv.eq(pads.dv),
+ pads_d.rx_data.eq(pads.rx_data)
+ ]
+
+ gmii_rx = LiteEthPHYGMIIRX(pads_d)
+ self.submodules += gmii_rx
+
+ mii_rx = LiteEthPHYMIIRX(pads_d)
+ self.submodules += mii_rx
+
+ mux = Multiplexer(eth_phy_description(8), 2)
+ self.submodules += mux
+ self.comb += [
+ mux.sel.eq(mode == modes["MII"]),
+ Record.connect(gmii_rx.source, mux.sink0),
+ Record.connect(mii_rx.source, mux.sink1),
+ Record.connect(mux.source, source)
+ ]
+
+
+class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
+ def __init__(self, clk_freq):
+ self.mode = Signal()
+ self._mode = CSRStatus()
+
+ # # #
+
+ mode = Signal()
+ update_mode = Signal()
+ self.sync += \
+ If(update_mode,
+ self.mode.eq(mode)
+ )
+ self.comb += self._mode.status.eq(self.mode)
+
+ # Principle:
+ # sys_clk >= 125MHz
+ # eth_rx <= 125Mhz
+ # We generate ticks every 1024 clock cycles in eth_rx domain
+ # and measure ticks period in sys_clk domain.
+
+ # Generate a tick every 1024 clock cycles (eth_rx clock domain)
+ eth_tick = Signal()
+ eth_counter = Signal(10)
+ self.sync.eth_rx += eth_counter.eq(eth_counter + 1)
+ self.comb += eth_tick.eq(eth_counter == 0)
+
+ # Synchronize tick (sys clock domain)
+ sys_tick = Signal()
+ eth_ps = PulseSynchronizer("eth_rx", "sys")
+ self.comb += [
+ eth_ps.i.eq(eth_tick),
+ sys_tick.eq(eth_ps.o)
+ ]
+ self.submodules += eth_ps
+
+ # sys_clk domain counter
+ sys_counter = Counter(24)
+ self.submodules += sys_counter
+
+ fsm = FSM(reset_state="IDLE")
+ self.submodules += fsm
+
+ fsm.act("IDLE",
+ sys_counter.reset.eq(1),
+ If(sys_tick,
+ NextState("COUNT")
+ )
+ )
+ fsm.act("COUNT",
+ sys_counter.ce.eq(1),
+ If(sys_tick,
+ NextState("DETECTION")
+ )
+ )
+ fsm.act("DETECTION",
+ update_mode.eq(1),
+ # if freq < 125MHz-5% use MII mode
+ If(sys_counter.value > int((clk_freq/125000000)*1024*1.05),
+ mode.eq(1)
+ # if freq >= 125MHz-5% use GMII mode
+ ).Else(
+ mode.eq(0)
+ ),
+ NextState("IDLE")
+ )
+
+
+class LiteEthPHYGMIIMII(Module, AutoCSR):
+ def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
+ self.dw = 8
+ # Note: we can use GMII CRG since it also handles tx clock pad used for MII
+ self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
+ mode = self.mode_detection.mode
+ self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
+ self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
+ self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")
+ self.sink, self.source = self.tx.sink, self.rx.source
--- /dev/null
+from misoclib.com.liteethmini.common import *
+from misoclib.com.liteethmini.generic import *
+
+
+class LiteEthPHYLoopbackCRG(Module, AutoCSR):
+ def __init__(self):
+ self._reset = CSRStorage()
+
+ # # #
+
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+ self.comb += [
+ self.cd_eth_rx.clk.eq(ClockSignal()),
+ self.cd_eth_tx.clk.eq(ClockSignal())
+ ]
+
+ reset = self._reset.storage
+ self.comb += [
+ self.cd_eth_rx.rst.eq(reset),
+ self.cd_eth_tx.rst.eq(reset)
+ ]
+
+
+class LiteEthPHYLoopback(Module, AutoCSR):
+ def __init__(self):
+ self.dw = 8
+ self.submodules.crg = LiteEthLoopbackPHYCRG()
+ self.sink = sink = Sink(eth_phy_description(8))
+ self.source = source = Source(eth_phy_description(8))
+ self.comb += Record.connect(self.sink, self.source)
--- /dev/null
+from misoclib.com.liteethmini.common import *
+
+
+def converter_description(dw):
+ payload_layout = [("data", dw)]
+ return EndpointDescription(payload_layout, packetized=True)
+
+
+class LiteEthPHYMIITX(Module):
+ def __init__(self, pads, pads_register=True):
+ self.sink = sink = Sink(eth_phy_description(8))
+
+ # # #
+
+ if hasattr(pads, "tx_er"):
+ self.sync += pads.tx_er.eq(0)
+ converter = Converter(converter_description(8),
+ converter_description(4))
+ self.submodules += converter
+ self.comb += [
+ converter.sink.stb.eq(sink.stb),
+ converter.sink.data.eq(sink.data),
+ sink.ack.eq(converter.sink.ack),
+ converter.source.ack.eq(1)
+ ]
+ pads_eq = [
+ pads.tx_en.eq(converter.source.stb),
+ pads.tx_data.eq(converter.source.data)
+ ]
+ if pads_register:
+ self.sync += pads_eq
+ else:
+ self.comb += pads_eq
+
+
+class LiteEthPHYMIIRX(Module):
+ def __init__(self, pads):
+ self.source = source = Source(eth_phy_description(8))
+
+ # # #
+
+ sop = FlipFlop(reset=1)
+ self.submodules += sop
+
+ converter = Converter(converter_description(4),
+ converter_description(8))
+ converter = InsertReset(converter)
+ self.submodules += converter
+
+ self.sync += [
+ converter.reset.eq(~pads.dv),
+ converter.sink.stb.eq(1),
+ converter.sink.data.eq(pads.rx_data)
+ ]
+ self.comb += [
+ sop.reset.eq(~pads.dv),
+ sop.ce.eq(pads.dv),
+ converter.sink.sop.eq(sop.q),
+ converter.sink.eop.eq(~pads.dv)
+ ]
+ self.comb += Record.connect(converter.source, source)
+
+
+class LiteEthPHYMIICRG(Module, AutoCSR):
+ def __init__(self, clock_pads, pads, with_hw_init_reset):
+ self._reset = CSRStorage()
+
+ # # #
+
+ if hasattr(clock_pads, "phy"):
+ self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
+
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+ self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
+ self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
+
+ if with_hw_init_reset:
+ reset = Signal()
+ counter_done = Signal()
+ self.submodules.counter = counter = Counter(max=512)
+ self.comb += [
+ counter_done.eq(counter.value == 256),
+ counter.ce.eq(~counter_done),
+ reset.eq(~counter_done | self._reset.storage)
+ ]
+ else:
+ reset = self._reset.storage
+ self.comb += pads.rst_n.eq(~reset)
+ self.specials += [
+ AsyncResetSynchronizer(self.cd_eth_tx, reset),
+ AsyncResetSynchronizer(self.cd_eth_rx, reset),
+ ]
+
+
+class LiteEthPHYMII(Module, AutoCSR):
+ def __init__(self, clock_pads, pads, with_hw_init_reset=True):
+ self.dw = 8
+ self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
+ self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
+ self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
+ self.sink, self.source = self.tx.sink, self.rx.source
--- /dev/null
+# RGMII PHY for Spartan-6
+
+from migen.genlib.io import DDROutput
+from migen.genlib.misc import WaitTimer
+from migen.genlib.fsm import FSM, NextState
+
+from misoclib.com.liteethmini.common import *
+
+
+class LiteEthPHYRGMIITX(Module):
+ def __init__(self, pads, pads_register=True):
+ self.sink = sink = Sink(eth_phy_description(8))
+
+ # # #
+
+ self.specials += Instance("ODDR2",
+ p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
+ i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"),
+ i_CE=1, i_S=0, i_R=0,
+ i_D0=sink.stb, i_D1=sink.stb, o_Q=pads.tx_ctl,
+ )
+ for i in range(4):
+ self.specials += Instance("ODDR2",
+ p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
+ i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"),
+ i_CE=1, i_S=0, i_R=0,
+ i_D0=sink.data[i], i_D1=sink.data[4+i], o_Q=pads.tx_data[i],
+ )
+ self.comb += sink.ack.eq(1)
+
+
+class LiteEthPHYRGMIIRX(Module):
+ def __init__(self, pads):
+ self.source = source = Source(eth_phy_description(8))
+
+ # # #
+
+ rx_ctl = Signal()
+ rx_data = Signal(8)
+
+ self.specials += Instance("IDDR2",
+ p_DDR_ALIGNMENT="C0", p_INIT_Q0=0, p_INIT_Q1=0, p_SRTYPE="ASYNC",
+ i_C0=ClockSignal("eth_rx"), i_C1=~ClockSignal("eth_rx"),
+ i_CE=1, i_S=0, i_R=0,
+ i_D=pads.rx_ctl, o_Q1=rx_ctl,
+ )
+ for i in range(4):
+ self.specials += Instance("IDDR2",
+ p_DDR_ALIGNMENT="C0", p_INIT_Q0=0, p_INIT_Q1=0, p_SRTYPE="ASYNC",
+ i_C0=ClockSignal("eth_rx"), i_C1=~ClockSignal("eth_rx"),
+ i_CE=1, i_S=0, i_R=0,
+ i_D=pads.rx_data[i], o_Q0=rx_data[4+i], o_Q1=rx_data[i],
+ )
+
+
+ rx_ctl_d = Signal()
+ self.sync += rx_ctl_d.eq(rx_ctl)
+
+ sop = Signal()
+ eop = Signal()
+ self.comb += [
+ sop.eq(rx_ctl & ~rx_ctl_d),
+ eop.eq(~rx_ctl & rx_ctl_d)
+ ]
+ self.sync += [
+ source.stb.eq(rx_ctl),
+ source.sop.eq(sop),
+ source.data.eq(rx_data)
+ ]
+ self.comb += source.eop.eq(eop)
+
+
+class LiteEthPHYRGMIICRG(Module, AutoCSR):
+ def __init__(self, clock_pads, pads, with_hw_init_reset):
+ self._reset = CSRStorage()
+
+ # # #
+
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+
+
+ # RX
+ dcm_reset = Signal()
+ dcm_locked = Signal()
+
+ timer = WaitTimer(1024)
+ fsm = FSM(reset_state="DCM_RESET")
+ self.submodules += timer, fsm
+
+ fsm.act("DCM_RESET",
+ dcm_reset.eq(1),
+ timer.wait.eq(1),
+ If(timer.done,
+ timer.wait.eq(0),
+ NextState("DCM_WAIT")
+ )
+ )
+ fsm.act("DCM_WAIT",
+ timer.wait.eq(1),
+ If(timer.done,
+ NextState("DCM_CHECK_LOCK")
+ )
+ )
+ fsm.act("DCM_CHECK_LOCK",
+ If(~dcm_locked,
+ NextState("DCM_RESET")
+ )
+ )
+
+ clk90_rx = Signal()
+ clk0_rx = Signal()
+ clk0_rx_bufg = Signal()
+ self.specials += Instance("DCM",
+ i_CLKIN=clock_pads.rx,
+ i_CLKFB=clk0_rx_bufg,
+ o_CLK0=clk0_rx,
+ o_CLK90=clk90_rx,
+ o_LOCKED=dcm_locked,
+ i_PSEN=0,
+ i_PSCLK=0,
+ i_PSINCDEC=0,
+ i_RST=dcm_reset
+ )
+
+ self.specials += Instance("BUFG", i_I=clk0_rx, o_O=clk0_rx_bufg)
+ self.specials += Instance("BUFG", i_I=clk90_rx, o_O=self.cd_eth_rx.clk)
+
+ # TX
+ self.specials += DDROutput(1, 0, clock_pads.tx, ClockSignal("eth_tx"))
+ self.specials += Instance("BUFG", i_I=self.cd_eth_rx.clk, o_O=self.cd_eth_tx.clk)
+
+ # Reset
+ if with_hw_init_reset:
+ reset = Signal()
+ counter_done = Signal()
+ self.submodules.counter = counter = Counter(max=512)
+ self.comb += [
+ counter_done.eq(counter.value == 256),
+ counter.ce.eq(~counter_done),
+ reset.eq(~counter_done | self._reset.storage)
+ ]
+ else:
+ reset = self._reset.storage
+ self.comb += pads.rst_n.eq(~reset)
+ self.specials += [
+ AsyncResetSynchronizer(self.cd_eth_tx, reset),
+ AsyncResetSynchronizer(self.cd_eth_rx, reset),
+ ]
+
+
+class LiteEthPHYRGMII(Module, AutoCSR):
+ def __init__(self, clock_pads, pads, with_hw_init_reset=True):
+ self.dw = 8
+ self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
+ pads,
+ with_hw_init_reset)
+ self.submodules.tx = RenameClockDomains(LiteEthPHYRGMIITX(pads),
+ "eth_tx")
+ self.submodules.rx = RenameClockDomains(LiteEthPHYRGMIIRX(pads),
+ "eth_rx")
+ self.sink, self.source = self.tx.sink, self.rx.source
--- /dev/null
+import os
+
+from misoclib.com.liteethmini.common import *
+
+
+class LiteEthPHYSimCRG(Module, AutoCSR):
+ def __init__(self):
+ self._reset = CSRStorage()
+
+ # # #
+
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+ self.comb += [
+ self.cd_eth_rx.clk.eq(ClockSignal()),
+ self.cd_eth_tx.clk.eq(ClockSignal())
+ ]
+
+ reset = self._reset.storage
+ self.comb += [
+ self.cd_eth_rx.rst.eq(reset),
+ self.cd_eth_tx.rst.eq(reset)
+ ]
+
+
+class LiteEthPHYSim(Module, AutoCSR):
+ def __init__(self, pads, tap="tap0", ip_address="192.168.0.14"):
+ self.dw = 8
+ self.submodules.crg = LiteEthPHYSimCRG()
+ self.sink = sink = Sink(eth_phy_description(8))
+ self.source = source = Source(eth_phy_description(8))
+ self.tap = tap
+ self.ip_address = ip_address
+
+ self.comb += [
+ pads.source_stb.eq(self.sink.stb),
+ pads.source_data.eq(self.sink.data),
+ self.sink.ack.eq(1)
+ ]
+
+ self.sync += [
+ self.source.stb.eq(pads.sink_stb),
+ self.source.sop.eq(pads.sink_stb & ~self.source.stb),
+ self.source.data.eq(pads.sink_data),
+ ]
+ self.comb += [
+ self.source.eop.eq(~pads.sink_stb & self.source.stb),
+ ]
+
+ # XXX avoid use of os.system
+ os.system("openvpn --mktun --dev {}".format(self.tap))
+ os.system("ifconfig {} {} up".format(self.tap, self.ip_address))
+ os.system("mknod /dev/net/{} c 10 200".format(self.tap))
+
+ def do_exit(self, *args, **kwargs):
+ # XXX avoid use of os.system
+ os.system("rm -f /dev/net/{}".format(self.tap))
+ os.system("openvpn --rmtun --dev {}".format(self.tap))
from misoclib.soc import mem_decoder
from misoclib.soc.sdram import SDRAMSoC
-from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.core.mac import LiteEthMAC
+from misoclib.com.liteethmini.phy import LiteEthPHY
+from misoclib.com.liteethmini.mac import LiteEthMAC
class _CRG(Module):
from misoclib.soc import mem_decoder
from misoclib.soc.sdram import SDRAMSoC
from misoclib.com import gpio
-from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.core.mac import LiteEthMAC
+from misoclib.com.liteethmini.phy import LiteEthPHY
+from misoclib.com.liteethmini.mac import LiteEthMAC
class _MXCRG(Module):
from migen.genlib.io import CRG
from misoclib.soc import SoC, mem_decoder
-from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.core.mac import LiteEthMAC
+from misoclib.com.liteethmini.phy import LiteEthPHY
+from misoclib.com.liteethmini.mac import LiteEthMAC
class BaseSoC(SoC):
projects / litex.git / commitdiff
