utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically...

diff --git a/litex/utils/litex_sim.py b/litex/utils/litex_sim.py
index 4e6eb88dc289ed6e8efb4d8a2b4192206b5bc732..868dbb19724e895354b0280d4d4093a68cf1480d 100755 (executable)
--- a/litex/utils/litex_sim.py
+++ b/litex/utils/litex_sim.py
@@ -218,11 +218,11 @@ def main():
     if args.rom_init:
         soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
     if not args.with_sdram:
-        soc_kwargs["integrated_main_ram_size"] = 0x10000
+        soc_kwargs["integrated_main_ram_size"] = 0x1000000 # 256 MB
         if args.ram_init is not None:
             soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
-            soc_kwargs["integrated_main_ram_size"] = max(len(soc_kwargs["integrated_main_ram_init"]), 0x10000)
     else:
+        assert args.ram_init is None
         soc_kwargs["integrated_main_ram_size"] = 0x0
     if args.with_ethernet:
         sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
@@ -235,6 +235,8 @@ def main():
         with_etherbone=args.with_etherbone,
         with_analyzer=args.with_analyzer,
         **soc_kwargs)
+    if args.ram_init is not None:
+        soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
     builder_kwargs["csr_csv"] = "csr.csv"
     builder = Builder(soc, **builder_kwargs)
     vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace)